From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49DFB1F4190; Tue, 8 Jul 2025 17:34:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; cv=none; b=FV3yDbjmu4B0TZgtcLGtPuVzOhyEAlgl3K+hbMMTsf6PdqeQCy1WY+1/p0BfpuGiITZWudIBa/5dBqrMpcgykeOMnzORwskJq4rTsoOxmgwe98r0TyN+FMKoqotiL7W+zNldzkgOMY6rDkgh8EwWZNg2ctKkSYsuR7w62ILvn98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; c=relaxed/simple; bh=eO//bdZjML2f/yBZKp3pfm6LXOZ7G6limhAcR80kGHA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BQmG8lvA7LyFuWPmeqbXgOmC+/vi/KlLjJLCaI2buGzYXMTrAz94kHW558/M9MfUTd7Lj1+ZL0KGfizc4mcf5YBbx90BbNUXPJsABnF90gO/HLafH0nRq4Pa7J+hUbaWofxJfvajZIhrDyaSThbAPGoPkkhsdxeZ/l3FfoNBvTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=q1uXX1a9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="q1uXX1a9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8B06C4CEED; Tue, 8 Jul 2025 17:34:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751996050; bh=eO//bdZjML2f/yBZKp3pfm6LXOZ7G6limhAcR80kGHA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q1uXX1a9l+I8CG9FADpHMOcZ3yd7vIohUDkbLuCoFJL29a5uBH6HmBitz7BcBI3Pi 22oA/96TYkhn4RUhUWX/1AuGTw1UEdedkbTuR4ds/nZcEI8eqap3HSrUksWw+bXvxD Ci0oxoqFkzjbVGl7W79dh5RmobXurAXbrGOPIi7W6yS+sR8P557cfhMY1/kCqEdG7e ejVw4rq7LRZnzLHmLG4QXdw88ixV07LXBNqGqCXSqCvvRdPbISzyf9EGKtj6Bh9BLO N3GdHsSMbf3pI5s0Zjn2VJ2baD2cXY1tUYDOHRIqI0Ke6kIAxBkKVg/YwEQ8MiARpg rNZVXwjCv1HjA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZCCm-00Dqhw-Pt; Tue, 08 Jul 2025 18:34:08 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 01/13] genirq: Teach handle_simple_irq() to resend an in-progress interrupt Date: Tue, 8 Jul 2025 18:33:52 +0100 Message-Id: <20250708173404.1278635-2-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" It appears that the defect outlined in 9c15eeb5362c4 ("genirq: Allow fasteoi handler to resend interrupts on concurrent handling") also affects some other less stellar MSI controllers, this time using the handle_simple_irq() flow. Teach this flow about irqd_needs_resend_when_in_progress(). Given the invasive nature of this workaround, only this flow is updated. Reviewed-by: Thomas Gleixner Signed-off-by: Marc Zyngier --- kernel/irq/chip.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 2b274007e8bab..6e789035919f7 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -559,7 +559,13 @@ void handle_simple_irq(struct irq_desc *desc) { guard(raw_spinlock)(&desc->lock); =20 - if (!irq_can_handle(desc)) + if (!irq_can_handle_pm(desc)) { + if (irqd_needs_resend_when_in_progress(&desc->irq_data)) + desc->istate |=3D IRQS_PENDING; + return; + } + + if (!irq_can_handle_actions(desc)) return; =20 kstat_incr_irqs_this_cpu(desc); --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A14522126E; Tue, 8 Jul 2025 17:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; cv=none; b=XjKDuA++TGXphJZTTsh8ayWO2IPlSf1AYgW1Zg7EmY7eBy88UO7DuegNbZq8jGhRAeIzdmYDz770EYNzPCSnWcqVtKE+R4WdG3ETI28GlGnNVAFCuCNSEkc0djeES8nZuUHozwsjfNPNQICMkms5ug+Nd8aCpdk4cRRn6loPFYA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; c=relaxed/simple; bh=9TTQFkyY0M8aTj6Iv8cpYI5ilm3sw2M2ZI3G1K0Exkc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qANJaxvx6/K43vrBAFU55qEL+TYupRZeq+rzngEabPkHE06Z3QuhuHKTQ8qYfTQmkZ+kZuS3tkmBHHUM5S0qAlIa41XXEGJGJHnnvIkm+orL0uJOWdZG8xUhIlK4aAzbd5ZAKomORNshhiTjMxNTvDs1kMCVyQO2Lr69zr+cftI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iqsZbG6u; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iqsZbG6u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 150EBC4CEFD; Tue, 8 Jul 2025 17:34:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751996051; bh=9TTQFkyY0M8aTj6Iv8cpYI5ilm3sw2M2ZI3G1K0Exkc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iqsZbG6u6KjiRwauw+wclsVudQEywuNtzdpxpn9C7bV2B/q34vHG1nRvzKPrOf7CO tOPDOmb0riqbgd1/sb0Qcuko+/844q1IXjDGb5xKRW25oqg1XpLTNXM7M3SAXv/0lD ZbMwN64WXLItvlpolw3jhC+rPTi+LFJWdqns9ftjFrCWk1scsd81YbWVvAxPvhw6J9 c/VSdHAukMex41O+ZBO545kPBfkxNddAQJdIGrMQMZrZ7Y73+CfLOCoZFy+UvJHyYn EdvpxrE85zkkyb3TAXTXTYwcmSdjX4KlITmtZJ7vG1H7YU+ZGG4GMI1sjQ71Dx7qmO PsGhljKqrlMrg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZCCn-00Dqhw-0H; Tue, 08 Jul 2025 18:34:09 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 02/13] PCI: xgene: Defer probing if the MSI widget driver hasn't probed yet Date: Tue, 8 Jul 2025 18:33:53 +0100 Message-Id: <20250708173404.1278635-3-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" As a preparatory work to make the XGene MSI driver probe less of a sorry hack, make the PCI driver check for the availability of the MSI parent domain, and defer the probing otherwise. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pc= i-xgene.c index 1e2ebbfa36d19..f26cb58f814ec 100644 --- a/drivers/pci/controller/pci-xgene.c +++ b/drivers/pci/controller/pci-xgene.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -594,6 +595,24 @@ static struct pci_ops xgene_pcie_ops =3D { .write =3D pci_generic_config_write32, }; =20 +static bool xgene_check_pcie_msi_ready(void) +{ + struct device_node *np; + struct irq_domain *d; + + if (!IS_ENABLED(CONFIG_PCI_XGENE_MSI)) + return true; + + np =3D of_find_compatible_node(NULL, NULL, "apm,xgene1-msi"); + if (!np) + return true; + + d =3D irq_find_matching_host(np, DOMAIN_BUS_PCI_MSI); + of_node_put(np); + + return d && irq_domain_is_msi_parent(d); +} + static int xgene_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -602,6 +621,10 @@ static int xgene_pcie_probe(struct platform_device *pd= ev) struct pci_host_bridge *bridge; int ret; =20 + if (!xgene_check_pcie_msi_ready()) + return dev_err_probe(&pdev->dev, -EPROBE_DEFER, + "MSI driver not ready\n"); + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*port)); if (!bridge) return -ENOMEM; --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A1B32DC33D; Tue, 8 Jul 2025 17:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; cv=none; b=OanZa6CqEkkM+Ydc9YwMfJwqBOsStpOq7Kh6DVRQHQpoAyT8gCy+MTAwPtL2soxRjen/V8/HkRKllpGH9mvPdrG8RQWULirLtsCTQ8GXiJmD+BrK8teo73FBvH4uQ8WbDyUjIwIlQE2a4iF1bhEI7hvWjpKpGfnBLIByQEVnU4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; c=relaxed/simple; bh=XyHVZgTEEU9jeG0R0aHxp6hZU2S5LzzIaxTXL9QhFBI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Gd4RWa7FR/eLO38N+rHa6m/co7Nwu/8rUYfnEANeUuhlZE0vrULQwOB5rghruUl4WkO8ZEdPa8DZ3tKt1EHcmsPC6jT2blZzL/SnPVkbf7A9nH4Xmj8X+gpAQ3foGW6R6GrwNgE7EjlFejB87IhN1/i7BxMXER+06NkdwcfGCm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KZEa4lmr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KZEa4lmr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06B6DC4CEFA; Tue, 8 Jul 2025 17:34:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751996051; bh=XyHVZgTEEU9jeG0R0aHxp6hZU2S5LzzIaxTXL9QhFBI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KZEa4lmr/XbpSiQfqy9xVJlRrLxqSoRb3TAE4WOf6rxiPDcBTlnNnN2iPqVPYdIgx LxHD93E78a9QAQkE6f13GM83mP3T7mCyGtUwmDAztFgFWVcls4LfUMsJjQKvw9LOe9 S/0z/mp3EjrLkCaN/KNt9Uxsf2IOz5lxRpn/k1N862bCadwfdyv7zqCti1h+sy6Of0 81c9jVULtaOrKRJ0YejX3n2bRkO7EsfZUCXyPoM760hSwaBv56rVOucwjcLO7hPH9V huv2Gff272VBr8LbUwKy3BKnkk/5mbDwQxHDt1Zi7Fh6bbGVAaYg4sGM4kfYlsNY90 BtMnq0bMi0zoQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZCCn-00Dqhw-6d; Tue, 08 Jul 2025 18:34:09 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 03/13] PCI: xgene: Drop useless conditional compilation Date: Tue, 8 Jul 2025 18:33:54 +0100 Message-Id: <20250708173404.1278635-4-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" pci-xgene.c only gets compiled if CONFIG_PCI_XGENE is selected. It is therefore pointless to check for CONFIG_PCI_XGENE inside the driver. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pc= i-xgene.c index f26cb58f814ec..a848f98203ae4 100644 --- a/drivers/pci/controller/pci-xgene.c +++ b/drivers/pci/controller/pci-xgene.c @@ -58,7 +58,6 @@ #define XGENE_PCIE_IP_VER_1 1 #define XGENE_PCIE_IP_VER_2 2 =20 -#if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_P= CI_QUIRKS)) struct xgene_pcie { struct device_node *node; struct device *dev; @@ -189,7 +188,6 @@ static int xgene_pcie_config_read32(struct pci_bus *bus= , unsigned int devfn, =20 return PCIBIOS_SUCCESSFUL; } -#endif =20 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) static int xgene_get_csr_resource(struct acpi_device *adev, @@ -280,7 +278,6 @@ const struct pci_ecam_ops xgene_v2_pcie_ecam_ops =3D { }; #endif =20 -#if defined(CONFIG_PCI_XGENE) static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr, u32 flags, u64 size) { @@ -670,4 +667,3 @@ static struct platform_driver xgene_pcie_driver =3D { .probe =3D xgene_pcie_probe, }; builtin_platform_driver(xgene_pcie_driver); -#endif --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB2782E6D0A; Tue, 8 Jul 2025 17:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; cv=none; b=FBTuuNZp4DRP0jiS041vnd8a9psh5uEu/GJnSdbdKzRFQ534wzHKeSORbUf0DydbXbGWfmpQ7ul9gC9QoHKpokQ5jE3t82BJLtONHcQwf2M4v9Tm1zA8/voB5T0ELSXthCljb5NWS+XVRWiZvimd+Uw++3orYQ4bWIfsB/U3fiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; c=relaxed/simple; bh=zWAmwKnV6f1cwbtaUPgrJ1lIE+Rc2XJQ33KR+f1+GBg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Tc3ilkt5pJE9/R15uxyQUshoAHScteWBP6aNV2kq+0wrpMUS6FDSXVpd5neqyiQmjrOk3sAXDo0bmhcV7ip4Vtenvj8y48sUA+TaNlfzXMsb9NjGPYMJt8K61FrAU0Ykd6WUUBsWmZw68pWhGhqOClqIi9SlpL1+p0cdsIz0R2M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lk6AEc+p; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lk6AEc+p" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 748F6C4CEED; Tue, 8 Jul 2025 17:34:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751996051; bh=zWAmwKnV6f1cwbtaUPgrJ1lIE+Rc2XJQ33KR+f1+GBg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lk6AEc+pwSSa+6W1orB9UPtYr+5as8dQlcw92PkFHIS9ReJX4+jIoRaoNLr8bWezK 24hexua/XsO18wygcvBn01f2hMKsjWl57Es0lBicNtMBk5NjcAjusqioZQSqop7z6n WAN7jspqfMTFam6mkvcxJVISPIo+e2NoRJoBbD2AISWrzl7IJq68Hr8rPmalWtkP2f KkX31v8A5O5ky7TvJnvk+MlRLNLOyMzghVn6vqRYUamnSKYjLbCSDrchGyBz8Ejo5/ HhndG0C7xCxtKycWWmGUo172CXRemaj7NwZbgKAeaPYIpazxAWiK6ZmblPx0xXRQpY XNPzgMNdNijJg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZCCn-00Dqhw-Ch; Tue, 08 Jul 2025 18:34:09 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 04/13] PCI: xgene: Drop XGENE_PCIE_IP_VER_UNKN Date: Tue, 8 Jul 2025 18:33:55 +0100 Message-Id: <20250708173404.1278635-5-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" XGENE_PCIE_IP_VER_UNKN is only refered to when probing for the original XGene PCIe implementation, and get immediately overridden if the device has the "apm,xgene-pcie" compatible string. Given that the only way to get there is by finding this very string in the DT, it is obvious that we will always ovwrite the version with XGENE_PCIE_IP_VER_1. Drop the whole thing. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pc= i-xgene.c index a848f98203ae4..b95afa35201d0 100644 --- a/drivers/pci/controller/pci-xgene.c +++ b/drivers/pci/controller/pci-xgene.c @@ -54,7 +54,6 @@ #define XGENE_V1_PCI_EXP_CAP 0x40 =20 /* PCIe IP version */ -#define XGENE_PCIE_IP_VER_UNKN 0 #define XGENE_PCIE_IP_VER_1 1 #define XGENE_PCIE_IP_VER_2 2 =20 @@ -630,10 +629,7 @@ static int xgene_pcie_probe(struct platform_device *pd= ev) =20 port->node =3D of_node_get(dn); port->dev =3D dev; - - port->version =3D XGENE_PCIE_IP_VER_UNKN; - if (of_device_is_compatible(port->node, "apm,xgene-pcie")) - port->version =3D XGENE_PCIE_IP_VER_1; + port->version =3D XGENE_PCIE_IP_VER_1; =20 ret =3D xgene_pcie_map_reg(port, pdev); if (ret) --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4B5B2E613E; Tue, 8 Jul 2025 17:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; cv=none; b=IeY3fMOHsb0VmLxtFxfWJ0GV98/3n4b+3OE32JzHvsYlDLt/RfZ90K4sWD2yhyeUuQOgPpnbQvIH8OAJmpZZyt3X9uUzwD/D6jWwrAqYnAC7RIwyKNYCXHSv5yWk2QBT5vUKK5shNvNx8LhJuWhHLVvGDJNxeDc4Iv1FXRfM9Ds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996051; c=relaxed/simple; bh=GcwbIHtYH5IvK/ZrsZkV+WGzeAfxODsrDBcp9MXIE4E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NDzICw5TEV7cDeRCpPBKAOx2+axVwORRSc5zGOTjtppp19jUotG3JtcT7XkE+5QJ+O1TnLi+vSFWtwowBKi3Wk6p3KXxvelGmi/rT5orlYnte4cNHAhaACzG3yTFy3Jf3s4KL0sd78n9RbBIB7XDk2MCbi0pvmQVzJAoM8LXfSw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s1Ms+XLB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s1Ms+XLB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7AB03C4CEF5; Tue, 8 Jul 2025 17:34:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751996051; bh=GcwbIHtYH5IvK/ZrsZkV+WGzeAfxODsrDBcp9MXIE4E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s1Ms+XLBKvaS6OLuasxkeCVmVMNaniPuw3GhOy2cJ3HVI1Rugquyb9GV4YaJ0MCZD 3Slu0C668w5WomxBFMOFzNjSfRWETgcuXVgCHVG2blIykmf6cK842u8ZxJoF9UWQ1I mRNknRykoC5zeVFaOFjyz4AUL+eOqP8IdZ4m+C6wYsEuGX3WakAmmf43a7QYnrzt+b gE9AAXRktxyXwCXf+D6oexvGl1cFXL3HBbblrEWD/Pw6tf0GcrXDJL/AxV1XaCyURg 52KoHQBxdOTW+i3O1KuYhF+WRZdJYt+ITtNTxqrsFe6bpmG4QcT5cgMScAaffvQaGO 0PrXnMGGAgN7Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZCCn-00Dqhw-Ix; Tue, 08 Jul 2025 18:34:09 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 05/13] PCI: xgene-msi: Make per-CPU interrupt setup robust Date: Tue, 8 Jul 2025 18:33:56 +0100 Message-Id: <20250708173404.1278635-6-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" The way the per-CPU interrupts are dealt with in the XGene MSI driver isn't great: - the affinity is set after the interrupt is enabled - nothing prevents userspace from moving the interrupt around - the affinity setting code pointlessly allocates memory - the driver checks for conditions that cannot possibly happen Address all of this in one go, resulting in slightly simpler setup code. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene-msi.c | 29 ++++++-------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index b05ec8b0bb93f..5b69286689177 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -355,40 +355,26 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu) { struct xgene_msi *msi =3D &xgene_msi_ctrl; struct xgene_msi_group *msi_group; - cpumask_var_t mask; int i; int err; =20 for (i =3D cpu; i < NR_HW_IRQS; i +=3D msi->num_cpus) { msi_group =3D &msi->msi_groups[i]; - if (!msi_group->gic_irq) - continue; - - irq_set_chained_handler_and_data(msi_group->gic_irq, - xgene_msi_isr, msi_group); =20 /* * Statically allocate MSI GIC IRQs to each CPU core. * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated * to each core. */ - if (alloc_cpumask_var(&mask, GFP_KERNEL)) { - cpumask_clear(mask); - cpumask_set_cpu(cpu, mask); - err =3D irq_set_affinity(msi_group->gic_irq, mask); - if (err) - pr_err("failed to set affinity for GIC IRQ"); - free_cpumask_var(mask); - } else { - pr_err("failed to alloc CPU mask for affinity\n"); - err =3D -EINVAL; - } - + irq_set_status_flags(msi_group->gic_irq, IRQ_NO_BALANCING); + err =3D irq_set_affinity(msi_group->gic_irq, cpumask_of(cpu)); if (err) { - irq_set_chained_handler_and_data(msi_group->gic_irq, - NULL, NULL); + pr_err("failed to set affinity for GIC IRQ"); return err; } + + irq_set_chained_handler_and_data(msi_group->gic_irq, + xgene_msi_isr, msi_group); } =20 return 0; @@ -402,9 +388,6 @@ static int xgene_msi_hwirq_free(unsigned int cpu) =20 for (i =3D cpu; i < NR_HW_IRQS; i +=3D msi->num_cpus) { msi_group =3D &msi->msi_groups[i]; - if (!msi_group->gic_irq) - continue; - irq_set_chained_handler_and_data(msi_group->gic_irq, NULL, NULL); } --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE6DC2E6D2A; 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SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" The xgene_msi structure remembers both the of_node of the device and the number of CPUs. All of which are perfectly useless. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene-msi.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index 5b69286689177..50a817920cfd9 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -31,14 +31,12 @@ struct xgene_msi_group { }; =20 struct xgene_msi { - struct device_node *node; struct irq_domain *inner_domain; u64 msi_addr; void __iomem *msi_regs; unsigned long *bitmap; struct mutex bitmap_lock; struct xgene_msi_group *msi_groups; - int num_cpus; }; =20 /* Global data */ @@ -147,7 +145,7 @@ static void xgene_compose_msi_msg(struct irq_data *data= , struct msi_msg *msg) */ static int hwirq_to_cpu(unsigned long hwirq) { - return (hwirq % xgene_msi_ctrl.num_cpus); + return (hwirq % num_possible_cpus()); } =20 static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq) @@ -186,9 +184,9 @@ static int xgene_irq_domain_alloc(struct irq_domain *do= main, unsigned int virq, mutex_lock(&msi->bitmap_lock); =20 msi_irq =3D bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0, - msi->num_cpus, 0); + num_possible_cpus(), 0); if (msi_irq < NR_MSI_VEC) - bitmap_set(msi->bitmap, msi_irq, msi->num_cpus); + bitmap_set(msi->bitmap, msi_irq, num_possible_cpus()); else msi_irq =3D -ENOSPC; =20 @@ -214,7 +212,7 @@ static void xgene_irq_domain_free(struct irq_domain *do= main, mutex_lock(&msi->bitmap_lock); =20 hwirq =3D hwirq_to_canonical_hwirq(d->hwirq); - bitmap_clear(msi->bitmap, hwirq, msi->num_cpus); + bitmap_clear(msi->bitmap, hwirq, num_possible_cpus()); =20 mutex_unlock(&msi->bitmap_lock); =20 @@ -235,10 +233,11 @@ static const struct msi_parent_ops xgene_msi_parent_o= ps =3D { .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 -static int xgene_allocate_domains(struct xgene_msi *msi) +static int xgene_allocate_domains(struct device_node *node, + struct xgene_msi *msi) { struct irq_domain_info info =3D { - .fwnode =3D of_fwnode_handle(msi->node), + .fwnode =3D of_fwnode_handle(node), .ops =3D &xgene_msi_domain_ops, .size =3D NR_MSI_VEC, .host_data =3D msi, @@ -358,7 +357,7 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu) int i; int err; =20 - for (i =3D cpu; i < NR_HW_IRQS; i +=3D msi->num_cpus) { + for (i =3D cpu; i < NR_HW_IRQS; i +=3D num_possible_cpus()) { msi_group =3D &msi->msi_groups[i]; =20 /* @@ -386,7 +385,7 @@ static int xgene_msi_hwirq_free(unsigned int cpu) struct xgene_msi_group *msi_group; int i; =20 - for (i =3D cpu; i < NR_HW_IRQS; i +=3D msi->num_cpus) { + for (i =3D cpu; i < NR_HW_IRQS; i +=3D num_possible_cpus()) { msi_group =3D &msi->msi_groups[i]; irq_set_chained_handler_and_data(msi_group->gic_irq, NULL, NULL); @@ -417,8 +416,6 @@ static int xgene_msi_probe(struct platform_device *pdev) goto error; } xgene_msi->msi_addr =3D res->start; - xgene_msi->node =3D pdev->dev.of_node; - xgene_msi->num_cpus =3D num_possible_cpus(); =20 rc =3D xgene_msi_init_allocator(xgene_msi); if (rc) { @@ -426,7 +423,7 @@ static int xgene_msi_probe(struct platform_device *pdev) goto error; } =20 - rc =3D xgene_allocate_domains(xgene_msi); + rc =3D xgene_allocate_domains(dev_of_node(&pdev->dev), xgene_msi); if (rc) { dev_err(&pdev->dev, "Failed to allocate MSI domain\n"); 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Tue, 08 Jul 2025 18:34:10 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 07/13] PCI: xgene-msi: Use device-managed memory allocations Date: Tue, 8 Jul 2025 18:33:58 +0100 Message-Id: <20250708173404.1278635-8-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Since the MSI driver is probed as a platform device, there is no reason to not use device-managed allocations. That's including the top-level bookkeeping structure, which is better dynamically alocated than being static. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene-msi.c | 37 +++++++++++++------------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index 50a817920cfd9..8b6724fe8d71c 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -40,7 +40,7 @@ struct xgene_msi { }; =20 /* Global data */ -static struct xgene_msi xgene_msi_ctrl; +static struct xgene_msi *xgene_msi_ctrl; =20 /* * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where @@ -253,18 +253,18 @@ static void xgene_free_domains(struct xgene_msi *msi) irq_domain_remove(msi->inner_domain); } =20 -static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi) +static int xgene_msi_init_allocator(struct device *dev) { - xgene_msi->bitmap =3D bitmap_zalloc(NR_MSI_VEC, GFP_KERNEL); - if (!xgene_msi->bitmap) + xgene_msi_ctrl->bitmap =3D devm_bitmap_zalloc(dev, NR_MSI_VEC, GFP_KERNEL= ); + if (!xgene_msi_ctrl->bitmap) return -ENOMEM; =20 - mutex_init(&xgene_msi->bitmap_lock); + mutex_init(&xgene_msi_ctrl->bitmap_lock); =20 - xgene_msi->msi_groups =3D kcalloc(NR_HW_IRQS, - sizeof(struct xgene_msi_group), - GFP_KERNEL); - if (!xgene_msi->msi_groups) + xgene_msi_ctrl->msi_groups =3D devm_kcalloc(dev, NR_HW_IRQS, + sizeof(struct xgene_msi_group), + GFP_KERNEL); + if (!xgene_msi_ctrl->msi_groups) return -ENOMEM; =20 return 0; @@ -273,15 +273,14 @@ static int xgene_msi_init_allocator(struct xgene_msi = *xgene_msi) static void xgene_msi_isr(struct irq_desc *desc) { struct irq_chip *chip =3D irq_desc_get_chip(desc); + struct xgene_msi *xgene_msi =3D xgene_msi_ctrl; struct xgene_msi_group *msi_groups; - struct xgene_msi *xgene_msi; int msir_index, msir_val, hw_irq, ret; u32 intr_index, grp_select, msi_grp; =20 chained_irq_enter(chip, desc); =20 msi_groups =3D irq_desc_get_handler_data(desc); - xgene_msi =3D msi_groups->msi; msi_grp =3D msi_groups->msi_grp; =20 /* @@ -344,15 +343,12 @@ static void xgene_msi_remove(struct platform_device *= pdev) =20 kfree(msi->msi_groups); =20 - bitmap_free(msi->bitmap); - msi->bitmap =3D NULL; - xgene_free_domains(msi); } =20 static int xgene_msi_hwirq_alloc(unsigned int cpu) { - struct xgene_msi *msi =3D &xgene_msi_ctrl; + struct xgene_msi *msi =3D xgene_msi_ctrl; struct xgene_msi_group *msi_group; int i; int err; @@ -381,7 +377,7 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu) =20 static int xgene_msi_hwirq_free(unsigned int cpu) { - struct xgene_msi *msi =3D &xgene_msi_ctrl; + struct xgene_msi *msi =3D xgene_msi_ctrl; struct xgene_msi_group *msi_group; int i; =20 @@ -406,7 +402,12 @@ static int xgene_msi_probe(struct platform_device *pde= v) int virt_msir; u32 msi_val, msi_idx; =20 - xgene_msi =3D &xgene_msi_ctrl; + xgene_msi_ctrl =3D devm_kzalloc(&pdev->dev, sizeof(*xgene_msi_ctrl), + GFP_KERNEL); + if (!xgene_msi_ctrl) + return -ENOMEM; + + xgene_msi =3D xgene_msi_ctrl; =20 platform_set_drvdata(pdev, xgene_msi); =20 @@ -417,7 +418,7 @@ static int xgene_msi_probe(struct platform_device *pdev) } xgene_msi->msi_addr =3D res->start; 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Tue, 08 Jul 2025 18:34:10 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 08/13] PCI: xgene-msi: Get rid of intermediate tracking structure Date: Tue, 8 Jul 2025 18:33:59 +0100 Message-Id: <20250708173404.1278635-9-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" The xgene-msi driver uses an odd construct in the form of an intermediate tracking structure, evidently designed to deal with multiple instances of the MSI widget. However, the existing HW only has one set, and it is obvious that there won't be new HW coming down that particular line. Simplify the driver by using a bit of pointer arithmetic instead, directly tracking the interrupt and avoiding extra memory allocation. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene-msi.c | 60 ++++++++------------------ 1 file changed, 18 insertions(+), 42 deletions(-) diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index 8b6724fe8d71c..cef0488749e1d 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -24,19 +24,13 @@ #define NR_HW_IRQS 16 #define NR_MSI_VEC (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS) =20 -struct xgene_msi_group { - struct xgene_msi *msi; - int gic_irq; - u32 msi_grp; -}; - struct xgene_msi { struct irq_domain *inner_domain; u64 msi_addr; void __iomem *msi_regs; unsigned long *bitmap; struct mutex bitmap_lock; - struct xgene_msi_group *msi_groups; + unsigned int gic_irq[NR_HW_IRQS]; }; =20 /* Global data */ @@ -261,27 +255,20 @@ static int xgene_msi_init_allocator(struct device *de= v) =20 mutex_init(&xgene_msi_ctrl->bitmap_lock); =20 - xgene_msi_ctrl->msi_groups =3D devm_kcalloc(dev, NR_HW_IRQS, - sizeof(struct xgene_msi_group), - GFP_KERNEL); - if (!xgene_msi_ctrl->msi_groups) - return -ENOMEM; - return 0; } =20 static void xgene_msi_isr(struct irq_desc *desc) { + unsigned int *irqp =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); struct xgene_msi *xgene_msi =3D xgene_msi_ctrl; - struct xgene_msi_group *msi_groups; int msir_index, msir_val, hw_irq, ret; u32 intr_index, grp_select, msi_grp; =20 chained_irq_enter(chip, desc); =20 - msi_groups =3D irq_desc_get_handler_data(desc); - msi_grp =3D msi_groups->msi_grp; + msi_grp =3D irqp - xgene_msi->gic_irq; =20 /* * MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt @@ -341,35 +328,31 @@ static void xgene_msi_remove(struct platform_device *= pdev) cpuhp_remove_state(pci_xgene_online); cpuhp_remove_state(CPUHP_PCI_XGENE_DEAD); =20 - kfree(msi->msi_groups); - xgene_free_domains(msi); } =20 static int xgene_msi_hwirq_alloc(unsigned int cpu) { - struct xgene_msi *msi =3D xgene_msi_ctrl; - struct xgene_msi_group *msi_group; int i; int err; =20 for (i =3D cpu; i < NR_HW_IRQS; i +=3D num_possible_cpus()) { - msi_group =3D &msi->msi_groups[i]; + unsigned int irq =3D xgene_msi_ctrl->gic_irq[i]; =20 /* * Statically allocate MSI GIC IRQs to each CPU core. * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated * to each core. */ - irq_set_status_flags(msi_group->gic_irq, IRQ_NO_BALANCING); - err =3D irq_set_affinity(msi_group->gic_irq, cpumask_of(cpu)); + irq_set_status_flags(irq, IRQ_NO_BALANCING); + err =3D irq_set_affinity(irq, cpumask_of(cpu)); if (err) { pr_err("failed to set affinity for GIC IRQ"); return err; } =20 - irq_set_chained_handler_and_data(msi_group->gic_irq, - xgene_msi_isr, msi_group); + irq_set_chained_handler_and_data(irq, xgene_msi_isr, + &xgene_msi_ctrl->gic_irq[i]); } =20 return 0; @@ -378,14 +361,11 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu) static int xgene_msi_hwirq_free(unsigned int cpu) { struct xgene_msi *msi =3D xgene_msi_ctrl; - struct xgene_msi_group *msi_group; int i; =20 - for (i =3D cpu; i < NR_HW_IRQS; i +=3D num_possible_cpus()) { - msi_group =3D &msi->msi_groups[i]; - irq_set_chained_handler_and_data(msi_group->gic_irq, NULL, - NULL); - } + for (i =3D cpu; i < NR_HW_IRQS; i +=3D num_possible_cpus()) + irq_set_chained_handler_and_data(msi->gic_irq[i], NULL, NULL); + return 0; } =20 @@ -397,10 +377,9 @@ static const struct of_device_id xgene_msi_match_table= [] =3D { static int xgene_msi_probe(struct platform_device *pdev) { struct resource *res; - int rc, irq_index; struct xgene_msi *xgene_msi; - int virt_msir; u32 msi_val, msi_idx; + int rc; =20 xgene_msi_ctrl =3D devm_kzalloc(&pdev->dev, sizeof(*xgene_msi_ctrl), GFP_KERNEL); @@ -430,15 +409,12 @@ static int xgene_msi_probe(struct platform_device *pd= ev) goto error; } =20 - for (irq_index =3D 0; irq_index < NR_HW_IRQS; irq_index++) { - virt_msir =3D platform_get_irq(pdev, irq_index); - if (virt_msir < 0) { - rc =3D virt_msir; + for (int irq_index =3D 0; irq_index < NR_HW_IRQS; irq_index++) { + rc =3D platform_get_irq(pdev, irq_index); + if (rc < 0) goto error; - } - xgene_msi->msi_groups[irq_index].gic_irq =3D virt_msir; - xgene_msi->msi_groups[irq_index].msi_grp =3D irq_index; - xgene_msi->msi_groups[irq_index].msi =3D xgene_msi; + + xgene_msi->gic_irq[irq_index] =3D rc; } =20 /* @@ -446,7 +422,7 @@ static int xgene_msi_probe(struct platform_device *pdev) * interrupt handlers, read all of them to clear spurious * interrupts that may occur before the driver is probed. */ - for (irq_index =3D 0; irq_index < NR_HW_IRQS; irq_index++) { + for (int irq_index =3D 0; irq_index < NR_HW_IRQS; irq_index++) { for (msi_idx =3D 0; msi_idx < IDX_PER_GROUP; msi_idx++) xgene_msi_ir_read(xgene_msi, irq_index, msi_idx); =20 --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6B722E7653; Tue, 8 Jul 2025 17:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Plugging a device that doesn't use managed affinity on an XGene-1 machine results in messages such as: genirq: irq_chip PCI-MSIX-0000:01:00.0 did not update eff. affinity mask of= irq 39 As it turns out, the driver was never updated to populate the effective affinity on irq_set_affinity() call, and the core code is prickly about that. But upon further investigation, it appears that the driver keeps repainting the hwirq field of the irq_data structure as a way to track the affinity of the MSI, something that is very much frowned upon as it breaks the fundamentals of an IRQ domain (an array indexed by hwirq). Fixing this results more or less in a rewrite of the driver: - Define how a hwirq and a cpu affinity map onto the MSI termination registers - Allocate a single entry in the bitmap per MSI instead of *8* - Correctly track CPU affinity - Fix the documentation so that it actually means something (to me) - Use standard bitmap iterators - and plenty of other cleanups With this, the driver behaves correctly on my vintage Mustang board. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene-msi.c | 222 +++++++++++-------------- 1 file changed, 93 insertions(+), 129 deletions(-) diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index cef0488749e1d..b9f364da87f2a 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -6,6 +6,7 @@ * Author: Tanmay Inamdar * Duc Dang */ +#include #include #include #include @@ -22,7 +23,15 @@ #define IDX_PER_GROUP 8 #define IRQS_PER_IDX 16 #define NR_HW_IRQS 16 -#define NR_MSI_VEC (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS) +#define NR_MSI_BITS (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS) +#define NR_MSI_VEC (NR_MSI_BITS / num_possible_cpus()) + +#define MSI_GROUP_MASK GENMASK(22, 19) +#define MSI_INDEX_MASK GENMASK(18, 16) +#define MSI_INTR_MASK GENMASK(19, 16) + +#define MSInRx_HWIRQ_MASK GENMASK(6, 4) +#define DATA_HWIRQ_MASK GENMASK(3, 0) =20 struct xgene_msi { struct irq_domain *inner_domain; @@ -37,8 +46,26 @@ struct xgene_msi { static struct xgene_msi *xgene_msi_ctrl; =20 /* - * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where - * n is group number (0..F), x is index of registers in each group (0..7) + * X-Gene v1 has 16 frames of MSI termination registers MSInIRx, where n is + * frame number (0..15), x is index of registers in each frame (0..7). Ea= ch + * 32b register is at the beginning of a 64kB region, each frame occupying + * 512kB (and the whole thing 8MB of PA space). + * + * Each register supports 16 MSI vectors (0..15) to generate interrupts. A + * write to the MSInIRx from the PCI side generates an interrupt. A read + * from the MSInRx on the CPU side returns a bitmap of the pending MSIs in + * the lower 16 bits. A side effect of this read is that all pending + * interrupts are acknowledged and cleared). + * + * Additionally, each MSI termination frame has 1 MSIINTn register (n is + * 0..15) to indicate the MSI pending status caused by any of its 8 + * termination registers, reported as a bitmap in the lower 8 bits. Each 3= 2b + * register is at the beginning of a 64kB region (and overall occupying an + * extra 1MB). + * + * There is one GIC IRQ assigned for each MSI termination frame, 16 in + * total. + * * The register layout is as follows: * MSI0IR0 base_addr * MSI0IR1 base_addr + 0x10000 @@ -59,107 +86,74 @@ static struct xgene_msi *xgene_msi_ctrl; * MSIINT1 base_addr + 0x810000 * ... ... * MSIINTF base_addr + 0x8F0000 - * - * Each index register supports 16 MSI vectors (0..15) to generate interru= pt. - * There are total 16 GIC IRQs assigned for these 16 groups of MSI termina= tion - * registers. - * - * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indic= ate - * the MSI pending status caused by 1 of its 8 index registers. */ =20 /* MSInIRx read helper */ -static u32 xgene_msi_ir_read(struct xgene_msi *msi, - u32 msi_grp, u32 msir_idx) +static u32 xgene_msi_ir_read(struct xgene_msi *msi, u32 msi_grp, u32 msir_= idx) { return readl_relaxed(msi->msi_regs + MSI_IR0 + - (msi_grp << 19) + (msir_idx << 16)); + (FIELD_PREP(MSI_GROUP_MASK, msi_grp) | + FIELD_PREP(MSI_INDEX_MASK, msir_idx))); } =20 /* MSIINTn read helper */ static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp) { - return readl_relaxed(msi->msi_regs + MSI_INT0 + (msi_grp << 16)); + return readl_relaxed(msi->msi_regs + MSI_INT0 + + FIELD_PREP(MSI_INTR_MASK, msi_grp)); } =20 /* - * With 2048 MSI vectors supported, the MSI message can be constructed usi= ng - * following scheme: - * - Divide into 8 256-vector groups - * Group 0: 0-255 - * Group 1: 256-511 - * Group 2: 512-767 - * ... - * Group 7: 1792-2047 - * - Each 256-vector group is divided into 16 16-vector groups - * As an example: 16 16-vector groups for 256-vector group 0-255 is - * Group 0: 0-15 - * Group 1: 16-32 - * ... - * Group 15: 240-255 - * - The termination address of MSI vector in 256-vector group n and 16-ve= ctor - * group x is the address of MSIxIRn - * - The data for MSI vector in 16-vector group x is x + * In order to allow an MSI to be moved from one CPU to another without + * having to repaint both the address and the data (which cannot be done + * atomically), we statically partitions the MSI frames between CPUs. Given + * that XGene-1 has 8 CPUs, each CPU gets two frames assigned to it + * + * We adopt the convention that when an MSI is moved, it is configured to + * target the same register number in the congruent frame assigned to the + * new target CPU. This reserves a given MSI across all CPUs, and reduces + * the MSI capacity from 2048 to 256. + * + * Effectively, this amounts to: + * - hwirq[7]::cpu[2:0] is the target frame number (n in MSInIRx) + * - hwirq[6:4] is the register index in any given frame (x in MSInIRx) + * - hwirq[3:0] is the MSI data */ -static u32 hwirq_to_reg_set(unsigned long hwirq) +static irq_hw_number_t compute_hwirq(u8 frame, u8 index, u8 data) { - return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX)); -} - -static u32 hwirq_to_group(unsigned long hwirq) -{ - return (hwirq % NR_HW_IRQS); -} - -static u32 hwirq_to_msi_data(unsigned long hwirq) -{ - return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX); + return (FIELD_PREP(BIT(7), FIELD_GET(BIT(3), frame)) | + FIELD_PREP(MSInRx_HWIRQ_MASK, index) | + FIELD_PREP(DATA_HWIRQ_MASK, data)); } =20 static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *m= sg) { struct xgene_msi *msi =3D irq_data_get_irq_chip_data(data); - u32 reg_set =3D hwirq_to_reg_set(data->hwirq); - u32 group =3D hwirq_to_group(data->hwirq); - u64 target_addr =3D msi->msi_addr + (((8 * group) + reg_set) << 16); + u64 target_addr; + u32 frame, msir; + int cpu; =20 - msg->address_hi =3D upper_32_bits(target_addr); - msg->address_lo =3D lower_32_bits(target_addr); - msg->data =3D hwirq_to_msi_data(data->hwirq); -} + cpu =3D cpumask_first(irq_data_get_effective_affinity_mask(data)); + msir =3D FIELD_GET(GENMASK(6, 4), data->hwirq); + frame =3D FIELD_PREP(BIT(3), FIELD_GET(BIT(7), data->hwirq)) | cpu; =20 -/* - * X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain - * the expected behaviour of .set_affinity for each MSI interrupt, the 16 - * MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs - * for each core). The MSI vector is moved from 1 MSI GIC IRQ to another - * MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a - * consequence, the total MSI vectors that X-Gene v1 supports will be - * reduced to 256 (2048/8) vectors. - */ -static int hwirq_to_cpu(unsigned long hwirq) -{ - return (hwirq % num_possible_cpus()); -} + target_addr =3D msi->msi_addr; + target_addr +=3D (FIELD_PREP(MSI_GROUP_MASK, frame) | + FIELD_PREP(MSI_INTR_MASK, msir)); =20 -static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq) -{ - return (hwirq - hwirq_to_cpu(hwirq)); + msg->address_hi =3D upper_32_bits(target_addr); + msg->address_lo =3D lower_32_bits(target_addr); + msg->data =3D FIELD_GET(DATA_HWIRQ_MASK, data->hwirq); } =20 static int xgene_msi_set_affinity(struct irq_data *irqdata, const struct cpumask *mask, bool force) { int target_cpu =3D cpumask_first(mask); - int curr_cpu; - - curr_cpu =3D hwirq_to_cpu(irqdata->hwirq); - if (curr_cpu =3D=3D target_cpu) - return IRQ_SET_MASK_OK_DONE; =20 - /* Update MSI number to target the new CPU */ - irqdata->hwirq =3D hwirq_to_canonical_hwirq(irqdata->hwirq) + target_cpu; + irq_data_update_effective_affinity(irqdata, cpumask_of(target_cpu)); =20 + /* Force the core code to regenerate the message */ return IRQ_SET_MASK_OK; } =20 @@ -173,23 +167,20 @@ static int xgene_irq_domain_alloc(struct irq_domain *= domain, unsigned int virq, unsigned int nr_irqs, void *args) { struct xgene_msi *msi =3D domain->host_data; - int msi_irq; + irq_hw_number_t hwirq; =20 mutex_lock(&msi->bitmap_lock); =20 - msi_irq =3D bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0, - num_possible_cpus(), 0); - if (msi_irq < NR_MSI_VEC) - bitmap_set(msi->bitmap, msi_irq, num_possible_cpus()); - else - msi_irq =3D -ENOSPC; + hwirq =3D find_first_zero_bit(msi->bitmap, NR_MSI_VEC); + if (hwirq < NR_MSI_VEC) + set_bit(hwirq, msi->bitmap); =20 mutex_unlock(&msi->bitmap_lock); =20 - if (msi_irq < 0) - return msi_irq; + if (hwirq >=3D NR_MSI_VEC) + return -ENOSPC; =20 - irq_domain_set_info(domain, virq, msi_irq, + irq_domain_set_info(domain, virq, hwirq, &xgene_msi_bottom_irq_chip, domain->host_data, handle_simple_irq, NULL, NULL); =20 @@ -201,12 +192,10 @@ static void xgene_irq_domain_free(struct irq_domain *= domain, { struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); struct xgene_msi *msi =3D irq_data_get_irq_chip_data(d); - u32 hwirq; =20 mutex_lock(&msi->bitmap_lock); =20 - hwirq =3D hwirq_to_canonical_hwirq(d->hwirq); - bitmap_clear(msi->bitmap, hwirq, num_possible_cpus()); + clear_bit(d->hwirq, msi->bitmap); =20 mutex_unlock(&msi->bitmap_lock); =20 @@ -263,55 +252,30 @@ static void xgene_msi_isr(struct irq_desc *desc) unsigned int *irqp =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); struct xgene_msi *xgene_msi =3D xgene_msi_ctrl; - int msir_index, msir_val, hw_irq, ret; - u32 intr_index, grp_select, msi_grp; + unsigned long grp_pending; + int msir_idx; + u32 msi_grp; =20 chained_irq_enter(chip, desc); =20 msi_grp =3D irqp - xgene_msi->gic_irq; =20 - /* - * MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt - * If bit x of this register is set (x is 0..7), one or more interrupts - * corresponding to MSInIRx is set. - */ - grp_select =3D xgene_msi_int_read(xgene_msi, msi_grp); - while (grp_select) { - msir_index =3D ffs(grp_select) - 1; - /* - * Calculate MSInIRx address to read to check for interrupts - * (refer to termination address and data assignment - * described in xgene_compose_msi_msg() ) - */ - msir_val =3D xgene_msi_ir_read(xgene_msi, msi_grp, msir_index); - while (msir_val) { - intr_index =3D ffs(msir_val) - 1; - /* - * Calculate MSI vector number (refer to the termination - * address and data assignment described in - * xgene_compose_msi_msg function) - */ - hw_irq =3D (((msir_index * IRQS_PER_IDX) + intr_index) * - NR_HW_IRQS) + msi_grp; - /* - * As we have multiple hw_irq that maps to single MSI, - * always look up the virq using the hw_irq as seen from - * CPU0 - */ - hw_irq =3D hwirq_to_canonical_hwirq(hw_irq); - ret =3D generic_handle_domain_irq(xgene_msi->inner_domain, hw_irq); + grp_pending =3D xgene_msi_int_read(xgene_msi, msi_grp); + + for_each_set_bit(msir_idx, &grp_pending, IDX_PER_GROUP) { + unsigned long msir; + int intr_idx; + + msir =3D xgene_msi_ir_read(xgene_msi, msi_grp, msir_idx); + + for_each_set_bit(intr_idx, &msir, IRQS_PER_IDX) { + irq_hw_number_t hwirq; + int ret; + + hwirq =3D compute_hwirq(msi_grp, msir_idx, intr_idx); + ret =3D generic_handle_domain_irq(xgene_msi->inner_domain, + hwirq); WARN_ON_ONCE(ret); - msir_val &=3D ~(1 << intr_index); - } - grp_select &=3D ~(1 << msir_index); - - if (!grp_select) { - /* - * We handled all interrupts happened in this group, - * resample this group MSI_INTx register in case - * something else has been made pending in the meantime - */ - grp_select =3D xgene_msi_int_read(xgene_msi, msi_grp); } } =20 --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB33E2E7644; Tue, 8 Jul 2025 17:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Since changing the affinity of an MSI really is about changing the target address and that it isn't possible to mask an individual MSI, it is completely possible for an interrupt to race with itself, usually resulting in a lost interrupt. Paper over the design blunder by informing the core code of this sad state of affair. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene-msi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index b9f364da87f2a..a190c25c8df52 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -183,6 +183,7 @@ static int xgene_irq_domain_alloc(struct irq_domain *do= main, unsigned int virq, irq_domain_set_info(domain, virq, hwirq, &xgene_msi_bottom_irq_chip, domain->host_data, handle_simple_irq, NULL, NULL); + irqd_set_resend_when_in_progress(irq_get_irq_data(virq)); =20 return 0; } --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F23342E7BBC; Tue, 8 Jul 2025 17:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996053; cv=none; b=oUNEvQNXGdYDKxmgmbTsz+eY10uPbm0DKyLYNCzDffNeMp5R6oC7u8N9WpllNt1BolQQ8+AmCJBu38xhzDdzC+ashg0W1rKdnsykNyAYHex+Ain4zuoLC7awLmTnH61K3KxPObYi5YKz7eA6itEco9R4yYdHN7ttnL1L/AE4HDs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996053; c=relaxed/simple; bh=R1XE97PXvA2ANKeTAsd6SDjyoafLP7919cZJ82aU2GU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aFmXKZ+v5ncR9Qp06nmAjospIih4sKNG0w8suBEJ6Ri9YWaebZuQiaTeGj4iMtKI3f/18zf+vn3YFbE3oVOYKBjmoynwPEnlicMcmpPfpDAQTYYgUwv/girLRfISE6ip8WnwXPJOXA4EcCz5mE/rp3dC6LxGCreFoHYhrQHOrxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RbM5gYfp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RbM5gYfp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 96CB0C4CEF8; Tue, 8 Jul 2025 17:34:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751996052; bh=R1XE97PXvA2ANKeTAsd6SDjyoafLP7919cZJ82aU2GU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RbM5gYfp7zNIfYsBNm9Yil6S+w3K1LUNu7NHSjNpD6v2mDyXpjJX8BX4SeC8THFze 3FJpGCOWwpcWKnMyjLVVI3brVfYF25HO7lRLxbCAH41IXFM2d0iO2wlKcbQZMllSmM byytUP52pOLhqk/aQrTnLgJY0r4fW+OveghnhitKPz2gRD1Bw0rC+IgQutehm0RrV9 PP7/GMGRG6fcGgkxnomWPZJdtT2ob4zKwluEPhguctvBwoRPOrO3/9TBcOsFtZV0zK q/ROl8pl00R3OzWZ/Nx3cg/h5ZwBD4phK/SjleA5dp0sF+Kov4D9/v6HhOqNK5gAkJ ivpmOv2YxbQGg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZCCo-00Dqhw-PD; Tue, 08 Jul 2025 18:34:10 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 11/13] PCI: xgene-msi: Probe as a standard platform driver Date: Tue, 8 Jul 2025 18:34:02 +0100 Message-Id: <20250708173404.1278635-12-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Now that we have made the dependedncy between the PCI driver and the MSI driver explicit, there is no need to use subsys_initcall() as a probing hook, and we can rely on builtin_platform_driver() instead. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene-msi.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index a190c25c8df52..243c7721c8799 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -429,9 +429,4 @@ static struct platform_driver xgene_msi_driver =3D { .probe =3D xgene_msi_probe, .remove =3D xgene_msi_remove, }; - -static int __init xgene_pcie_msi_init(void) -{ - return platform_driver_register(&xgene_msi_driver); -} -subsys_initcall(xgene_pcie_msi_init); +builtin_platform_driver(xgene_msi_driver); --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCEC42E765B; Tue, 8 Jul 2025 17:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996053; cv=none; b=tIAOgCZ9B1lxnxGD9AUhLIV7PeCmhBxLR+C02qgAYtYBV/JhYVkuXLG3Tbd0hC0ByDggYcNmUjnz3wg1PEj0jMLsiRZlHLCwk492fF3HGAkI0dhQ2hK2K8g5UyPGnpMfVildULE2ccZm3onhZ+k/Ry5vQWZDXS1QnVOQbQukgY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996053; c=relaxed/simple; bh=6fDBnG3B0k3eKz3zYgAFbJfo6asA8fjCKgUn7vcapoE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F9xDvbZ/aATMY/0IqhPp30d6bmJEhMnP4B9rDIqwBcvnLn6Q7YOE1p7aFTDMzA/wTUVMyWkaaZLT6Wk4OnJGhKt56NGeNtD44a854nuPkOLWBtCP2uEjxDCi4UPwiQ3k+u+HoYGWvczk3CItFHjrf+hoTNJr2UsnpGmQZPEXvdE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KKbc7g5t; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KKbc7g5t" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BDABEC4CEFA; Tue, 8 Jul 2025 17:34:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751996052; bh=6fDBnG3B0k3eKz3zYgAFbJfo6asA8fjCKgUn7vcapoE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KKbc7g5t1AmOB88oViPL9AWf3FUX951LqtBCuuGW9YwBwTVcFS5cNGFhNREE/Ah/c 64pOfEuSgfR0/rRjCL2DG5Z8vDZ3jrvCvXkxJtJK4G7+Ek7KUlhtn3fmb5wyUaJu/2 gMNJvjQZftiHHjYPqwva8+aBVyQN2gEfTze94VeUCHUL+6Dg9yuiai54U2C0yJH+bY LntshdHhG5QNqxwIP8g/FQ9AT8hN7IgZbb+RQ8y1K9UW1Eo/nle+4hMYIS4s5PVkH5 h+5wNQGmvEmZ4tqVTa47U6aqs566Ngzf58FPt0QmsxVUmlymykKvs4aG3FF1rBChpG 0s5xH8bfdpfMg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZCCo-00Dqhw-W4; Tue, 08 Jul 2025 18:34:11 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 12/13] PCI: xgene-msi: Restructure handler setup/teardown Date: Tue, 8 Jul 2025 18:34:03 +0100 Message-Id: <20250708173404.1278635-13-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Another utterly pointless aspect of the xgene-msi driver is that it is built around CPU hotplug. Which is quite amusing since this is one of the few arm64 platforms that, by construction, cannot do CPU hotplug in a supported way (no EL3, no PSCI, no luck). Drop the CPU hotplug nonsense and just setup the IRQs and handlers in a less overdesigned way, grouping things more logically in the process. Signed-off-by: Marc Zyngier --- drivers/pci/controller/pci-xgene-msi.c | 107 +++++++++---------------- 1 file changed, 37 insertions(+), 70 deletions(-) diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controlle= r/pci-xgene-msi.c index 243c7721c8799..dd8b119ab90e0 100644 --- a/drivers/pci/controller/pci-xgene-msi.c +++ b/drivers/pci/controller/pci-xgene-msi.c @@ -231,12 +231,6 @@ static int xgene_allocate_domains(struct device_node *= node, return msi->inner_domain ? 0 : -ENOMEM; } =20 -static void xgene_free_domains(struct xgene_msi *msi) -{ - if (msi->inner_domain) - irq_domain_remove(msi->inner_domain); -} - static int xgene_msi_init_allocator(struct device *dev) { xgene_msi_ctrl->bitmap =3D devm_bitmap_zalloc(dev, NR_MSI_VEC, GFP_KERNEL= ); @@ -283,26 +277,48 @@ static void xgene_msi_isr(struct irq_desc *desc) chained_irq_exit(chip, desc); } =20 -static enum cpuhp_state pci_xgene_online; - static void xgene_msi_remove(struct platform_device *pdev) { - struct xgene_msi *msi =3D platform_get_drvdata(pdev); - - if (pci_xgene_online) - cpuhp_remove_state(pci_xgene_online); - cpuhp_remove_state(CPUHP_PCI_XGENE_DEAD); + for (int i =3D 0; i < NR_HW_IRQS; i++) { + unsigned int irq =3D xgene_msi_ctrl->gic_irq[i]; + if (!irq) + continue; + irq_set_chained_handler_and_data(irq, NULL, NULL); + } =20 - xgene_free_domains(msi); + if (xgene_msi_ctrl->inner_domain) + irq_domain_remove(xgene_msi_ctrl->inner_domain); } =20 -static int xgene_msi_hwirq_alloc(unsigned int cpu) +static int xgene_msi_handler_setup(struct platform_device *pdev) { + struct xgene_msi *xgene_msi =3D xgene_msi_ctrl; int i; - int err; =20 - for (i =3D cpu; i < NR_HW_IRQS; i +=3D num_possible_cpus()) { - unsigned int irq =3D xgene_msi_ctrl->gic_irq[i]; + for (i =3D 0; i < NR_HW_IRQS; i++) { + u32 msi_val; + int irq, err; + + /* + * MSInIRx registers are read-to-clear; before registering + * interrupt handlers, read all of them to clear spurious + * interrupts that may occur before the driver is probed. + */ + for (int msi_idx =3D 0; msi_idx < IDX_PER_GROUP; msi_idx++) + xgene_msi_ir_read(xgene_msi, i, msi_idx); + + /* Read MSIINTn to confirm */ + msi_val =3D xgene_msi_int_read(xgene_msi, i); + if (msi_val) { + dev_err(&pdev->dev, "Failed to clear spurious IRQ\n"); + return EINVAL; + } + + irq =3D platform_get_irq(pdev, i); + if (irq < 0) + return irq; + + xgene_msi->gic_irq[i] =3D irq; =20 /* * Statically allocate MSI GIC IRQs to each CPU core. @@ -310,7 +326,7 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu) * to each core. */ irq_set_status_flags(irq, IRQ_NO_BALANCING); - err =3D irq_set_affinity(irq, cpumask_of(cpu)); + err =3D irq_set_affinity(irq, cpumask_of(i % num_possible_cpus())); if (err) { pr_err("failed to set affinity for GIC IRQ"); return err; @@ -323,17 +339,6 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu) return 0; } =20 -static int xgene_msi_hwirq_free(unsigned int cpu) -{ - struct xgene_msi *msi =3D xgene_msi_ctrl; - int i; - - for (i =3D cpu; i < NR_HW_IRQS; i +=3D num_possible_cpus()) - irq_set_chained_handler_and_data(msi->gic_irq[i], NULL, NULL); - - return 0; -} - static const struct of_device_id xgene_msi_match_table[] =3D { {.compatible =3D "apm,xgene1-msi"}, {}, @@ -343,7 +348,6 @@ static int xgene_msi_probe(struct platform_device *pdev) { struct resource *res; struct xgene_msi *xgene_msi; - u32 msi_val, msi_idx; int rc; =20 xgene_msi_ctrl =3D devm_kzalloc(&pdev->dev, sizeof(*xgene_msi_ctrl), @@ -353,8 +357,6 @@ static int xgene_msi_probe(struct platform_device *pdev) =20 xgene_msi =3D xgene_msi_ctrl; =20 - platform_set_drvdata(pdev, xgene_msi); - xgene_msi->msi_regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, &= res); if (IS_ERR(xgene_msi->msi_regs)) { rc =3D PTR_ERR(xgene_msi->msi_regs); @@ -374,48 +376,13 @@ static int xgene_msi_probe(struct platform_device *pd= ev) goto error; } =20 - for (int irq_index =3D 0; irq_index < NR_HW_IRQS; irq_index++) { - rc =3D platform_get_irq(pdev, irq_index); - if (rc < 0) - goto error; - - xgene_msi->gic_irq[irq_index] =3D rc; - } - - /* - * MSInIRx registers are read-to-clear; before registering - * interrupt handlers, read all of them to clear spurious - * interrupts that may occur before the driver is probed. - */ - for (int irq_index =3D 0; irq_index < NR_HW_IRQS; irq_index++) { - for (msi_idx =3D 0; msi_idx < IDX_PER_GROUP; msi_idx++) - xgene_msi_ir_read(xgene_msi, irq_index, msi_idx); - - /* Read MSIINTn to confirm */ - msi_val =3D xgene_msi_int_read(xgene_msi, irq_index); - if (msi_val) { - dev_err(&pdev->dev, "Failed to clear spurious IRQ\n"); - rc =3D -EINVAL; - goto error; - } - } - - rc =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online", - xgene_msi_hwirq_alloc, NULL); - if (rc < 0) - goto err_cpuhp; - pci_xgene_online =3D rc; - rc =3D cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL, - xgene_msi_hwirq_free); + rc =3D xgene_msi_handler_setup(pdev); if (rc) - goto err_cpuhp; + goto error; =20 dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n"); =20 return 0; - -err_cpuhp: - dev_err(&pdev->dev, "failed to add CPU MSI notifier\n"); error: xgene_msi_remove(pdev); return rc; --=20 2.39.2 From nobody Tue Oct 7 16:04:24 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28AB02E7F07; Tue, 8 Jul 2025 17:34:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996053; cv=none; b=DRxJ0+7xmUejBe6CXJcwCadYkqSHjZhoBzxilnL/gaB6Ee8etxTw/2f8anQXQKbRkS5TUa1ot/4r2T7fBLVtja9PQxu8UiR7nlTxkxNjp6jNLi5d64F5rS9pqtFNopseXpac9XmmAKeaFY4IgU6UpQ/OnkGPqVGH5n5z2P6C8UM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751996053; c=relaxed/simple; bh=k98cYHJAeNwc/m55APAuSnpJZEiaO0Z2w/xQyAaUaQw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Oc7DQpcIWPBH/qbIWR0n/iBqrbPCnMeRNJfALBP9HmsTOv6gc63HwXtQthuGhF7AoXx7rratdZeL3eiApmROa1VaAIavrmDjg+OvD3BCEHHRS4FsXLjO9HjV2SMhnWA2mru/l8QXf7Eya74zw7sG3PwKfmNoAnPFRcIN6HpJqXU= ARC-Authentication-Results: i=1; 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Tue, 08 Jul 2025 18:34:11 +0100 From: Marc Zyngier To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Toan Le , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Thomas Gleixner Subject: [PATCH v2 13/13] cpu/hotplug: Remove unused cpuhp_state CPUHP_PCI_XGENE_DEAD Date: Tue, 8 Jul 2025 18:34:04 +0100 Message-Id: <20250708173404.1278635-14-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250708173404.1278635-1-maz@kernel.org> References: <20250708173404.1278635-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, toan@os.amperecomputing.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Now that the XGene MSI driver has been mostly rewritten and doesn't use the CPU hotplug infrastructure, CPUHP_PCI_XGENE_DEAD is unused. Remove it to reduce the size of cpuhp_hp_states[]. Signed-off-by: Marc Zyngier --- include/linux/cpuhotplug.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index df366ee15456b..eaca70eb6136b 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -90,7 +90,6 @@ enum cpuhp_state { CPUHP_RADIX_DEAD, CPUHP_PAGE_ALLOC, CPUHP_NET_DEV_DEAD, - CPUHP_PCI_XGENE_DEAD, CPUHP_IOMMU_IOVA_DEAD, CPUHP_AP_ARM_CACHE_B15_RAC_DEAD, CPUHP_PADATA_DEAD, --=20 2.39.2