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[2003:e4:1f4e:9b00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-454cd43c6besm18557475e9.7.2025.07.08.03.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jul 2025 03:52:52 -0700 (PDT) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Rob Herring , Conor Dooley , Jonathan Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: memory: tegra: Add Tegra264 support Date: Tue, 8 Jul 2025 12:52:42 +0200 Message-ID: <20250708105245.1516143-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250708105245.1516143-1-thierry.reding@gmail.com> References: <20250708105245.1516143-1-thierry.reding@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Gupta Add bindings for the Memory Controller (MC) and External Memory Controller (EMC) found on the Tegra264 SoC. Tegra264 SoC has a different number of interrupt lines for MC sub-units: UCF_SOC, hub, hub common, syncpoint and MC channel. The total number of interrupt lines is eight. Update maxItems for MC interrupts accordingly. Signed-off-by: Sumit Gupta Signed-off-by: Thierry Reding --- .../nvidia,tegra186-mc.yaml | 65 ++++++++++++++++++- 1 file changed, 63 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,te= gra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidi= a,tegra186-mc.yaml index 935d63d181d9..52575a16349b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-= mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-= mc.yaml @@ -32,6 +32,7 @@ properties: - nvidia,tegra186-mc - nvidia,tegra194-mc - nvidia,tegra234-mc + - nvidia,tegra264-mc =20 reg: minItems: 6 @@ -42,8 +43,12 @@ properties: maxItems: 18 =20 interrupts: - items: - - description: MC general interrupt + minItems: 1 + maxItems: 8 + + interrupt-names: + minItems: 1 + maxItems: 8 =20 "#address-cells": const: 2 @@ -74,6 +79,7 @@ patternProperties: - nvidia,tegra186-emc - nvidia,tegra194-emc - nvidia,tegra234-emc + - nvidia,tegra264-emc =20 reg: minItems: 1 @@ -127,6 +133,15 @@ patternProperties: reg: minItems: 2 =20 + - if: + properties: + compatible: + const: nvidia,tegra264-emc + then: + properties: + reg: + minItems: 2 + additionalProperties: false =20 required: @@ -220,6 +235,52 @@ allOf: - const: ch14 - const: ch15 =20 + - if: + properties: + compatible: + const: nvidia,tegra264-mc + then: + properties: + reg: + minItems: 17 + description: 17 memory controller channels + + reg-names: + items: + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 + + interrupts: + minItems: 8 + maxItems: 8 + description: One interrupt line for each MC component + + interrupt-names: + items: + - const: mcf + - const: hub1 + - const: hub2 + - const: hub3 + - const: hub4 + - const: hub5 + - const: sbs + - const: channel + additionalProperties: false =20 required: --=20 2.50.0