From nobody Tue Oct 7 19:26:32 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37A1E299A98; Tue, 8 Jul 2025 08:59:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751965163; cv=none; b=G+emwjzIFo3SlrPj2bWs/+jWmnH73rUUMAOdrO3mDimX1nY50Dgxygae8dNqdB6g5+OJwKByUW5i/tVWMmWChSDgT9mxFAnV9dRNdoh4YlxCrhIvK9IyRglCh/o6ZpS7S38AtN7nzsYhcdwp6dBt2k5MropvxJ06PxvwaaQsrQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751965163; c=relaxed/simple; bh=fJ1kp7Blksibzxw+i/MHrtrSTimGdKNHUb4iw9W3fwk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ehGKUy6lc4XNMmnjjSsCx7uZJr4tHxT6rjdH60gBNsI5uu0mgeEdJ4Un+mN9VmiQKqoYyRrEqx2eQgTSKm6J/EWFIaBgolZ5KlUUuYdEhmtHQECq3aiosZDkhec36HdE3rnikAfFHHwxnRlzJWHXEGVexk0DL2O59txhEOi+dj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=GSXqnP3w; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="GSXqnP3w" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5688xCts465280; Tue, 8 Jul 2025 03:59:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751965152; bh=7gCN8MKW4Vjja7SF1dc5owa6CI5jAKB1JIkjZa802RQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GSXqnP3wAXh3OHQW9zaS4ZqMuYn0+wMisihQVK2R0WZh7uekbpeFMVqud1gZtmZLr aG7ah7ebCnQWjqu2ZRUasOVqxPcn9gIc461On8BJTX1NLuWnmdClZja1sALiAhFd6N tpdpsrFf46SdpI+jxkXRDFeVh9jSr0SLKk2MeSlo= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5688xCFE2226064 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 8 Jul 2025 03:59:12 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 8 Jul 2025 03:59:11 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 8 Jul 2025 03:59:11 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5688xBRi1787567; Tue, 8 Jul 2025 03:59:11 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v7 3/4] arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs Date: Tue, 8 Jul 2025 14:28:38 +0530 Message-ID: <20250708085839.1498505-4-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250708085839.1498505-1-p-bhagat@ti.com> References: <20250708085839.1498505-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Update k3-pinctrl file to include pin definitions for AM62D2 family of SoCs. Signed-off-by: Paresh Bhagat Reviewed-by: Devarsh Thakkar --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index cac7cccc1112..0cf57179c974 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -63,6 +63,9 @@ #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) +#define AM62DX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) + #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 --=20 2.34.1