From nobody Tue Oct 7 19:26:32 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E08D8299A98; Tue, 8 Jul 2025 08:59:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751965158; cv=none; b=iKlok3Vr8PVee47iFFCNFHqZNNQppip2rOjbYyFJ0+oWS3hUYbpwMgCSUXqpIFqLAfsGhoNd1ISXHyX9JXfECNztA0QJCOqZJ/SCNYFSQPXk3GyceRM/dHuD1Cjr3NzYCjdaSFgu6uNd80szSpHb2unGm3wmhKsHHFbuV1hegug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751965158; c=relaxed/simple; bh=ZEai/T2ltKtKEFlkHw3XWYouQucjBQrVHpxXHmgbGbw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nHwLaQBa0i1Q2qkg/5SKCw0G6RCEgJG9zr0eErhZAaDnDkplL/knHq/bCd10jYpBJRini+3etEuynIrdLBEQOv9XmcSqfWz35jarP43sPfg03gBNGbqggkKvTpfhQ4Yp17Q7UtIYrOmiWjBKjv6OWtzgsuwGCxt7qamBvtScc4o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=y6le9Qhb; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="y6le9Qhb" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5688x8QY1130379; Tue, 8 Jul 2025 03:59:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751965148; bh=P5eeNotykfq5haIV93tVSq9+9IqgohNN8/O839jOTfY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=y6le9Qhbq1Dnz9TckdShRiRu92aZud2VyfZ/g1QLkRdpwDN7w7ahH8sAndbaTqE1o F7fljHv9qpgsGiCf+37tjPsa7AkOA2sM3bMFpjMhn8r7Re7mcJInzS+wTkWS78qYp7 ULrkbpzAcNwKv95IGA86zrpFwhql/PffzJNTJmcg= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5688x8FS858569 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 8 Jul 2025 03:59:08 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 8 Jul 2025 03:59:07 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 8 Jul 2025 03:59:07 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5688x6GD1496963; Tue, 8 Jul 2025 03:59:07 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v7 1/4] arm64: dts: ti: Add bootph property to nodes at source for am62a Date: Tue, 8 Jul 2025 14:28:36 +0530 Message-ID: <20250708085839.1498505-2-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250708085839.1498505-1-p-bhagat@ti.com> References: <20250708085839.1498505-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add bootph property directly into the original definitions of relevant nodes (e.g., power domains, USB controllers, and other peripherals) within their respective DTSI files (ex. main, mcu, and wakeup) for am62a. By defining bootph in the nodes source definitions instead of appending it later in final DTS files, this change ensures that the property is inherently present wherever the nodes are reused across derived device trees. Signed-off-by: Paresh Bhagat Reviewed-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 2 ++ 2 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index 63e097ddf988..44e7e459f176 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -51,6 +51,7 @@ phy_gmii_sel: phy@4044 { compatible =3D "ti,am654-phy-gmii-sel"; reg =3D <0x4044 0x8>; #phy-cells =3D <1>; + bootph-all; }; =20 epwm_tbclk: clock-controller@4130 { @@ -96,6 +97,7 @@ secure_proxy_main: mailbox@4d000000 { #mbox-cells =3D <1>; interrupt-names =3D "rx_012"; interrupts =3D ; + bootph-all; }; =20 inta_main_dmss: interrupt-controller@48000000 { @@ -131,6 +133,7 @@ main_bcdma: dma-controller@485c0100 { ti,sci-rm-range-bchan =3D <0x20>; /* BLOCK_COPY_CHAN */ ti,sci-rm-range-rchan =3D <0x21>; /* SPLIT_TR_RX_CHAN */ ti,sci-rm-range-tchan =3D <0x22>; /* SPLIT_TR_TX_CHAN */ + bootph-all; }; =20 main_pktdma: dma-controller@485c0000 { @@ -147,6 +150,8 @@ main_pktdma: dma-controller@485c0000 { "ring", "tchan", "rchan", "rflow"; msi-parent =3D <&inta_main_dmss>; #dma-cells =3D <2>; + bootph-all; + ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <30>; ti,sci-rm-range-tchan =3D <0x23>, /* UNMAPPED_TX_CHAN */ @@ -220,16 +225,19 @@ dmsc: system-controller@44043000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -254,6 +262,7 @@ secure_proxy_sa3: mailbox@43600000 { * firmware on non-MPU processors */ status =3D "disabled"; + bootph-all; }; =20 main_pmx0: pinctrl@f4000 { @@ -282,6 +291,7 @@ main_timer0: timer@2400000 { assigned-clock-parents =3D <&k3_clks 36 3>; power-domains =3D <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + bootph-all; }; =20 main_timer1: timer@2410000 { @@ -651,6 +661,7 @@ usb0: usb@31000000 { interrupt-names =3D "host", "peripheral"; maximum-speed =3D "high-speed"; dr_mode =3D "otg"; + bootph-all; snps,usb2-gadget-lpm-disable; snps,usb2-lpm-disable; }; @@ -745,6 +756,7 @@ cpsw_port1: port@1 { phys =3D <&phy_gmii_sel 1>; mac-address =3D [00 00 00 00 00 00]; ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; + bootph-all; }; =20 cpsw_port2: port@2 { @@ -764,6 +776,7 @@ cpsw3g_mdio: mdio@f00 { clocks =3D <&k3_clks 13 0>; clock-names =3D "fck"; bus_freq =3D <1000000>; + bootph-all; }; =20 cpts@3d000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index 259ae6ebbfb5..9ef1c829a9df 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -17,6 +17,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; =20 opp_efuse_table: syscon@18 { @@ -67,6 +68,7 @@ wkup_uart0: serial@0 { reg =3D <0 0x100>; interrupts =3D ; status =3D "disabled"; + bootph-pre-ram; }; }; =20 --=20 2.34.1