From nobody Tue Oct 7 19:28:33 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FFA1220F3F; Tue, 8 Jul 2025 08:43:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751964196; cv=none; b=RjkRrw8M4OY1SzcwwOzQSAk42GQv3sKmlbqA012RI/eM85XDCeSNlrV6loJIc3zVyOuzHeB+Xho2iqUWJSFTPYB62r9SHUwcTXkLuAQBJVmiBsJl8KYaIL6OJiGR58hGTaPzptTKaORJtDUywd6y0PwH9x3/02YaGHaPZd5FscY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751964196; c=relaxed/simple; bh=5YDH1141umgB4N/RjMjRIMHOMnox94txJ12BSfHAnCw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FNNSkkM8qCRTm/7H9pvbug2MpmsR1V+MZ/N7FzJg7C93u6sE4sUKOA96FD066IXJQ+OfJFXoDnypAtkP5jNa+F96GgOICwjKhSwIn1SX3B2UDADivctBdcn0J/qi9/dfwEqeeYZZsPrh/xUENBIxM7o7e7EEbwKLBDh04wTz5uY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=r1h2RNfA; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="r1h2RNfA" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5688h8tI1106667; Tue, 8 Jul 2025 03:43:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751964188; bh=FHoskmb3DJi/U+ZNZVaudRs269s2afu05qdvCXbp/98=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=r1h2RNfAF3W+Ma8ZSvs0rYCduqebd6AnNa+OCgQAadtdGwteQ+/JcCsPIQEphdTYf dQxnFmkQlCH/dRlEUxZXvxrOsbz+A2/KP3ZckbkYIWfDrNdQ4Y0rE+q2dUQnbQlAuS dGzZfBOttSZ6t2ekL/i5tDQLl6A1JtRM2d4B+pfc= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5688h87g1287333 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 8 Jul 2025 03:43:08 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 8 Jul 2025 03:43:07 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 8 Jul 2025 03:43:07 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5688h7T01768216; Tue, 8 Jul 2025 03:43:07 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , CC: , , , , Roger Quadros Subject: [PATCH v5 2/4] arm64: dts: ti: k3-am62p5-sk: Add bootph-all property to enable Ethernet boot Date: Tue, 8 Jul 2025 14:12:50 +0530 Message-ID: <20250708084252.1028191-3-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250708084252.1028191-1-c-vankar@ti.com> References: <20250708084252.1028191-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot for AM62P5-SK. Reviewed-by: Roger Quadros Signed-off-by: Chintan Vankar --- Changes from v4 to v5: - Split [PATCH v4 2/2] to [PATCH v5 2/4] and [PATCH v5 3/4]. - Added properties to board specific files. Link to v4: https://lore.kernel.org/r/20250429072644.2400295-3-c-vankar@ti.com/ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 83c37de7d338..58be0f5d8702 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -214,6 +214,10 @@ sound_master: simple-audio-card,codec { }; }; =20 +&phy_gmii_sel { + bootph-all; +}; + &main_gpio0 { bootph-all; }; @@ -267,6 +271,7 @@ main_mdio1_pins_default: main-mdio1-default-pins { AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ >; + bootph-all; }; =20 main_mmc1_pins_default: main-mmc1-default-pins { @@ -547,6 +552,7 @@ &cpsw_port1 { phy-mode =3D "rgmii-rxid"; phy-handle =3D <&cpsw3g_phy0>; status =3D "okay"; + bootph-all; }; =20 &cpsw_port2 { @@ -562,6 +568,7 @@ &cpsw3g_mdio { =20 cpsw3g_phy0: ethernet-phy@0 { reg =3D <0>; + bootph-all; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; --=20 2.34.1