From nobody Tue Oct 7 19:28:33 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF2F62BE038; Tue, 8 Jul 2025 08:43:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751964196; cv=none; b=uTMeinc4fEBtIjAG2fNX/JVBqrr2Kk6ZtutYSyL/RVQaySiRB1quGSFdQjHAS238Hz3ATcd3LxOfLbA8ZJiEvhsGtdubZ2U9AjwCoUhozd9tkrQQvrs3s5v6/ZUuewjupqp7e7bUja1kid4/qBULCGjFVrCTCRA+Lt/o7aY/0Fo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751964196; c=relaxed/simple; bh=USHzvjQLjuliLOyj5WuDHkEPrIamnlob3NFVy/g8z8s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mvYA8x3A4UF3ajh1aY4r+9gfVo+jfHTOVlSf9ywBTRvra7sRZrwSWDfSmbpgb3nVTBjPKm0fEzHAY7XwBuSupeMLW+d4QwEOiz1BAuGOfTi3yeRkZQrLZ5D4Z7r5FafvuPwSipYC6LYY/YFHLeWVfDCPXwhcIAn7L33t0IrZqwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ZnzshLQi; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ZnzshLQi" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5688h6WV1127907; Tue, 8 Jul 2025 03:43:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751964186; bh=3/pGmmdajVxNwT5tDRcZXsQU6jBB855KwO+eJ6aQvBA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZnzshLQiqsrNfdCrVOlkDsQPtZDQB+vonh2jfXVXDs16I9aMFsLZk6ZqycHkKbM5k I+3D1jOy8xemDV/oIF9ZmYXP/eVQpgDA1ZrqUsXRJBVNN+Ror+Y7rRHii3wiIZxZ4L SlMq77o2053YNlKXmNWV7uvM2r1RzKRiWnAKRG0I= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5688h6dT2215240 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 8 Jul 2025 03:43:06 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 8 Jul 2025 03:43:06 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 8 Jul 2025 03:43:06 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5688h5Kh1768158; Tue, 8 Jul 2025 03:43:06 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , CC: , , , Subject: [PATCH v5 1/4] arm64: dts: ti: k3-am68-sk-base-board: Add bootph-all property to enable Ethernet boot Date: Tue, 8 Jul 2025 14:12:49 +0530 Message-ID: <20250708084252.1028191-2-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250708084252.1028191-1-c-vankar@ti.com> References: <20250708084252.1028191-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot on SK-AM68. Reviewed-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- Changes from v4 to v5: - No changes. Link to v4: https://lore.kernel.org/r/20250429072644.2400295-1-c-vankar@ti.com/ arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 5fa70a874d7b..e84c504c87d2 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -344,6 +344,7 @@ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RG= MII1_TD3 */ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; + bootph-all; }; =20 mcu_mdio_pins_default: mcu-mdio-default-pins { @@ -351,6 +352,7 @@ mcu_mdio_pins_default: mcu-mdio-default-pins { J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; + bootph-all; }; =20 mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -412,6 +414,14 @@ J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_G= PIO0_49 */ }; }; =20 +&cpsw_mac_syscon { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + &main_gpio0 { status =3D "okay"; pinctrl-names =3D "default"; @@ -626,6 +636,7 @@ &mcu_cpsw { &davinci_mdio { phy0: ethernet-phy@0 { reg =3D <0>; + bootph-all; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; @@ -635,6 +646,7 @@ phy0: ethernet-phy@0 { &cpsw_port1 { phy-mode =3D "rgmii-rxid"; phy-handle =3D <&phy0>; + bootph-all; }; =20 &mcu_mcan0 { --=20 2.34.1