From nobody Tue Oct 7 17:48:37 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 245FD29E0F4; Tue, 8 Jul 2025 08:11:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751962273; cv=none; b=bWJCZbH8jPBZ/8Ak6C47QCSHeDIwolvcwhAIYEl8BeS61a+rA/HT1kUqcIvnLkpIHR9BLYHU9qasUNmpXSHyu/CG5XG9YFk4HussuhujSykhxqHPvsV92lKYGCMqli9azz0wpaaoVslmDFIOaLjNia47FZJjmdtcFaB4syWCLBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751962273; c=relaxed/simple; bh=2KBI/He/+9WaeB5e2qZq2toSVw6Z840hdBFA1BSC5CI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jvVOcNf9yM1EC7ZPeH9HVQw2NVG8WPrK9bKC/nCbgbrUzRh5gJanjs7bVkaZ0iDdWuIvly+giikKj6WmaYFVyfHW+PD+2ysU2srAZolmsHe3paYotNehBq84hW+vkaZ6zDp42HdhRHiXsCiQwK4GftXi8lS3IEAfRaZ8uZ75U5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=R6JKbm3z; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="R6JKbm3z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751962272; x=1783498272; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2KBI/He/+9WaeB5e2qZq2toSVw6Z840hdBFA1BSC5CI=; b=R6JKbm3zBizx+mbm+HduKZIZfOdzS7sBxuSvaO4nYCWnpDQqFXjMn970 hoIGOQyyS+6M1wlminWaTiQc3RYD3jwd5Wax7DhbJy0hz59Wgn83T8dYE 46tBbzZ8Uav8qAPaV9HFX/Ra6wenxAqlY5w1XJkF0R40Qe7RW8VC1p8IG SVZMZZB9ddFMjE6m/OwZaRhDBZwy6St/GiEztMyV8ABaXrCiOG8j7XduA oCT53IRPqQqW9IyVcD0dbEuTFogHbSdZiD+JUyyR/IyEDY7YXCzGRYSaB lxzBxX++Q81bUgoIh9JdPY46EMVusmC660g/0N8pcsLxdBz3FUbiRjdzz g==; X-CSE-ConnectionGUID: eBpEiNJlTuqxuFujXe6J/w== X-CSE-MsgGUID: MTmvZA1LSVma7U81HOfBuA== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="65543219" X-IronPort-AV: E=Sophos;i="6.16,296,1744095600"; d="scan'208";a="65543219" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 01:11:11 -0700 X-CSE-ConnectionGUID: CpwIvPRvQW2/kfAwrIRbVg== X-CSE-MsgGUID: HwxByaVjTrugqPCqFKxbVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,296,1744095600"; d="scan'208";a="161076600" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa005.jf.intel.com with ESMTP; 08 Jul 2025 01:11:07 -0700 From: Xiaoyao Li To: Dave Hansen , Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, "Kirill A. Shutemov" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , Xiaoyao Li , rick.p.edgecombe@intel.com, Kai Huang , binbin.wu@linux.intel.com, yan.y.zhao@intel.com, reinette.chatre@intel.com, isaku.yamahata@intel.com, adrian.hunter@intel.com, tony.lindgren@intel.com Subject: [PATCH 1/2] x86/tdx: Fix the typo of TDX_ATTR_MIGRTABLE Date: Tue, 8 Jul 2025 16:03:13 +0800 Message-ID: <20250708080314.43081-2-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250708080314.43081-1-xiaoyao.li@intel.com> References: <20250708080314.43081-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix the typo of TDX_ATTR_MIGRTABLE to TDX_ATTR_MIGRATABLE. Reviewed-by: Kirill A. Shutemov Signed-off-by: Xiaoyao Li Reviewed-by: Kai Huang --- arch/x86/coco/tdx/debug.c | 2 +- arch/x86/include/asm/shared/tdx.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/coco/tdx/debug.c b/arch/x86/coco/tdx/debug.c index cef847c8bb67..28990c2ab0a1 100644 --- a/arch/x86/coco/tdx/debug.c +++ b/arch/x86/coco/tdx/debug.c @@ -17,7 +17,7 @@ static __initdata const char *tdx_attributes[] =3D { DEF_TDX_ATTR_NAME(ICSSD), DEF_TDX_ATTR_NAME(LASS), DEF_TDX_ATTR_NAME(SEPT_VE_DISABLE), - DEF_TDX_ATTR_NAME(MIGRTABLE), + DEF_TDX_ATTR_NAME(MIGRATABLE), DEF_TDX_ATTR_NAME(PKS), DEF_TDX_ATTR_NAME(KL), DEF_TDX_ATTR_NAME(TPA), diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index 8bc074c8d7c6..11f3cf30b1ac 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -35,8 +35,8 @@ #define TDX_ATTR_LASS BIT_ULL(TDX_ATTR_LASS_BIT) #define TDX_ATTR_SEPT_VE_DISABLE_BIT 28 #define TDX_ATTR_SEPT_VE_DISABLE BIT_ULL(TDX_ATTR_SEPT_VE_DISABLE_BIT) -#define TDX_ATTR_MIGRTABLE_BIT 29 -#define TDX_ATTR_MIGRTABLE BIT_ULL(TDX_ATTR_MIGRTABLE_BIT) +#define TDX_ATTR_MIGRATABLE_BIT 29 +#define TDX_ATTR_MIGRATABLE BIT_ULL(TDX_ATTR_MIGRATABLE_BIT) #define TDX_ATTR_PKS_BIT 30 #define TDX_ATTR_PKS BIT_ULL(TDX_ATTR_PKS_BIT) #define TDX_ATTR_KL_BIT 31 --=20 2.43.0 From nobody Tue Oct 7 17:48:37 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A0EC2BD590; Tue, 8 Jul 2025 08:11:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751962278; cv=none; b=j4T5r10rZ2J+gXcYRAsZ1sDI4tv5QMX7TB+ANaovkYCW6Qy2gTYFDXZvE9QYbTj9Qdgvezg9oGtXrMI3YNLDkWlqs4kZuFpqDux3l0sWOrIyNiPoaRjT8jObaui+dA+ouZPnm4sf5gbcPPFW9czuB29+CRp8puEAFKUzZOKYBR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751962278; c=relaxed/simple; bh=ZB9nCtjrRzq0q0am81PMOUb3zQxW12guoujcDogZtQ0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aumv7MapxIQwwLjjLsFrNhxxBva9fsd6UI37B5OAjsl39dy6jeJqUVnQyVqzu5dB4FPmeJLYAWbNhjFVnSAoRXCSBKHrKW82d4mjUiyrW81KCm6THID8jlwT/rhCtgD4gL3CThA/CAqAy3cIiJEQL+47eGVwSE18KYdoC/Yp1Ds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L/V/K1pm; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L/V/K1pm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751962277; x=1783498277; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZB9nCtjrRzq0q0am81PMOUb3zQxW12guoujcDogZtQ0=; b=L/V/K1pmZxjDBfvvX5ZO1q29vTNFAIsbA1dmNNaK5bzU+kpUO8+SQi5C VNNhP/p7rX/NfMBLuOPsIFi+ttRzHpspvzOkS5z30YBiHqx2Nq1lgaQpm WywAiFHEPgm5YcJcblveuIM6YSBaCC6rIj80IBm99+WD+gYngOnKxmQnW A+UhEky21tQnoN/NX2A+PrbGx9DpMsbIHeTEr56uugiiqIoTtBGxHVsiH OF0WNppA99FHTditu0pACimOknHKDwehoSJUDokHt+ryctizLa35BMqV5 5jTUxq+W6+RF/Sy5RM1zBplgUuVJVv80VuPe9AWEo77CJLysknl5Qtc3a Q==; X-CSE-ConnectionGUID: wIUWDEzERTeAP5d2s6hFRA== X-CSE-MsgGUID: +GvZPJo6SdqrAL3cvcysGg== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="65543234" X-IronPort-AV: E=Sophos;i="6.16,296,1744095600"; d="scan'208";a="65543234" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 01:11:16 -0700 X-CSE-ConnectionGUID: mCinE0+bR5yOWsiN1/46qw== X-CSE-MsgGUID: Te2HtNq9QlKgRWGeN5AyEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,296,1744095600"; d="scan'208";a="161076605" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa005.jf.intel.com with ESMTP; 08 Jul 2025 01:11:12 -0700 From: Xiaoyao Li To: Dave Hansen , Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, "Kirill A. Shutemov" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , Xiaoyao Li , rick.p.edgecombe@intel.com, Kai Huang , binbin.wu@linux.intel.com, yan.y.zhao@intel.com, reinette.chatre@intel.com, isaku.yamahata@intel.com, adrian.hunter@intel.com, tony.lindgren@intel.com Subject: [PATCH 2/2] KVM: TDX: Remove redundant definitions of TDX_TD_ATTR_* Date: Tue, 8 Jul 2025 16:03:14 +0800 Message-ID: <20250708080314.43081-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250708080314.43081-1-xiaoyao.li@intel.com> References: <20250708080314.43081-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are definitions of TD attributes bits inside asm/shared/tdx.h as TDX_ATTR_*. Remove KVM's definitions and use the ones in asm/shared/tdx.h Reviewed-by: Kirill A. Shutemov Signed-off-by: Xiaoyao Li Reviewed-by: Kai Huang --- arch/x86/kvm/vmx/tdx.c | 4 ++-- arch/x86/kvm/vmx/tdx_arch.h | 6 ------ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index c539c2e6109f..efb7d589b672 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -62,7 +62,7 @@ void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass,= char *op, u32 field, pr_err("TDH_VP_WR[%s.0x%x]%s0x%llx failed: 0x%llx\n", uclass, field, op, = val, err); } =20 -#define KVM_SUPPORTED_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE) +#define KVM_SUPPORTED_TD_ATTRS (TDX_ATTR_SEPT_VE_DISABLE) =20 static __always_inline struct kvm_tdx *to_kvm_tdx(struct kvm *kvm) { @@ -700,7 +700,7 @@ int tdx_vcpu_create(struct kvm_vcpu *vcpu) vcpu->arch.l1_tsc_scaling_ratio =3D kvm_tdx->tsc_multiplier; =20 vcpu->arch.guest_state_protected =3D - !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_TD_ATTR_DEBUG); + !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_ATTR_DEBUG); =20 if ((kvm_tdx->xfam & XFEATURE_MASK_XTILE) =3D=3D XFEATURE_MASK_XTILE) vcpu->arch.xfd_no_write_intercept =3D true; diff --git a/arch/x86/kvm/vmx/tdx_arch.h b/arch/x86/kvm/vmx/tdx_arch.h index a30e880849e3..350143b9b145 100644 --- a/arch/x86/kvm/vmx/tdx_arch.h +++ b/arch/x86/kvm/vmx/tdx_arch.h @@ -75,12 +75,6 @@ struct tdx_cpuid_value { u32 edx; } __packed; =20 -#define TDX_TD_ATTR_DEBUG BIT_ULL(0) -#define TDX_TD_ATTR_SEPT_VE_DISABLE BIT_ULL(28) -#define TDX_TD_ATTR_PKS BIT_ULL(30) -#define TDX_TD_ATTR_KL BIT_ULL(31) -#define TDX_TD_ATTR_PERFMON BIT_ULL(63) - #define TDX_EXT_EXIT_QUAL_TYPE_MASK GENMASK(3, 0) #define TDX_EXT_EXIT_QUAL_TYPE_PENDING_EPT_VIOLATION 6 /* --=20 2.43.0