From nobody Tue Oct 7 19:25:31 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26BF01F0E58; Tue, 8 Jul 2025 06:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751957751; cv=none; b=j4sBAFMzMlma21zWDA98JDhILk/bybeYsyW+jvTu4yGmMn6UD8ZUqbzCzdl2+DPBmanTQrDwMHEqGX8qiOaVE6S95GIMEY9cfbtKu3TUtt7WRqFEMMogfKdPWobB3zwqdYR4haGrtIyltDHcrv2wOsznhkiIDi8sc+yOssZClUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751957751; c=relaxed/simple; bh=Ts6wjIPrgq/fmJpANSvpSlmzgn5ELYhYJWwDDY73F1A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JRba1ZnezG8kq6GIEX0zBHguLKZYbvRfhrFYplI5VzYLZLix2GJcYNXrHgOxjyAjiA0BPfxBnTG0psZ/AisH2qFUM0pGlYCEnQakRHrZDHnN9sSwK5+osjYVBt6cWZiUiwb6be6WZ/T8JXi5CL0zQT1KOt+4CGeR++y0gtGbnIw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 8 Jul 2025 14:55:44 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 8 Jul 2025 14:55:44 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [net-next v3 1/4] dt-bindings: net: ftgmac100: Add resets property Date: Tue, 8 Jul 2025 14:55:41 +0800 Message-ID: <20250708065544.201896-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250708065544.201896-1-jacky_chou@aspeedtech.com> References: <20250708065544.201896-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add optional resets property for Aspeed SoCs to reset the MAC and RGMII/RMII. Signed-off-by: Jacky Chou --- .../bindings/net/faraday,ftgmac100.yaml | 23 ++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b= /Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml index 55d6a8379025..a2e7d439074a 100644 --- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml +++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Faraday Technology FTGMAC100 gigabit ethernet controller =20 -allOf: - - $ref: ethernet-controller.yaml# - maintainers: - Po-Yu Chuang =20 @@ -35,6 +32,11 @@ properties: - description: MAC IP clock - description: RMII RCLK gate for AST2500/2600 =20 + resets: + maxItems: 1 + description: + Optional reset control for the MAC controller + clock-names: minItems: 1 items: @@ -74,6 +76,21 @@ required: - reg - interrupts =20 +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - aspeed,ast2600-mac + then: + properties: + resets: true + else: + properties: + resets: false + unevaluatedProperties: false =20 examples: --=20 2.34.1