From nobody Tue Oct 7 16:38:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2815273FE; Tue, 8 Jul 2025 12:47:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751978853; cv=none; b=MY/FTBR8zf6gddf+gr1V57Nif4ra2zO2jq7EE/Q40pgp5DlAeVrBC4gTySwvVJydXEcbJWH6ket8DCKADBeqUbFIU/tsQOriaqNsmvkDZ2tfZFxpOtkyHzfwwQQ5HmqSOGp0oC+6knSZKpSw12zN/6I85xjxGEkOQzRgvphwdzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751978853; c=relaxed/simple; bh=pj0ToWAvdk9MImwS3ciwuKF14EHt+YZ/Vr1onTRPAXg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DKxNeIY063JvLkT7HeJSgEFNgM8jTwiYi/qUu0lm7wMHAdZFC5n29DRiKRATP3iAwM25nj78E6t8dNl9ZD2KtjNWM1zRro9+2CJeQXkqtpjT9d7877J/wQW8S+eqXn8YbBMEFpffIqAN5/PRTwXqJT8uBq432RBMjVgFInt9dGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d1XCvHLr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d1XCvHLr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5034DC4CEED; Tue, 8 Jul 2025 12:47:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751978852; bh=pj0ToWAvdk9MImwS3ciwuKF14EHt+YZ/Vr1onTRPAXg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=d1XCvHLrBkkqO5o0qeKA8yHV8+qJUjbYkSRtoGQrMLSeqpMRZEac02U4/4bUWcMlu nJFJJmLPsK91nYcHJoUz7/XVcGdhuHwmbtKkdjF6IFwiEyZjn7TOkcCmQafzkgyREe bGHKvtqqIBhnVG7p8F2L0uQ648spfhlEkdfXSLfa89X7Q6ZbadBMOSDnDoA4Krs/gj 7tiGFMmv5omBZF2dt9hXX7sG+87fKIJP10aQwSvXF64oCxDWvNXoIDA/oBDZDOwN57 ZNPmmVQhCaq2hCYKnEdSDufE4aaHhseCI1fdd3wSaADTCJyO0lRZ45WpVASHtefUqt FALQr8GUkRwxQ== From: Konrad Dybcio Date: Tue, 08 Jul 2025 14:47:20 +0200 Subject: [PATCH 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-topic-8750_gpucc-v1-1-86c86a504d47@oss.qualcomm.com> References: <20250708-topic-8750_gpucc-v1-0-86c86a504d47@oss.qualcomm.com> In-Reply-To: <20250708-topic-8750_gpucc-v1-0-86c86a504d47@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751978844; l=5467; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=P7PMEJhRaxNBrvzCQCl5zw5RaGZ5DA+9rz7azhDMEXs=; b=1dU7A4zSImcMlBNwxqiNoRN0wsWoYH3NXVIBkq9arDfCP73iW4A4dHAMIgkfJG6DHuorV9Afa SMLa6lfpKvtCJBMdtpRedzwLvuOlc87aIhnrb5sf4qxH2glh1mf9sdT X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The SM8750 features a "traditional" GPU_CC block, much of which is controlled through the GMU microcontroller. Additionally, there's an separate GX_CC block, where the GX GDSC is moved. Add bindings to accommodate for that. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 5 ++ .../bindings/clock/qcom,sm8750-gxcc.yaml | 58 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,sm8750-gpucc.h | 53 ++++++++++++++++++= ++ 3 files changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 02968632fb3af34d6b3983a6a24aa742db1d59b1..d1b3557ab344b071d16dba4d5c6= a267b7ab70573 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -20,6 +20,7 @@ description: | include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h + include/dt-bindings/reset/qcom,sm8750-gpucc.h include/dt-bindings/reset/qcom,x1e80100-gpucc.h =20 properties: @@ -31,6 +32,7 @@ properties: - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc + - qcom,sm8750-gpucc - qcom,x1e80100-gpucc - qcom,x1p42100-gpucc =20 @@ -40,6 +42,9 @@ properties: - description: GPLL0 main branch source - description: GPLL0 div branch source =20 + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f35839193d18b608e177b4d6561= 827dfa98c9aa1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8750-gxcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM8750 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and p= ower + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/reset/qcom,sm8750-gpucc.h + +properties: + compatible: + enum: + - qcom,sm8750-gxcc + + reg: + maxItems: 1 + + power-domains: + maxItems: 3 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - power-domains + - '#power-domain-cells' + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@3d64000 { + compatible =3D "qcom,sm8750-gxcc"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_MXC>, + <&gpucc GPU_CC_CX_GDSC>; + #power-domain-cells =3D <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bin= dings/clock/qcom,sm8750-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..98e2f5df78740bf298c6b106597= 2d7e58ee81713 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_ACD_AHB_FF_CLK 13 +#define GPU_CC_GX_AHB_FF_CLK 14 +#define GPU_CC_GX_GMU_CLK 15 +#define GPU_CC_GX_RCG_AHB_FF_CLK 16 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_GPU_CC_CB_BCR 0 +#define GPU_CC_GPU_CC_CX_BCR 1 +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GPU_CC_FF_BCR 3 +#define GPU_CC_GPU_CC_GMU_BCR 4 +#define GPU_CC_GPU_CC_GX_BCR 5 +#define GPU_CC_GPU_CC_XO_BCR 6 + +/* GX_CC power domains */ +#define GX_CC_GX_GDSC 0 + +#endif --=20 2.50.0 From nobody Tue Oct 7 16:38:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE08A273FE; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AhHHjPov" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C6CE1C4CEF1; Tue, 8 Jul 2025 12:47:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751978856; bh=N31nWrVb/C3gwEWVst/IKabeIc+AzTRKmL5+kLekyaw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AhHHjPovoyE7wIEXTDoohINxCMgQKZK8YXOTbK4p9sfJ04l87uBMrQ8ODbGk3uBvT 0NWhliK0ylPChL+BG6FmbhPfOqkgIWIClQW0xmAUTYE5o5vzAKfcheoQKigkvCLyBA S+5YKdjIVKpuQoWj18o18axafx34oG6lVUVJyn1Jb2aH940n8+6kfegQesXWvi67SN T58fGPFj5yMaQvxlqmHdtResu/eC6U8fXTMLYzg/UjpWqQgyfBaltxWJWApJY9WIT1 40/c+sum5K70HCIZ+0An0Jz+VMH1UeNa7/R+vov7VExJ5bvJ48vjEQO2oadmoiUs3O 8c73ENYmWecbg== From: Konrad Dybcio Date: Tue, 08 Jul 2025 14:47:21 +0200 Subject: [PATCH 2/3] clk: qcom: Add a driver for SM8750 GPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-topic-8750_gpucc-v1-2-86c86a504d47@oss.qualcomm.com> References: <20250708-topic-8750_gpucc-v1-0-86c86a504d47@oss.qualcomm.com> In-Reply-To: <20250708-topic-8750_gpucc-v1-0-86c86a504d47@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751978844; l=16679; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=L8yXzcC4NPE7CAlvhnVhzKI94mQv61dcfqikD5recoY=; b=ZVbnOdeV6dseu/tFjygsqpYLpltFXWGVE5o24W/5wpVhjen/dfU7ZBGLmg8BP2IOo61F3mAgQ hOeGuKtJ9SgD818u2Ilhz9kfR9ky9jBB/Xg3QlbO7RBOMrVFgSLbEtJ X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The SM8750's GFX hardware is largely clocked by two domains: GPU_CC (which is very similar to the ones on previous SoCs) and GX_CC (where the GX GDSC now resides). As usual, the GMU drives most of the clocks and Linux only manages a subset required to boot it (and the SMMU) up. Add a driver to accommodate for that. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8750.c | 524 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 534 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 36d6e6e1e7f0162d53f02f39125f4593517e0dba..9f430fcee3ef4e44dbf8f6277d7= bf85888dedd59 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1295,6 +1295,15 @@ config SM_GPUCC_8650 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SM_GPUCC_8750 + tristate "SM8750 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8750 + help + Support for the graphics clock controller on SM8750 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_LPASSCC_6115 tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ab59434338bb6d6f49b0af94ff0f85cb386a16db..b55f373d71e136eaa279ed3ea8e= 8714119ecfd70 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -161,6 +161,7 @@ obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_GPUCC_8450) +=3D gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) +=3D gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) +=3D gpucc-sm8650.o +obj-$(CONFIG_SM_GPUCC_8750) +=3D gpucc-sm8750.o obj-$(CONFIG_SM_LPASSCC_6115) +=3D lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) +=3D tcsrcc-sm8650.o diff --git a/drivers/clk/qcom/gpucc-sm8750.c b/drivers/clk/qcom/gpucc-sm875= 0.c new file mode 100644 index 0000000000000000000000000000000000000000..ea8e5a87778d87745f29b115185= ba7b0fa4c43e1 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8750.c @@ -0,0 +1,524 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_elu_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x34, + .alpha =3D 0x1555, + .config_ctl_val =3D 0x19660387, + .config_ctl_hi_val =3D 0x098060a0, + .config_ctl_hi1_val =3D 0xb416cb20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D taycan_elu_vco, + .num_vco =3D ARRAY_SIZE(taycan_elu_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_elu_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpu_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_elu_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .fw_name =3D "bi_tcxo" }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0_out_even.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .fw_name =3D "gpll0_out_main" }, + { .fw_name =3D "gpll0_out_main_div" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(687500000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x93ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src =3D { + .reg =3D 0x942c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x90bc, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x90bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x910c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x910c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x90d4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x90e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x90e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk =3D { + .halt_reg =3D 0x9010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_demet_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk =3D { + .halt_reg =3D 0x9110, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_dpm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x900c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x900c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x9070, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x9060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x93e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x93e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x90e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x90f4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x9080, + .gds_hw_ctrl =3D 0x9094, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x8, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm8750_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] =3D &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] =3D &gpu_cc_dpm_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] =3D &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_EVEN] =3D &gpu_cc_pll0_out_even.clkr, +}; + +static struct gdsc *gpu_cc_sm8750_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sm8750_resets[] =3D { + [GPU_CC_GPU_CC_XO_BCR] =3D { 0x9000 }, + [GPU_CC_GPU_CC_GX_BCR] =3D { 0x905c }, + [GPU_CC_GPU_CC_CX_BCR] =3D { 0x907c }, + [GPU_CC_GPU_CC_GMU_BCR] =3D { 0x9314 }, + [GPU_CC_GPU_CC_CB_BCR] =3D { 0x93a0 }, + [GPU_CC_GPU_CC_FAST_HUB_BCR] =3D { 0x93e4 }, +}; + +static const struct regmap_config gpu_cc_sm8750_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9800, + .fast_io =3D true, +}; + +static struct clk_alpha_pll *gpu_cc_alpha_plls[] =3D { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_sm8750_critical_cbcrs[] =3D { + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x9064, /* GPU_CC_GX_AHB_FF_CLK */ + 0x90cc, /* GPU_CC_SLEEP_CLK */ + 0x93a4, /* GPU_CC_CB_CLK */ + 0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */ +}; + +static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data =3D { + .alpha_plls =3D gpu_cc_alpha_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_alpha_plls), + .clk_cbcrs =3D gpu_cc_sm8750_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_sm8750_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_sm8750_desc =3D { + .config =3D &gpu_cc_sm8750_regmap_config, + .clks =3D gpu_cc_sm8750_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_sm8750_clocks), + .resets =3D gpu_cc_sm8750_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_sm8750_resets), + .gdscs =3D gpu_cc_sm8750_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_sm8750_gdscs), + .driver_data =3D &gpu_cc_sm8750_driver_data, +}; + +static const struct of_device_id gpu_cc_sm8750_match_table[] =3D { + { .compatible =3D "qcom,sm8750-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8750_match_table); + +static int gpu_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_sm8750_desc); +} + +static struct platform_driver gpu_cc_sm8750_driver =3D { + .probe =3D gpu_cc_sm8750_probe, + .driver =3D { + .name =3D "sm8750-gpucc", + .of_match_table =3D gpu_cc_sm8750_match_table, + }, +}; +module_platform_driver(gpu_cc_sm8750_driver); + +static struct gdsc gx_cc_gx_gdsc =3D { + .gdscr =3D 0x4024, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gx_cc_gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc *gx_cc_gdscs[] =3D { + [GX_CC_GX_GDSC] =3D &gx_cc_gx_gdsc, +}; + +static const struct regmap_config gx_cc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x6000, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gx_cc_sm8750_desc =3D { + .config =3D &gx_cc_regmap_config, + .gdscs =3D gx_cc_gdscs, + .num_gdscs =3D ARRAY_SIZE(gx_cc_gdscs), + .use_rpm =3D true, +}; + +static const struct of_device_id gx_cc_sm8750_match_table[] =3D { + { .compatible =3D "qcom,sm8750-gxcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gx_cc_sm8750_match_table); + +static int gx_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gx_cc_sm8750_desc); +} + +static struct platform_driver gx_cc_sm8750_driver =3D { + .probe =3D gx_cc_sm8750_probe, + .driver =3D { + .name =3D "gx_cc-sm8750", + .of_match_table =3D gx_cc_sm8750_match_table, + }, +}; +module_platform_driver(gx_cc_sm8750_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM8750 Driver"); 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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=semBo5/H; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="semBo5/H" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A242C4CEED; Tue, 8 Jul 2025 12:47:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751978859; bh=nVcGMtqovNhYLTO5f7VRPEzyfGwo4DPtY/nMhcKEtMw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=semBo5/HZQ3/yrkkXABfj8viKzKZDYYs4/ZA76H6cChJjHFqHQTp/oIdyCXUkkg+h B7am+Njnnl5+y+yOSAetXE6eFt+gZqwhYcsdadO2YSzlVv2mhT575cl/4RdtnqEGoV 2bP5KmArXca7CCsOfJrWcV0TuPDOCDQ1xHi2+WqysPLwVE5j3KRrXkZg+CEYAogfjF 1EqB5H9B3bgKbPx3e/TGj/orxodMDJlril6lJfMD6LcwlYHvkakJaRBh+NdjYwRVak V4OZgJEJsEPrveahrCPvhRckc+3UHP7ib5WsF2UMre8rZ7/jO7XOF1W6BzAmzSI6OV AyRQ60aYqmQ2Q== From: Konrad Dybcio Date: Tue, 08 Jul 2025 14:47:22 +0200 Subject: [PATCH 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-topic-8750_gpucc-v1-3-86c86a504d47@oss.qualcomm.com> References: <20250708-topic-8750_gpucc-v1-0-86c86a504d47@oss.qualcomm.com> In-Reply-To: <20250708-topic-8750_gpucc-v1-0-86c86a504d47@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751978844; l=3538; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=7WkfONM1t9IOjJmIQnSYmNaGuqdmIeuahhgix3BR1tk=; b=Lbh77eD9/3OfcUSBIlsUsj8sjPlqjng4E/ZDYqC6/ERJib2Dqjgs/wCNIbDc26wkLNV+QjxCo glrzhhAnd8wCTNkI0vVa0OSvSx574/1tuiiI4WLV7kyepodxQbQo3Sb X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this is simply a separate block housing the GX GDSC) nodes, required to power up the graphics-related hardware. Make use of it by enabling the associated IOMMU as well. The GPU itself needs some more work and will be enabled later. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 63 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 4643705021c6ca095a16d8d7cc3adac920b21e82..ca0770a34bed64183185aedde04= f1bb96eebfa91 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -3154,6 +3155,68 @@ tcsrcc: clock-controller@f204008 { #reset-cells =3D <1>; }; =20 + gxcc: clock-controller@3d64000 { + compatible =3D "qcom,sm8750-gxcc"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_MXC>, + <&gpucc GPU_CC_CX_GDSC>; + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sm8750-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sm8750-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "hlos"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg =3D <0x0 0x15000000 0x0 0x100000>; --=20 2.50.0