From nobody Tue Oct 7 16:38:14 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E293D22F77E for ; Tue, 8 Jul 2025 19:37:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003458; cv=none; b=BsFG+yEkvU2Mf8nwPE8tqBbUzTDPWv+AqsIzZ0ZBXt8IN79Bs5mssWJ3nBSAD7Mwz+Uljfm49siK1bIb7Rs9CKPYvdXqVUxNFmxjMhiyQiM6tR3vT2ZSnYZoonClxIZe9y6ZIScl+WBXiB8yQUBKTvMdERs0oulS4Xu/oLX06mE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003458; c=relaxed/simple; bh=fJwma0mJDBsY9ZVoxM1qMkYfUKryUIw86A5Ugpb8bzs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lCZFvhsM2icbgZ0zqGBMAT5OJoUnLMQKeQSzJb/KPSCQ+g9lLUBn50TQHC/2prGb9dDaj6rB3cDlxw8qD5sE8TiuvjWNC+xTLDSJ/+t9PGxILDt/utRTWvs2SiI481E9zN0rPsVcMwrcMZq90xTGWd7hyEM0juvZSlFQA6UUzpQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=VIpJrn69; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="VIpJrn69" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752003455; bh=fJwma0mJDBsY9ZVoxM1qMkYfUKryUIw86A5Ugpb8bzs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VIpJrn69xdg63f0kze3ScULFeu855+uLn/DZLbBXAR39bzsGVEyLSzaTiKiWQTx0x o8OajCewUcVbtky8+cp3w8Ehmb/8oBK8BZJ6KD3lHSuiqqvMGs/FVoMFCOL9ZLzqch o+1IvQAp9a6SJSuIqO+VtHzTb/VFFL8LXPy6lJFzIrafURP/JDWXm6vs3fXVKqtebR KYsPfFcCN0/NGmbTgDsCYywag8kdR2q0/KbJsGB7cjom1eOvZT+o7VYSJudVGh0mAV VT3A85djOS/6hUmt6j/Wjtws+gY9Zn6NUcULH9YCDpp8avozHY5/EaisgKWEK1gBO1 e9DJHnKeNjiYg== Received: from localhost (unknown [212.93.144.165]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 3E34317E04AA; Tue, 8 Jul 2025 21:37:35 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:50 +0300 Subject: [PATCH 09/12] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-9-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Improve ->recalc_rate() callback of hdptx_phy_clk_ops to calculate the initial clock rate based on the actual PHY PLL configuration as retrieved from the related HW registers. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 90 +++++++++++++++++++= +++- 1 file changed, 89 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 71b076de7b75f2ba08eae679ded77caa2ba86590..e86bbc270a4ca448f55ca58b4b5= b52d378730d74 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1850,12 +1850,100 @@ static void rk_hdptx_phy_clk_unprepare(struct clk_= hw *hw) rk_hdptx_phy_consumer_put(hdptx, true); } =20 +#define PLL_REF_CLK 24000000ULL + +static unsigned long rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdp= tx_phy *hdptx) +{ + struct ropll_config ropll_hw; + u64 fout, sdm; + u32 mode, val; + int ret; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0008), &mode); + if (ret) + return 0; + + if (mode & LCPLL_LCVCO_MODE_EN_MASK) + return 0; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0051), &val); + if (ret) + return 0; + ropll_hw.pms_mdiv =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(005E), &val); + if (ret) + return 0; + ropll_hw.sdm_en =3D val & ROPLL_SDM_EN_MASK; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0064), &val); + if (ret) + return 0; + ropll_hw.sdm_num_sign =3D val & ROPLL_SDM_NUM_SIGN_RBR_MASK; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0065), &val); + if (ret) + return 0; + ropll_hw.sdm_num =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0060), &val); + if (ret) + return 0; + ropll_hw.sdm_deno =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0069), &val); + if (ret) + return 0; + ropll_hw.sdc_n =3D (val & ROPLL_SDC_N_RBR_MASK) + 3; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(006c), &val); + if (ret) + return 0; + ropll_hw.sdc_num =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0070), &val); + if (ret) + return 0; + ropll_hw.sdc_deno =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0086), &val); + if (ret) + return 0; + ropll_hw.pms_sdiv =3D ((val & PLL_PCG_POSTDIV_SEL_MASK) >> 4) + 1; + + fout =3D PLL_REF_CLK * ropll_hw.pms_mdiv; + if (ropll_hw.sdm_en) { + sdm =3D div_u64(PLL_REF_CLK * ropll_hw.sdc_deno * + ropll_hw.pms_mdiv * ropll_hw.sdm_num, + 16 * ropll_hw.sdm_deno * + (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num)); + + if (ropll_hw.sdm_num_sign) + fout =3D fout - sdm; + else + fout =3D fout + sdm; + } + + fout =3D div_u64(fout * 2, ropll_hw.pms_sdiv * 10); + + return fout; +} + static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + u32 status; + int ret; + + if (hdptx->hw_rate) + return hdptx->hw_rate; + + ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status); + if (ret || !(status & HDPTX_I_PLL_EN)) + return 0; =20 - return hdptx->hw_rate; + return rk_hdptx_phy_clk_calc_rate_from_pll_cfg(hdptx); } =20 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, --=20 2.50.0