From nobody Tue Oct 7 14:51:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B8D62248B3 for ; Tue, 8 Jul 2025 19:36:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003420; cv=none; b=O4ERfd7ycjwyCAMUbSoLlGDGa5J5rrQ1ZhK/IhQnpaIZ26TGuHzdZEMTryWvbm2YuQWqESVnruuWC+bWA9YH+ijw6I/0m3mvWH9zB41zzYiern0Omuob1lsnvUav47SSgiCdlSUcqSUnI9ZbeV02lgRtPDKSfoZZzeIZtfkc0uo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003420; c=relaxed/simple; bh=DZ07FftUuUFoLz4dKR+5e4A2hHQAYJ90Yq5kFNKzni8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iiBqQYqWQpEhyy38TwNAaVmj6iLmdxFZrOEnKy1J8SALM7jgsXcber13dICE3Ehoas7BmpxgncNebPHuJP9P7Cv5qEMME+d2v3L+DP7j1UovyUaSq00QsEhAxAF5sHCZWAMKVLR8Yt7lsrblTq44OUEFU+IlKFtTbziSHkVUpiM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=OTNtPggK; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="OTNtPggK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752003416; bh=DZ07FftUuUFoLz4dKR+5e4A2hHQAYJ90Yq5kFNKzni8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=OTNtPggKXTdERxFhH4lMVJsacxQUgadDNNhkPIxUrp54Es9Ygo+Ju2DzkDW/3hl/n OXpSL026NPDjW1S2N1Z/zmN2a7bGBwk0nAcCLm0V+F3XBAjvL/zwW8Sy3lAXh4+RL1 Xj32FGjTJJerinQegcP/ZEF2R032B6ikWEFJfcX/HO+KXUgB1m4ZoX0M1najg5TFtd 96P/9UXbypxjZkZMLU3qQZYZVmknqbrTWqEI/Hyfi1CIrKIuqQ0Klw6MTip9nCCYH3 ZmBUjV7okgCe2r6wlFJ9s5uobRdfYqS1neB8QT049AfPVKbxBhcIStXUcT8gf7dLbh TAc1/7T9Mc92w== Received: from localhost (unknown [212.93.144.165]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 6670D17E0FB8; Tue, 8 Jul 2025 21:36:56 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:42 +0300 Subject: [PATCH 01/12] phy: hdmi: Add HDMI 2.1 FRL configuration options Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-1-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Add support for configuring the Fixed Rate Link (FRL) mode for HDMI PHYs. For improved clarity, also rename existing HDMI mode to HDMI_TMDS. Since this mode is currently not being used explicitly, no further changes are needed. Signed-off-by: Cristian Ciocaltea --- include/linux/phy/phy-hdmi.h | 14 ++++++++++++-- include/linux/phy/phy.h | 3 ++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h index f0ec963c6e84f1b7728acafc824dff191c6b873d..0b26472d8defcc9ded142d4283e= 29861dc2b3746 100644 --- a/include/linux/phy/phy-hdmi.h +++ b/include/linux/phy/phy-hdmi.h @@ -6,16 +6,26 @@ #ifndef __PHY_HDMI_H_ #define __PHY_HDMI_H_ =20 +#include + /** * struct phy_configure_opts_hdmi - HDMI configuration set - * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. * @bpc: Bits per color channel. + * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * @frl.rate_per_lane: HDMI FRL Rate per Lane in Gbps. + * @frl.lanes: HDMI FRL lanes count. * * This structure is used to represent the configuration state of a HDMI p= hy. */ struct phy_configure_opts_hdmi { - unsigned long long tmds_char_rate; unsigned int bpc; + union { + unsigned long long tmds_char_rate; + struct { + u8 rate_per_lane; + u8 lanes; + } frl; + }; }; =20 #endif /* __PHY_HDMI_H_ */ diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 13add0c2c40721fe9ca3f0350d13c035cd25af45..04c84c1dbd6dac55fd04c54203c= ff4f9d939d970 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -44,7 +44,8 @@ enum phy_mode { PHY_MODE_SATA, PHY_MODE_LVDS, PHY_MODE_DP, - PHY_MODE_HDMI, + PHY_MODE_HDMI_TMDS, + PHY_MODE_HDMI_FRL, }; =20 enum phy_media { --=20 2.50.0 From nobody Tue Oct 7 14:51:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 257642206A9 for ; Tue, 8 Jul 2025 19:37:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003430; cv=none; b=Egj07vXP/J1zea5Z9jGivGe4nsdTG57/oiOoC/N7kwO566xWX2uDPQwKUSLsHkWT9jtj2NTzwCzoKQ9J7bVpcu2bTc+X2/xAqoDtH8Sk4MpOET6saC5GTsqFeijSr7wpi7DVWKa4Bb2oe+rokXi2+J1BBWXJ2Ge+rW1l4LPLVN4= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-2-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Due to its relatively low frequency, a noise stemming from the 24MHz PLL reference clock may traverse the low-pass loop filter of ROPLL, which could potentially generate some HDMI flash artifacts. Reduce ROPLL loop bandwidth in an attempt to mitigate the problem. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Co-developed-by: Algea Cao Signed-off-by: Algea Cao Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 79db57ee90d1487b51f4ddadde870a275dd7b17b..d7d6c1ebacc890e257c1550210e= e144387ef7183 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -500,9 +500,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(0043), 0x00), REG_SEQ0(CMN_REG(0044), 0x46), REG_SEQ0(CMN_REG(0045), 0x24), - REG_SEQ0(CMN_REG(0046), 0xff), REG_SEQ0(CMN_REG(0047), 0x00), - REG_SEQ0(CMN_REG(0048), 0x44), REG_SEQ0(CMN_REG(0049), 0xfa), REG_SEQ0(CMN_REG(004a), 0x08), REG_SEQ0(CMN_REG(004b), 0x00), @@ -575,6 +573,8 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init= _seq[] =3D { REG_SEQ0(CMN_REG(0034), 0x00), REG_SEQ0(CMN_REG(003d), 0x40), REG_SEQ0(CMN_REG(0042), 0x78), + REG_SEQ0(CMN_REG(0046), 0xdd), + REG_SEQ0(CMN_REG(0048), 0x11), REG_SEQ0(CMN_REG(004e), 0x34), REG_SEQ0(CMN_REG(005c), 0x25), REG_SEQ0(CMN_REG(005e), 0x4f), --=20 2.50.0 From nobody Tue Oct 7 14:51:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14E08224B0D for ; Tue, 8 Jul 2025 19:37:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003438; cv=none; b=mM9hFUB+Bmh/hjVwur7h+p8f/YYP+JhBKNtOAXB1B2jCLO830UN6v7iJX6IP546v9fbOnzHm0oM25Wj2I6ymb/oPYBcHXYoXTR08IwXXb5jaB5WqtoMW9PaRxkuwWU88J/5RwhMzOCvDY1MfweF/J66h3P779X9aJuOcraeG1to= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003438; c=relaxed/simple; bh=QvHYoBZpVNwqNTbauHVKNfMaD6wc++kyq4PE4rdkCb0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W/KtDuvMS/oPMhiZhlxcFnoA9/T/7NepudwliV/p1TOexXJ7wKTub+ipnKgs2iQpAwJwr1RVj1ThSJxeTyXVtVSNruQVUkRrxO8jphTzWXjSssU+fvdnAP8hp2H1CS+xXiRp5PfZybYM6mAPeeeLglFw7DMQq8rc9SCw6lN0O78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=EcAxHAY/; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="EcAxHAY/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1752003435; bh=QvHYoBZpVNwqNTbauHVKNfMaD6wc++kyq4PE4rdkCb0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EcAxHAY/gAzDlJ8OuP0RnmQoB5gCPVnyZ+7wl39KWyUZVDs2xcgnjCjFmUHe6GA7q XaGXzr2YTK2N+/EDjVkWS9g5m2fsin13vkvBXUP57yt6bt6xafUVnIspojApW54Et5 A5UWVFKnXwoeEU6S658CjhDw/EzhEWBPQc+OBNTv+QVRYhyiplhjbqu4YWFaYjB8F7 iWehbKrNXieTVV9Z3s8bUjrHB657KchE+hhoxHe4Rp4q8PA1XIMv70z7XtpSyNnGAx 9owgGSAVDUDZTuhtuglCGJfPfI2tP97VHh86c4FW2L8U6PIBxjN6viOHaSEvwkBxFZ vgUYrsAilAb1A== Received: from localhost (unknown [212.93.144.165]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 2840517E0CF8; Tue, 8 Jul 2025 21:37:15 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:44 +0300 Subject: [PATCH 03/12] phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-3-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Fixup PHY deskew FIFO to prevent the phase of D2 lane going ahead of other lanes. It's worth noting this might only happen when dealing with HDMI 2.0 rates. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Co-developed-by: Algea Cao Signed-off-by: Algea Cao Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index d7d6c1ebacc890e257c1550210ee144387ef7183..2dd70f0cd8de34aad957d4d1463= 66e5521cd897e 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -668,13 +668,9 @@ static const struct reg_sequence rk_hdtpx_common_lane_= init_seq[] =3D { =20 static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0312), 0x00), - REG_SEQ0(LANE_REG(031e), 0x00), REG_SEQ0(LANE_REG(0412), 0x00), - REG_SEQ0(LANE_REG(041e), 0x00), REG_SEQ0(LANE_REG(0512), 0x00), - REG_SEQ0(LANE_REG(051e), 0x00), REG_SEQ0(LANE_REG(0612), 0x00), - REG_SEQ0(LANE_REG(061e), 0x08), REG_SEQ0(LANE_REG(0303), 0x2f), REG_SEQ0(LANE_REG(0403), 0x2f), REG_SEQ0(LANE_REG(0503), 0x2f), @@ -687,6 +683,11 @@ static const struct reg_sequence rk_hdtpx_tmds_lane_in= it_seq[] =3D { REG_SEQ0(LANE_REG(0406), 0x1c), REG_SEQ0(LANE_REG(0506), 0x1c), REG_SEQ0(LANE_REG(0606), 0x1c), + /* Keep Inter-Pair Skew in the limits */ + REG_SEQ0(LANE_REG(031e), 0x02), + REG_SEQ0(LANE_REG(041e), 0x02), + REG_SEQ0(LANE_REG(051e), 0x02), + REG_SEQ0(LANE_REG(061e), 0x0a), }; =20 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] =3D { --=20 2.50.0 From nobody Tue Oct 7 14:51:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4F39225793 for ; Tue, 8 Jul 2025 19:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003444; cv=none; b=PKLhF4cEUcWEIE597uQFnI6Pyyg1PBdsTtxTqDlnyUhYsR2Pr0kLVbHnB90mXskTeu1lr9O3ZTKxf8C3eaLQn7XWErkAZGz5Q3EYwT0jjIXLvRza67dcDCeuFKJMztXjF4AqzCuQqkxU5NfBymJxKzj4+vguBcmKg2gKvugVCTc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003444; c=relaxed/simple; bh=+erTwrLAUAZ2OsDl2bkXkrwnk4JpthhQCZF8qikCfo4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Tue, 8 Jul 2025 21:37:21 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:45 +0300 Subject: [PATCH 04/12] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-4-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 rk_hdptx_dp_reset() is allowed to sleep, hence replace the busy waiting with usleep_range(), to allow other threads to run. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 2dd70f0cd8de34aad957d4d146366e5521cd897e..6f12ac54abc1e1f0d67226899bb= 2c394e71a99cf 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1074,7 +1074,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hd= ptx) reset_control_assert(hdptx->rsts[RST_INIT].rstc); =20 reset_control_assert(hdptx->rsts[RST_APB].rstc); - udelay(10); + usleep_range(10, 15); reset_control_deassert(hdptx->rsts[RST_APB].rstc); =20 regmap_update_bits(hdptx->regmap, LANE_REG(0301), --=20 2.50.0 From nobody Tue Oct 7 14:51:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D16FE2288F9 for ; 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Tue, 8 Jul 2025 21:37:21 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:46 +0300 Subject: [PATCH 05/12] phy: rockchip: samsung-hdptx: Fix coding style alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-5-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Handle a bunch of reported checkpatch.pl complaints: CHECK: Alignment should match open parenthesis Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 6f12ac54abc1e1f0d67226899bb2c394e71a99cf..9d21a26bce460b7b4da0db9692f= 78a9fd1068abf 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1656,11 +1656,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdpt= x_phy *hdptx, regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, LN_TX_JEQ_EVEN_CTRL_RBR_MASK, FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK, - ctrl->tx_jeq_even_ctrl)); + ctrl->tx_jeq_even_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset, LN_TX_JEQ_ODD_CTRL_RBR_MASK, FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK, - ctrl->tx_jeq_odd_ctrl)); + ctrl->tx_jeq_odd_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, LN_TX_SER_40BIT_EN_RBR_MASK, FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1)); @@ -1670,11 +1670,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdpt= x_phy *hdptx, regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, LN_TX_JEQ_EVEN_CTRL_HBR_MASK, FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK, - ctrl->tx_jeq_even_ctrl)); + ctrl->tx_jeq_even_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, LN_TX_JEQ_ODD_CTRL_HBR_MASK, FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK, - ctrl->tx_jeq_odd_ctrl)); + ctrl->tx_jeq_odd_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, LN_TX_SER_40BIT_EN_HBR_MASK, FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1)); @@ -1685,11 +1685,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdpt= x_phy *hdptx, regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, - ctrl->tx_jeq_even_ctrl)); + ctrl->tx_jeq_even_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, LN_TX_JEQ_ODD_CTRL_HBR2_MASK, FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK, - ctrl->tx_jeq_odd_ctrl)); + ctrl->tx_jeq_odd_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, LN_TX_SER_40BIT_EN_HBR2_MASK, FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1)); --=20 2.50.0 From nobody Tue Oct 7 14:51:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7283622A4EA for ; Tue, 8 Jul 2025 19:37:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752003446; cv=none; b=F1dbkHyoNLrGIWkrmYJIxI7uB1xjuGNUFaeYwWandXZNNbCYiokMr3Ofaz4us1g5XnDRHosVPONnUFXkyv9+8rV4ZaqQXuln2x1gokXcXACkw45dJYoboPnzVf9Wb40UnSItMtrjSMETfe0ruORxKIoSKQMj1xt4/wwzePbK8+A= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-6-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Fix the naming inconsistencies for some of the functions and global variables: * Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable * Replace '_ropll_tmds_' with '_tmds_ropll_' globally * Replace 'hdtpx' with 'hdptx' globally Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 62 +++++++++++--------= ---- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 9d21a26bce460b7b4da0db9692f78a9fd1068abf..21b8ed427baf338300a0bce8130= 37a54121e9ed9 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -32,17 +32,17 @@ #define HDPTX_O_PHY_RDY BIT(1) #define HDPTX_O_SB_RDY BIT(0) =20 -#define HDTPX_REG(_n, _min, _max) \ +#define HDPTX_REG(_n, _min, _max) \ ( \ BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \ BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \ ((0x##_n) * 4) \ ) =20 -#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7) -#define SB_REG(n) HDTPX_REG(n, 0100, 0129) -#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229) -#define LANE_REG(n) HDTPX_REG(n, 0300, 062d) +#define CMN_REG(n) HDPTX_REG(n, 0000, 00a7) +#define SB_REG(n) HDPTX_REG(n, 0100, 0129) +#define LNTOP_REG(n) HDPTX_REG(n, 0200, 0229) +#define LANE_REG(n) HDPTX_REG(n, 0300, 062d) =20 /* CMN_REG(0008) */ #define OVRD_LCPLL_EN_MASK BIT(7) @@ -411,7 +411,7 @@ struct rk_hdptx_phy { unsigned int lanes; }; =20 -static const struct ropll_config ropll_tmds_cfg[] =3D { +static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] =3D { { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, @@ -456,7 +456,7 @@ static const struct ropll_config ropll_tmds_cfg[] =3D { 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, }; =20 -static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0009), 0x0c), REG_SEQ0(CMN_REG(000a), 0x83), REG_SEQ0(CMN_REG(000b), 0x06), @@ -546,7 +546,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(009b), 0x10), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0008), 0x00), REG_SEQ0(CMN_REG(0011), 0x01), REG_SEQ0(CMN_REG(0017), 0x20), @@ -588,14 +588,14 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(009b), 0x00), }; =20 -static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_sb_init_seq[] =3D { REG_SEQ0(SB_REG(0114), 0x00), REG_SEQ0(SB_REG(0115), 0x00), REG_SEQ0(SB_REG(0116), 0x00), REG_SEQ0(SB_REG(0117), 0x00), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0201), 0x00), REG_SEQ0(LNTOP_REG(0202), 0x00), REG_SEQ0(LNTOP_REG(0203), 0x0f), @@ -603,7 +603,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_hi= ghbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0205), 0xff), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lntop_lowbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0201), 0x07), REG_SEQ0(LNTOP_REG(0202), 0xc1), REG_SEQ0(LNTOP_REG(0203), 0xf0), @@ -611,7 +611,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lo= wbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0205), 0x1f), }; =20 -static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0303), 0x0c), REG_SEQ0(LANE_REG(0307), 0x20), REG_SEQ0(LANE_REG(030a), 0x17), @@ -666,7 +666,7 @@ static const struct reg_sequence rk_hdtpx_common_lane_i= nit_seq[] =3D { REG_SEQ0(LANE_REG(0620), 0xa0), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0312), 0x00), REG_SEQ0(LANE_REG(0412), 0x00), REG_SEQ0(LANE_REG(0512), 0x00), @@ -971,7 +971,7 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long lon= g rate, return true; } =20 -static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx) +static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; @@ -980,9 +980,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdp= tx_phy *hdptx) if (!hdptx->hdmi_cfg.tmds_char_rate) return 0; =20 - for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) { - cfg =3D &ropll_tmds_cfg[i]; + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) + if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rat= e) { + cfg =3D &rk_hdptx_tmds_ropll_cfg[i]; break; } =20 @@ -1002,8 +1002,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_h= dptx_phy *hdptx) =20 rk_hdptx_pre_power_up(hdptx); =20 - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq); =20 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); @@ -1044,25 +1044,25 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk= _hdptx_phy *hdptx) return ret; } =20 -static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx) +static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) { - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq); =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq); } else { /* For 1/10 bitrate clk */ - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_lowbr_seq); } =20 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); =20 - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq); =20 return rk_hdptx_post_enable_lane(hdptx); } @@ -1121,7 +1121,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_= phy *hdptx) if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { - ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx); + ret =3D rk_hdptx_tmds_ropll_cmn_config(hdptx); if (ret) goto dec_usage; } @@ -1468,7 +1468,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) regmap_write(hdptx->grf, GRF_HDPTX_CON0, HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); =20 - ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx); + ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); if (ret) rk_hdptx_phy_consumer_put(hdptx, true); } @@ -1491,11 +1491,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct r= k_hdptx_phy *hdptx, if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) return -EINVAL; =20 - for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (hdmi->tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) + if (hdmi->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) break; =20 - if (i =3D=3D ARRAY_SIZE(ropll_tmds_cfg) && + if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) return -EINVAL; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-7-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 In preparation to support FRL mode, move the PHY lane output enablement from the TMDS specific configuration to the common *_post_enable_lane() helper and make sure it gets turned off in *_phy_disable(). Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 21b8ed427baf338300a0bce813037a54121e9ed9..595aa94eb2dd22acd44c653e51d= 85ac497a1cc44 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -830,6 +830,8 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_ph= y *hdptx) HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); =20 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); + ret =3D regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, (val & HDPTX_O_PHY_RDY) && (val & HDPTX_O_PLL_LOCK_DONE), @@ -883,6 +885,7 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *h= dptx) usleep_range(20, 30); reset_control_deassert(hdptx->rsts[RST_APB].rstc); =20 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0); 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Tue, 8 Jul 2025 21:37:29 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:49 +0300 Subject: [PATCH 08/12] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-8-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Drop redundant reg_sequence entries from rk_hdptx_common_cmn_init_seq[], i.e. those that are either duplicated or overridden in rk_hdptx_tmds_cmn_init_seq[]. Additionally, a few items do not really belong to the former, hence move them to the latter. That's mostly a preparatory step for adding FRL support. No functional changes intended at this point. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 22 ++++---------------= --- 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 595aa94eb2dd22acd44c653e51d85ac497a1cc44..71b076de7b75f2ba08eae679ded= 77caa2ba86590 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -465,13 +465,11 @@ static const struct reg_sequence rk_hdptx_common_cmn_= init_seq[] =3D { REG_SEQ0(CMN_REG(000e), 0x0f), REG_SEQ0(CMN_REG(000f), 0x0f), REG_SEQ0(CMN_REG(0010), 0x04), - REG_SEQ0(CMN_REG(0011), 0x00), REG_SEQ0(CMN_REG(0012), 0x26), REG_SEQ0(CMN_REG(0013), 0x22), REG_SEQ0(CMN_REG(0014), 0x24), REG_SEQ0(CMN_REG(0015), 0x77), REG_SEQ0(CMN_REG(0016), 0x08), - REG_SEQ0(CMN_REG(0017), 0x00), REG_SEQ0(CMN_REG(0018), 0x04), REG_SEQ0(CMN_REG(0019), 0x48), REG_SEQ0(CMN_REG(001a), 0x01), @@ -479,13 +477,7 @@ static const struct reg_sequence rk_hdptx_common_cmn_i= nit_seq[] =3D { REG_SEQ0(CMN_REG(001c), 0x01), REG_SEQ0(CMN_REG(001d), 0x64), REG_SEQ0(CMN_REG(001f), 0x00), - REG_SEQ0(CMN_REG(0026), 0x53), REG_SEQ0(CMN_REG(0029), 0x01), - REG_SEQ0(CMN_REG(0030), 0x00), - REG_SEQ0(CMN_REG(0031), 0x20), - REG_SEQ0(CMN_REG(0032), 0x30), - REG_SEQ0(CMN_REG(0033), 0x0b), - REG_SEQ0(CMN_REG(0034), 0x23), REG_SEQ0(CMN_REG(0035), 0x00), REG_SEQ0(CMN_REG(0038), 0x00), REG_SEQ0(CMN_REG(0039), 0x00), @@ -496,7 +488,6 @@ static const struct reg_sequence rk_hdptx_common_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(003f), 0x83), REG_SEQ0(CMN_REG(0040), 0x06), REG_SEQ0(CMN_REG(0041), 0x20), - REG_SEQ0(CMN_REG(0042), 0xb8), REG_SEQ0(CMN_REG(0043), 0x00), REG_SEQ0(CMN_REG(0044), 0x46), REG_SEQ0(CMN_REG(0045), 0x24), @@ -506,14 +497,9 @@ static const struct reg_sequence rk_hdptx_common_cmn_i= nit_seq[] =3D { REG_SEQ0(CMN_REG(004b), 0x00), REG_SEQ0(CMN_REG(004c), 0x01), REG_SEQ0(CMN_REG(004d), 0x64), - REG_SEQ0(CMN_REG(004e), 0x14), REG_SEQ0(CMN_REG(004f), 0x00), REG_SEQ0(CMN_REG(0050), 0x00), - REG_SEQ0(CMN_REG(005d), 0x0c), REG_SEQ0(CMN_REG(005f), 0x01), - REG_SEQ0(CMN_REG(006b), 0x04), - REG_SEQ0(CMN_REG(0073), 0x30), - REG_SEQ0(CMN_REG(0074), 0x00), REG_SEQ0(CMN_REG(0075), 0x20), REG_SEQ0(CMN_REG(0076), 0x30), REG_SEQ0(CMN_REG(0077), 0x08), @@ -525,13 +511,10 @@ static const struct reg_sequence rk_hdptx_common_cmn_= init_seq[] =3D { REG_SEQ0(CMN_REG(007e), 0x00), REG_SEQ0(CMN_REG(007f), 0x00), REG_SEQ0(CMN_REG(0080), 0x00), - REG_SEQ0(CMN_REG(0081), 0x09), REG_SEQ0(CMN_REG(0082), 0x04), REG_SEQ0(CMN_REG(0083), 0x24), REG_SEQ0(CMN_REG(0084), 0x20), REG_SEQ0(CMN_REG(0085), 0x03), - REG_SEQ0(CMN_REG(0086), 0x01), - REG_SEQ0(CMN_REG(0087), 0x0c), REG_SEQ0(CMN_REG(008a), 0x55), REG_SEQ0(CMN_REG(008b), 0x25), REG_SEQ0(CMN_REG(008c), 0x2c), @@ -543,7 +526,6 @@ static const struct reg_sequence rk_hdptx_common_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(0092), 0x00), REG_SEQ0(CMN_REG(0093), 0x00), REG_SEQ0(CMN_REG(009a), 0x11), - REG_SEQ0(CMN_REG(009b), 0x10), }; =20 static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] =3D { @@ -577,9 +559,13 @@ static const struct reg_sequence rk_hdptx_tmds_cmn_ini= t_seq[] =3D { REG_SEQ0(CMN_REG(0048), 0x11), REG_SEQ0(CMN_REG(004e), 0x34), REG_SEQ0(CMN_REG(005c), 0x25), + REG_SEQ0(CMN_REG(005d), 0x0c), REG_SEQ0(CMN_REG(005e), 0x4f), + REG_SEQ0(CMN_REG(006b), 0x04), + REG_SEQ0(CMN_REG(0073), 0x30), REG_SEQ0(CMN_REG(0074), 0x04), REG_SEQ0(CMN_REG(0081), 0x01), + REG_SEQ0(CMN_REG(0086), 0x01), REG_SEQ0(CMN_REG(0087), 0x04), REG_SEQ0(CMN_REG(0089), 0x00), REG_SEQ0(CMN_REG(0095), 0x00), --=20 2.50.0 From nobody Tue Oct 7 14:51:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E293D22F77E for ; Tue, 8 Jul 2025 19:37:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Tue, 8 Jul 2025 21:37:35 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:50 +0300 Subject: [PATCH 09/12] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-9-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Improve ->recalc_rate() callback of hdptx_phy_clk_ops to calculate the initial clock rate based on the actual PHY PLL configuration as retrieved from the related HW registers. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 90 +++++++++++++++++++= +++- 1 file changed, 89 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 71b076de7b75f2ba08eae679ded77caa2ba86590..e86bbc270a4ca448f55ca58b4b5= b52d378730d74 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1850,12 +1850,100 @@ static void rk_hdptx_phy_clk_unprepare(struct clk_= hw *hw) rk_hdptx_phy_consumer_put(hdptx, true); } =20 +#define PLL_REF_CLK 24000000ULL + +static unsigned long rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdp= tx_phy *hdptx) +{ + struct ropll_config ropll_hw; + u64 fout, sdm; + u32 mode, val; + int ret; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0008), &mode); + if (ret) + return 0; + + if (mode & LCPLL_LCVCO_MODE_EN_MASK) + return 0; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0051), &val); + if (ret) + return 0; + ropll_hw.pms_mdiv =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(005E), &val); + if (ret) + return 0; + ropll_hw.sdm_en =3D val & ROPLL_SDM_EN_MASK; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0064), &val); + if (ret) + return 0; + ropll_hw.sdm_num_sign =3D val & ROPLL_SDM_NUM_SIGN_RBR_MASK; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0065), &val); + if (ret) + return 0; + ropll_hw.sdm_num =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0060), &val); + if (ret) + return 0; + ropll_hw.sdm_deno =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0069), &val); + if (ret) + return 0; + ropll_hw.sdc_n =3D (val & ROPLL_SDC_N_RBR_MASK) + 3; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(006c), &val); + if (ret) + return 0; + ropll_hw.sdc_num =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0070), &val); + if (ret) + return 0; + ropll_hw.sdc_deno =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0086), &val); + if (ret) + return 0; + ropll_hw.pms_sdiv =3D ((val & PLL_PCG_POSTDIV_SEL_MASK) >> 4) + 1; + + fout =3D PLL_REF_CLK * ropll_hw.pms_mdiv; + if (ropll_hw.sdm_en) { + sdm =3D div_u64(PLL_REF_CLK * ropll_hw.sdc_deno * + ropll_hw.pms_mdiv * ropll_hw.sdm_num, + 16 * ropll_hw.sdm_deno * + (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num)); + + if (ropll_hw.sdm_num_sign) + fout =3D fout - sdm; + else + fout =3D fout + sdm; + } + + fout =3D div_u64(fout * 2, ropll_hw.pms_sdiv * 10); + + return fout; +} + static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + u32 status; + int ret; + + if (hdptx->hw_rate) + return hdptx->hw_rate; + + ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status); + if (ret || !(status & HDPTX_I_PLL_EN)) + return 0; =20 - return hdptx->hw_rate; + return rk_hdptx_phy_clk_calc_rate_from_pll_cfg(hdptx); } =20 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, --=20 2.50.0 From nobody Tue Oct 7 14:51:16 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A567223DCE for ; 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Tue, 8 Jul 2025 21:37:36 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:51 +0300 Subject: [PATCH 10/12] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-10-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 In preparation to support the FRL operation mode which gets configured via the lanes and rate per lane tuple, switch to a driver specific struct for configuring the link rate and bpc. This simplifies and optimizes the implementation by allowing implicit switches between TMDS and FRL rates, without requiring additional checks of the active PHY mode followed by recalculations of the link rate when operating in FRL mode. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 46 +++++++++++++------= ---- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index e86bbc270a4ca448f55ca58b4b5b52d378730d74..325d2596395123b88e4720cb503= bee4436292e85 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -387,6 +387,11 @@ struct rk_hdptx_phy_cfg { unsigned int phy_ids[MAX_HDPTX_PHY_NUM]; }; =20 +struct rk_hdptx_hdmi_cfg { + unsigned long long rate; + unsigned int bpc; +}; + struct rk_hdptx_phy { struct device *dev; struct regmap *regmap; @@ -394,7 +399,7 @@ struct rk_hdptx_phy { =20 int phy_id; struct phy *phy; - struct phy_configure_opts_hdmi hdmi_cfg; + struct rk_hdptx_hdmi_cfg hdmi_cfg; struct clk_bulk_data *clks; int nr_clks; struct reset_control_bulk_data rsts[RST_MAX]; @@ -966,19 +971,19 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_h= dptx_phy *hdptx) struct ropll_config rc =3D {0}; int ret, i; =20 - if (!hdptx->hdmi_cfg.tmds_char_rate) + if (!hdptx->hdmi_cfg.rate) return 0; =20 for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) - if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rat= e) { + if (hdptx->hdmi_cfg.rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) { cfg =3D &rk_hdptx_tmds_ropll_cfg[i]; break; } =20 if (!cfg) { - if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) { + if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.rate, &rc)) { dev_err(hdptx->dev, "%s cannot find pll cfg for rate=3D%llu\n", - __func__, hdptx->hdmi_cfg.tmds_char_rate); + __func__, hdptx->hdmi_cfg.rate); return -EINVAL; } =20 @@ -986,7 +991,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdp= tx_phy *hdptx) } =20 dev_dbg(hdptx->dev, "%s rate=3D%llu mdiv=3D%u sdiv=3D%u sdm_en=3D%u k_sig= n=3D%u k=3D%u lc=3D%u\n", - __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv += 1, + __func__, hdptx->hdmi_cfg.rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); =20 rk_hdptx_pre_power_up(hdptx); @@ -1028,7 +1033,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_h= dptx_phy *hdptx) =20 ret =3D rk_hdptx_post_enable_pll(hdptx); if (!ret) - hdptx->hw_rate =3D hdptx->hdmi_cfg.tmds_char_rate; + hdptx->hw_rate =3D hdptx->hdmi_cfg.rate; =20 return ret; } @@ -1039,7 +1044,7 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_= hdptx_phy *hdptx) =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 - if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { + if (hdptx->hdmi_cfg.rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq); } else { @@ -1410,19 +1415,19 @@ static int rk_hdptx_phy_power_on(struct phy *phy) int ret, lane; =20 if (mode !=3D PHY_MODE_DP) { - if (!hdptx->hdmi_cfg.tmds_char_rate) { + if (!hdptx->hdmi_cfg.rate) { /* * FIXME: Temporary workaround to setup TMDS char rate * from the RK DW HDMI QP bridge driver. * Will be removed as soon the switch to the HDMI PHY * configuration API has been completed on both ends. */ - hdptx->hdmi_cfg.tmds_char_rate =3D phy_get_bus_width(hdptx->phy) & 0xff= fffff; - hdptx->hdmi_cfg.tmds_char_rate *=3D 100; + hdptx->hdmi_cfg.rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; + hdptx->hdmi_cfg.rate *=3D 100; } =20 dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); } =20 ret =3D rk_hdptx_phy_consumer_get(hdptx); @@ -1769,12 +1774,13 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { - hdptx->hdmi_cfg =3D opts->hdmi; + hdptx->hdmi_cfg.rate =3D opts->hdmi.tmds_char_rate; + hdptx->hdmi_cfg.bpc =3D opts->hdmi.bpc; hdptx->restrict_rate_change =3D true; } =20 dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); return ret; } =20 @@ -1956,7 +1962,7 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw= *hw, unsigned long rate, * To be dropped as soon as the RK DW HDMI QP bridge driver * switches to make use of phy_configure(). */ - if (!hdptx->restrict_rate_change && rate !=3D hdptx->hdmi_cfg.tmds_char_r= ate) { + if (!hdptx->restrict_rate_change && rate !=3D hdptx->hdmi_cfg.rate) { struct phy_configure_opts_hdmi hdmi =3D { .tmds_char_rate =3D rate, }; @@ -1965,7 +1971,7 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw= *hw, unsigned long rate, if (ret) return ret; =20 - hdptx->hdmi_cfg =3D hdmi; + hdptx->hdmi_cfg.rate =3D rate; } =20 /* @@ -1973,7 +1979,7 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw= *hw, unsigned long rate, * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with * a different rate argument. */ - return hdptx->hdmi_cfg.tmds_char_rate; + return hdptx->hdmi_cfg.rate; } =20 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, @@ -1982,10 +1988,10 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw = *hw, unsigned long rate, struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 /* Revert any unlikely TMDS char rate change since round_rate() */ - if (hdptx->hdmi_cfg.tmds_char_rate !=3D rate) { + if (hdptx->hdmi_cfg.rate !=3D rate) { dev_warn(hdptx->dev, "Reverting unexpected rate change from %lu to %llu\= n", - rate, hdptx->hdmi_cfg.tmds_char_rate); - hdptx->hdmi_cfg.tmds_char_rate =3D rate; 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Tue, 8 Jul 2025 21:37:36 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 08 Jul 2025 22:35:52 +0300 Subject: [PATCH 11/12] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-11-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 In order to facilitate introduction of HDMI 2.1 FRL support and to avoid recomputing the link rate after verifying the HDMI configuration given as input, extend rk_hdptx_phy_verify_hdmi_config() by providing an optional output parameter to store the validated configuration. For improved code readability, also rename the existing hdmi input parameter. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 35 ++++++++++++-------= ---- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 325d2596395123b88e4720cb503bee4436292e85..daccaf134c0ee36972f8f7c0eeb= f3dac86faeff1 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1477,25 +1477,24 @@ static int rk_hdptx_phy_power_off(struct phy *phy) } =20 static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, - struct phy_configure_opts_hdmi *hdmi) + struct phy_configure_opts_hdmi *hdmi_in, + struct rk_hdptx_hdmi_cfg *hdmi_out) { int i; =20 - if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) + if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RATE) return -EINVAL; =20 for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) - if (hdmi->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) + if (hdmi_in->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) break; =20 if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && - !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) + !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL)) return -EINVAL; =20 - if (!hdmi->bpc) - hdmi->bpc =3D 8; - - switch (hdmi->bpc) { + switch (hdmi_in->bpc) { + case 0: case 8: case 10: case 12: @@ -1505,6 +1504,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, return -EINVAL; } =20 + if (hdmi_out) { + hdmi_out->rate =3D hdmi_in->tmds_char_rate; + hdmi_out->bpc =3D hdmi_in->bpc ?: 8; + } + return 0; } =20 @@ -1770,17 +1774,15 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt int ret; =20 if (mode !=3D PHY_MODE_DP) { - ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); + ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi, &hdptx->hdmi= _cfg); if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { - hdptx->hdmi_cfg.rate =3D opts->hdmi.tmds_char_rate; - hdptx->hdmi_cfg.bpc =3D opts->hdmi.bpc; hdptx->restrict_rate_change =3D true; + dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); } =20 - dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); return ret; } =20 @@ -1824,7 +1826,7 @@ static int rk_hdptx_phy_validate(struct phy *phy, enu= m phy_mode mode, struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); =20 if (mode !=3D PHY_MODE_DP) - return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); + return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi, NULL); =20 return rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); } @@ -1966,12 +1968,11 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_= hw *hw, unsigned long rate, struct phy_configure_opts_hdmi hdmi =3D { .tmds_char_rate =3D rate, }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250708-phy-hdptx-frl-v1-12-cfe096e224f4@collabora.com> References: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> In-Reply-To: <20250708-phy-hdptx-frl-v1-0-cfe096e224f4@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The PHY is capable of handling four HDMI 2.1 Fixed Rate Link (FRL) lanes, and each one can operate at any of the rates of 3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps. Co-developed-by: Algea Cao Signed-off-by: Algea Cao Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 410 ++++++++++++++++++= +++- 1 file changed, 393 insertions(+), 17 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index daccaf134c0ee36972f8f7c0eebf3dac86faeff1..0e75bac7358960dd8bb5203df44= 5b5ea5284079f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -22,6 +22,7 @@ #include =20 #define GRF_HDPTX_CON0 0x00 +#define LC_REF_CLK_SEL BIT(11) #define HDPTX_I_PLL_EN BIT(7) #define HDPTX_I_BIAS_EN BIT(6) #define HDPTX_I_BGR_EN BIT(5) @@ -322,6 +323,9 @@ =20 #define HDMI14_MAX_RATE 340000000 #define HDMI20_MAX_RATE 600000000 +#define FRL_8G4L_RATE 3200000000 +#define FRL_6G3L_RATE 1800000000 +#define FRL_3G3L_RATE 900000000 =20 enum dp_link_rate { DP_BW_RBR, @@ -329,6 +333,37 @@ enum dp_link_rate { DP_BW_HBR2, }; =20 +struct lcpll_config { + unsigned long long rate; + u8 lcvco_mode_en; + u8 pi_en; + u8 clk_en_100m; + u8 pms_mdiv; + u8 pms_mdiv_afc; + u8 pms_pdiv; + u8 pms_refdiv; + u8 pms_sdiv; + u8 pi_cdiv_rstn; + u8 pi_cdiv_sel; + u8 sdm_en; + u8 sdm_rstn; + u8 sdc_frac_en; + u8 sdc_rstn; + u8 sdm_deno; + u8 sdm_num_sign; + u8 sdm_num; + u8 sdc_n; + u8 sdc_n2; + u8 sdc_num; + u8 sdc_deno; + u8 sdc_ndiv_rstn; + u8 ssc_en; + u8 ssc_fm_dev; + u8 ssc_fm_freq; + u8 ssc_clk_div_sel; + u8 cd_tx_ser_rate_sel; +}; + struct ropll_config { unsigned long long rate; u8 pms_mdiv; @@ -416,6 +451,19 @@ struct rk_hdptx_phy { unsigned int lanes; }; =20 +static const struct lcpll_config rk_hdptx_frl_lcpll_cfg[] =3D { + { 4800000000ULL, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0,= 2, + 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, + { 4000000000ULL, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1,= 1, + 0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0, }, + { 2400000000ULL, 1, 0, 0, 0x7d, 0x7d, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0,= 2, + 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, + { 1800000000ULL, 1, 0, 0, 0x7d, 0x7d, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0,= 2, + 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, + { 900000000ULL, 1, 0, 0, 0x7d, 0x7d, 1, 1, 3, 0, 0, 0, 0, 1, 1, 1, 0, 0, = 2, + 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, +}; + static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] =3D { { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, @@ -533,6 +581,110 @@ static const struct reg_sequence rk_hdptx_common_cmn_= init_seq[] =3D { REG_SEQ0(CMN_REG(009a), 0x11), }; =20 +static const struct reg_sequence rk_hdptx_frl_lcpll_cmn_init_seq[] =3D { + REG_SEQ0(CMN_REG(0011), 0x00), + REG_SEQ0(CMN_REG(0017), 0x00), + REG_SEQ0(CMN_REG(0025), 0x10), + REG_SEQ0(CMN_REG(0026), 0x53), + REG_SEQ0(CMN_REG(0027), 0x01), + REG_SEQ0(CMN_REG(0028), 0x0d), + REG_SEQ0(CMN_REG(002e), 0x02), + REG_SEQ0(CMN_REG(002f), 0x0d), + REG_SEQ0(CMN_REG(0030), 0x00), + REG_SEQ0(CMN_REG(0031), 0x20), + REG_SEQ0(CMN_REG(0032), 0x30), + REG_SEQ0(CMN_REG(0033), 0x0b), + REG_SEQ0(CMN_REG(0034), 0x23), + REG_SEQ0(CMN_REG(003d), 0x00), + REG_SEQ0(CMN_REG(0042), 0xb8), + REG_SEQ0(CMN_REG(0046), 0xff), + REG_SEQ0(CMN_REG(0048), 0x44), + REG_SEQ0(CMN_REG(004e), 0x14), + REG_SEQ0(CMN_REG(0051), 0x00), + REG_SEQ0(CMN_REG(0055), 0x00), + REG_SEQ0(CMN_REG(0059), 0x11), + REG_SEQ0(CMN_REG(005a), 0x03), + REG_SEQ0(CMN_REG(005c), 0x05), + REG_SEQ0(CMN_REG(005d), 0x0c), + REG_SEQ0(CMN_REG(005e), 0x07), + REG_SEQ0(CMN_REG(0060), 0x01), + REG_SEQ0(CMN_REG(0064), 0x07), + REG_SEQ0(CMN_REG(0065), 0x00), + REG_SEQ0(CMN_REG(0069), 0x00), + REG_SEQ0(CMN_REG(006b), 0x04), + REG_SEQ0(CMN_REG(006c), 0x00), + REG_SEQ0(CMN_REG(0070), 0x01), + REG_SEQ0(CMN_REG(0073), 0x30), + REG_SEQ0(CMN_REG(0074), 0x00), + REG_SEQ0(CMN_REG(0081), 0x09), + REG_SEQ0(CMN_REG(0086), 0x01), + REG_SEQ0(CMN_REG(0087), 0x0c), + REG_SEQ0(CMN_REG(0089), 0x02), + REG_SEQ0(CMN_REG(0095), 0x00), + REG_SEQ0(CMN_REG(0097), 0x00), + REG_SEQ0(CMN_REG(0099), 0x00), + REG_SEQ0(CMN_REG(009b), 0x10), +}; + +static const struct reg_sequence rk_hdptx_frl_lcpll_ropll_cmn_init_seq[] = =3D { + REG_SEQ0(CMN_REG(0008), 0xd0), + REG_SEQ0(CMN_REG(0011), 0x00), + REG_SEQ0(CMN_REG(0017), 0x00), + REG_SEQ0(CMN_REG(001e), 0x35), + REG_SEQ0(CMN_REG(0020), 0x6b), + REG_SEQ0(CMN_REG(0021), 0x6b), + REG_SEQ0(CMN_REG(0022), 0x11), + REG_SEQ0(CMN_REG(0024), 0x00), + REG_SEQ0(CMN_REG(0025), 0x10), + REG_SEQ0(CMN_REG(0026), 0x53), + REG_SEQ0(CMN_REG(0027), 0x15), + REG_SEQ0(CMN_REG(0028), 0x0d), + REG_SEQ0(CMN_REG(002a), 0x09), + REG_SEQ0(CMN_REG(002b), 0x01), + REG_SEQ0(CMN_REG(002c), 0x02), + REG_SEQ0(CMN_REG(002d), 0x02), + REG_SEQ0(CMN_REG(002e), 0x0d), + REG_SEQ0(CMN_REG(002f), 0x61), + REG_SEQ0(CMN_REG(0030), 0x00), + REG_SEQ0(CMN_REG(0031), 0x20), + REG_SEQ0(CMN_REG(0032), 0x30), + REG_SEQ0(CMN_REG(0033), 0x0b), + REG_SEQ0(CMN_REG(0034), 0x23), + REG_SEQ0(CMN_REG(0037), 0x00), + REG_SEQ0(CMN_REG(003d), 0xc0), + REG_SEQ0(CMN_REG(0042), 0xb8), + REG_SEQ0(CMN_REG(0046), 0xff), + REG_SEQ0(CMN_REG(0048), 0x44), + REG_SEQ0(CMN_REG(004e), 0x14), + REG_SEQ0(CMN_REG(0054), 0x19), + REG_SEQ0(CMN_REG(0058), 0x19), + REG_SEQ0(CMN_REG(0059), 0x11), + REG_SEQ0(CMN_REG(005b), 0x30), + REG_SEQ0(CMN_REG(005c), 0x25), + REG_SEQ0(CMN_REG(005d), 0x14), + REG_SEQ0(CMN_REG(005e), 0x0e), + REG_SEQ0(CMN_REG(0063), 0x01), + REG_SEQ0(CMN_REG(0064), 0x0e), + REG_SEQ0(CMN_REG(0068), 0x00), + REG_SEQ0(CMN_REG(0069), 0x02), + REG_SEQ0(CMN_REG(006b), 0x00), + REG_SEQ0(CMN_REG(006f), 0x00), + REG_SEQ0(CMN_REG(0073), 0x02), + REG_SEQ0(CMN_REG(0074), 0x00), + REG_SEQ0(CMN_REG(007a), 0x00), + REG_SEQ0(CMN_REG(0081), 0x09), + REG_SEQ0(CMN_REG(0086), 0x11), + REG_SEQ0(CMN_REG(0087), 0x0c), + REG_SEQ0(CMN_REG(0089), 0x00), + REG_SEQ0(CMN_REG(0095), 0x03), + REG_SEQ0(CMN_REG(0097), 0x00), + REG_SEQ0(CMN_REG(0099), 0x00), + REG_SEQ0(CMN_REG(009b), 0x10), + REG_SEQ0(CMN_REG(009e), 0x03), + REG_SEQ0(CMN_REG(009f), 0xff), + REG_SEQ0(CMN_REG(00a0), 0x60), +}; + static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0008), 0x00), REG_SEQ0(CMN_REG(0011), 0x01), @@ -586,6 +738,16 @@ static const struct reg_sequence rk_hdptx_common_sb_in= it_seq[] =3D { REG_SEQ0(SB_REG(0117), 0x00), }; =20 +static const struct reg_sequence rk_hdptx_frl_lntop_init_seq[] =3D { + REG_SEQ0(LNTOP_REG(0200), 0x04), + REG_SEQ0(LNTOP_REG(0201), 0x00), + REG_SEQ0(LNTOP_REG(0202), 0x00), + REG_SEQ0(LNTOP_REG(0203), 0xf0), + REG_SEQ0(LNTOP_REG(0204), 0xff), + REG_SEQ0(LNTOP_REG(0205), 0xff), + REG_SEQ0(LNTOP_REG(0206), 0x05), +}; + static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0201), 0x00), REG_SEQ0(LNTOP_REG(0202), 0x00), @@ -657,6 +819,38 @@ static const struct reg_sequence rk_hdptx_common_lane_= init_seq[] =3D { REG_SEQ0(LANE_REG(0620), 0xa0), }; =20 +static const struct reg_sequence rk_hdptx_frl_lane_init_seq[] =3D { + REG_SEQ0(LANE_REG(0312), 0x3c), + REG_SEQ0(LANE_REG(0412), 0x3c), + REG_SEQ0(LANE_REG(0512), 0x3c), + REG_SEQ0(LANE_REG(0612), 0x3c), + REG_SEQ0(LANE_REG(0303), 0x2f), + REG_SEQ0(LANE_REG(0403), 0x2f), + REG_SEQ0(LANE_REG(0503), 0x2f), + REG_SEQ0(LANE_REG(0603), 0x2f), + REG_SEQ0(LANE_REG(0305), 0x03), + REG_SEQ0(LANE_REG(0405), 0x03), + REG_SEQ0(LANE_REG(0505), 0x03), + REG_SEQ0(LANE_REG(0605), 0x03), + REG_SEQ0(LANE_REG(0306), 0xfc), + REG_SEQ0(LANE_REG(0406), 0xfc), + REG_SEQ0(LANE_REG(0506), 0xfc), + REG_SEQ0(LANE_REG(0606), 0xfc), + REG_SEQ0(LANE_REG(0305), 0x4f), + REG_SEQ0(LANE_REG(0405), 0x4f), + REG_SEQ0(LANE_REG(0505), 0x4f), + REG_SEQ0(LANE_REG(0605), 0x4f), + REG_SEQ0(LANE_REG(0304), 0x14), + REG_SEQ0(LANE_REG(0404), 0x14), + REG_SEQ0(LANE_REG(0504), 0x14), + REG_SEQ0(LANE_REG(0604), 0x14), + /* Keep Inter-Pair Skew in the limits */ + REG_SEQ0(LANE_REG(031e), 0x02), + REG_SEQ0(LANE_REG(041e), 0x02), + REG_SEQ0(LANE_REG(051e), 0x02), + REG_SEQ0(LANE_REG(061e), 0x02), +}; + static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0312), 0x00), REG_SEQ0(LANE_REG(0412), 0x00), @@ -821,7 +1015,12 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_= phy *hdptx) HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); =20 - regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); + /* 3 lanes FRL mode */ + if (hdptx->hdmi_cfg.rate =3D=3D FRL_6G3L_RATE || + hdptx->hdmi_cfg.rate =3D=3D FRL_3G3L_RATE) + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x07); + else + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); =20 ret =3D regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, (val & HDPTX_O_PHY_RDY) && @@ -965,6 +1164,80 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long l= ong rate, return true; } =20 +static int rk_hdptx_frl_lcpll_cmn_config(struct rk_hdptx_phy *hdptx) +{ + const struct lcpll_config *cfg =3D NULL; + int i; + + dev_dbg(hdptx->dev, "%s rate=3D%llu\n", __func__, hdptx->hdmi_cfg.rate); + + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { + if (hdptx->hdmi_cfg.rate =3D=3D rk_hdptx_frl_lcpll_cfg[i].rate) { + cfg =3D &rk_hdptx_frl_lcpll_cfg[i]; + break; + } + } + + if (!cfg) { + dev_err(hdptx->dev, "%s cannot find pll cfg for rate=3D%llu\n", + __func__, hdptx->hdmi_cfg.rate); + return -EINVAL; + } + + rk_hdptx_pre_power_up(hdptx); + + regmap_write(hdptx->grf, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16); + + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lcpll_cmn_init_seq); + + regmap_update_bits(hdptx->regmap, CMN_REG(0008), + LCPLL_EN_MASK | LCPLL_LCVCO_MODE_EN_MASK, + FIELD_PREP(LCPLL_EN_MASK, 1) | + FIELD_PREP(LCPLL_LCVCO_MODE_EN_MASK, cfg->lcvco_mode_en)); + + regmap_update_bits(hdptx->regmap, CMN_REG(001e), + LCPLL_PI_EN_MASK | LCPLL_100M_CLK_EN_MASK, + FIELD_PREP(LCPLL_PI_EN_MASK, cfg->pi_en) | + FIELD_PREP(LCPLL_100M_CLK_EN_MASK, cfg->clk_en_100m)); + + regmap_write(hdptx->regmap, CMN_REG(0020), cfg->pms_mdiv); + regmap_write(hdptx->regmap, CMN_REG(0021), cfg->pms_mdiv_afc); + regmap_write(hdptx->regmap, CMN_REG(0022), + (cfg->pms_pdiv << 4) | cfg->pms_refdiv); + regmap_write(hdptx->regmap, CMN_REG(0023), + (cfg->pms_sdiv << 4) | cfg->pms_sdiv); + regmap_write(hdptx->regmap, CMN_REG(002a), cfg->sdm_deno); + regmap_write(hdptx->regmap, CMN_REG(002b), cfg->sdm_num_sign); + regmap_write(hdptx->regmap, CMN_REG(002c), cfg->sdm_num); + + regmap_update_bits(hdptx->regmap, CMN_REG(002d), LCPLL_SDC_N_MASK, + FIELD_PREP(LCPLL_SDC_N_MASK, cfg->sdc_n)); + + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, + FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, + FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1)); + + return rk_hdptx_post_enable_pll(hdptx); +} + +static int rk_hdptx_frl_lcpll_ropll_cmn_config(struct rk_hdptx_phy *hdptx) +{ + dev_dbg(hdptx->dev, "%s rate=3D%llu\n", __func__, hdptx->hdmi_cfg.rate); + + rk_hdptx_pre_power_up(hdptx); + + /* ROPLL input reference clock from LCPLL (cascade mode) */ + regmap_write(hdptx->grf, GRF_HDPTX_CON0, + (LC_REF_CLK_SEL << 16) | LC_REF_CLK_SEL); + + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lcpll_ropll_cmn_init_seq); + + return rk_hdptx_post_enable_pll(hdptx); +} + static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; @@ -996,6 +1269,8 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hd= ptx_phy *hdptx) =20 rk_hdptx_pre_power_up(hdptx); =20 + regmap_write(hdptx->grf, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq); =20 @@ -1038,6 +1313,28 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_= hdptx_phy *hdptx) return ret; } =20 +static int rk_hdptx_pll_cmn_config(struct rk_hdptx_phy *hdptx) +{ + if (hdptx->hdmi_cfg.rate <=3D HDMI20_MAX_RATE) + return rk_hdptx_tmds_ropll_cmn_config(hdptx); + + if (hdptx->hdmi_cfg.rate =3D=3D FRL_8G4L_RATE) + return rk_hdptx_frl_lcpll_ropll_cmn_config(hdptx); + + return rk_hdptx_frl_lcpll_cmn_config(hdptx); +} + +static int rk_hdptx_frl_lcpll_mode_config(struct rk_hdptx_phy *hdptx) +{ + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lntop_init_seq); + + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lane_init_seq); + + return rk_hdptx_post_enable_lane(hdptx); +} + static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) { rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq); @@ -1114,7 +1411,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_= phy *hdptx) if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { - ret =3D rk_hdptx_tmds_ropll_cmn_config(hdptx); + ret =3D rk_hdptx_pll_cmn_config(hdptx); if (ret) goto dec_usage; } @@ -1414,7 +1711,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) enum phy_mode mode =3D phy_get_mode(phy); int ret, lane; =20 - if (mode !=3D PHY_MODE_DP) { + if (mode !=3D PHY_MODE_DP && mode !=3D PHY_MODE_HDMI_FRL) { if (!hdptx->hdmi_cfg.rate) { /* * FIXME: Temporary workaround to setup TMDS char rate @@ -1461,7 +1758,11 @@ static int rk_hdptx_phy_power_on(struct phy *phy) regmap_write(hdptx->grf, GRF_HDPTX_CON0, HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); =20 - ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); + if (mode =3D=3D PHY_MODE_HDMI_FRL) + ret =3D rk_hdptx_frl_lcpll_mode_config(hdptx); + else + ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); + if (ret) rk_hdptx_phy_consumer_put(hdptx, true); } @@ -1482,16 +1783,49 @@ static int rk_hdptx_phy_verify_hdmi_config(struct r= k_hdptx_phy *hdptx, { int i; =20 - if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RATE) - return -EINVAL; + if (phy_get_mode(hdptx->phy) =3D=3D PHY_MODE_HDMI_FRL) { + unsigned long long frl_rate =3D 100000000ULL * hdmi_in->frl.lanes * + hdmi_in->frl.rate_per_lane; =20 - for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) - if (hdmi_in->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) + switch (hdmi_in->frl.rate_per_lane) { + case 3: + case 6: + case 8: + case 10: + case 12: break; + default: + return -EINVAL; + } =20 - if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && - !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL)) - return -EINVAL; + if (!hdmi_in->frl.lanes || hdmi_in->frl.lanes > 4) + return -EINVAL; + + if (frl_rate !=3D FRL_8G4L_RATE) { + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) + if (frl_rate =3D=3D rk_hdptx_frl_lcpll_cfg[i].rate) + break; + if (i =3D=3D ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg)) + return -EINVAL; + } + + if (hdmi_out) + hdmi_out->rate =3D frl_rate; + } else { + if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RAT= E) + return -EINVAL; + + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) + if (hdmi_in->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) + break; + + if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && + !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL)) + return -EINVAL; + + if (hdmi_out) + hdmi_out->rate =3D hdmi_in->tmds_char_rate; + } =20 switch (hdmi_in->bpc) { case 0: @@ -1504,10 +1838,8 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, return -EINVAL; } =20 - if (hdmi_out) { - hdmi_out->rate =3D hdmi_in->tmds_char_rate; + if (hdmi_out) hdmi_out->bpc =3D hdmi_in->bpc ?: 8; - } =20 return 0; } @@ -1862,17 +2194,61 @@ static void rk_hdptx_phy_clk_unprepare(struct clk_h= w *hw) =20 static unsigned long rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdp= tx_phy *hdptx) { + struct lcpll_config lcpll_hw; struct ropll_config ropll_hw; u64 fout, sdm; u32 mode, val; - int ret; + int ret, i; =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(0008), &mode); if (ret) return 0; =20 - if (mode & LCPLL_LCVCO_MODE_EN_MASK) + if (mode & LCPLL_LCVCO_MODE_EN_MASK) { + ret =3D regmap_read(hdptx->regmap, CMN_REG(0020), &val); + if (ret) + return 0; + lcpll_hw.pms_mdiv =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0023), &val); + return 0; + lcpll_hw.pms_sdiv =3D val & 0xf; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(002B), &val); + if (ret) + return 0; + lcpll_hw.sdm_num_sign =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(002C), &val); + if (ret) + return 0; + lcpll_hw.sdm_num =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(002A), &val); + if (ret) + return 0; + lcpll_hw.sdm_deno =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(002D), &val); + if (ret) + return 0; + lcpll_hw.sdc_n =3D (val & LCPLL_SDC_N_MASK) >> 1; + + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { + const struct lcpll_config *cfg =3D &rk_hdptx_frl_lcpll_cfg[i]; + + if (cfg->pms_mdiv =3D=3D lcpll_hw.pms_mdiv && + cfg->pms_sdiv =3D=3D lcpll_hw.pms_sdiv && + cfg->sdm_num_sign =3D=3D lcpll_hw.sdm_num_sign && + cfg->sdm_num =3D=3D lcpll_hw.sdm_num && + cfg->sdm_deno =3D=3D lcpll_hw.sdm_deno && + cfg->sdc_n =3D=3D lcpll_hw.sdc_n) + return cfg->rate; + } + + dev_dbg(hdptx->dev, "%s no FRL match found\n", __func__); return 0; + } =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(0051), &val); if (ret) @@ -2002,7 +2378,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *h= w, unsigned long rate, * while the latter being executed only once, i.e. when clock remains * in the prepared state during rate changes. */ - return rk_hdptx_tmds_ropll_cmn_config(hdptx); + return rk_hdptx_pll_cmn_config(hdptx); } =20 static const struct clk_ops hdptx_phy_clk_ops =3D { --=20 2.50.0