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Nguyen" , Nitin Rawat Subject: [PATCH V2 1/3] scsi: ufs: ufs-qcom: Update esi_vec_mask for HW major version >= 6 Date: Tue, 8 Jul 2025 02:32:58 +0530 Message-ID: <20250707210300.561-2-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250707210300.561-1-quic_nitirawa@quicinc.com> References: <20250707210300.561-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA3MDE0MSBTYWx0ZWRfX9xvS1MDgA4Sd ckttkqQ1yB6wU3GnduDll75xlD3euY93Ek2GzBu+aIafSPcB0n+i0Kecn30LYJXspszA03WKkM5 l7f7/ulkHEuH+BHoo0dQdLzmwHtgIBaGDLQYadstYdA5RTTGQxlZKKdGWPiwZ48wnN52YQK2cHL PewsaNKv21vRkk260dzLW9d9Gaqe5BzET7vrawBQ9ji/8NOJ5sZClbGSFNh+0dcV6OaxgId3QDR gFPkyMbUkT5gRXOWZkwhnqTjXq7dSiSYGCeTtRStt7WmQjyw3ZFJ0HFy65Jibngig8/l/kwUQx6 KvRuAHLwzFctRNnFiBb83xB6f+je4sdubbAh7J3RgPmYqDJHxpwIryu04t5sjL1aeUKwnNwBBPA mSNhfdBgDkQI2tCuPrpKp+R661U01iYothDcz/8yRaXBwDvar1OZDxW9ENQXc5ANaZWFHNmK X-Authority-Analysis: v=2.4 cv=Vq0jA/2n c=1 sm=1 tr=0 ts=686c360c cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=lUlEUqtdP5ObSgJ12z0A:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: CJqGhgtGr1-x0Ao-QCoxHY5x0b7Sdbuk X-Proofpoint-GUID: CJqGhgtGr1-x0Ao-QCoxHY5x0b7Sdbuk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-07_05,2025-07-07_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 clxscore=1011 mlxscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507070141 Content-Type: text/plain; charset="utf-8" From: "Bao D. Nguyen" The MCQ feature and ESI are supported by all Qualcomm UFS controller versions 6 and above. Therefore, update the ESI vector mask in the UFS_MEM_CFG3 register for platforms with major version number of 6 or higher. Signed-off-by: Bao D. Nguyen Signed-off-by: Nitin Rawat Reviewed-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 318dca7fe3d7..dfdc52333a96 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -2113,8 +2113,7 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba) =20 retain_and_null_ptr(qi); =20 - if (host->hw_ver.major =3D=3D 6 && host->hw_ver.minor =3D=3D 0 && - host->hw_ver.step =3D=3D 0) { + if (host->hw_ver.major >=3D 6) { ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), REG_UFS_CFG3); } --=20 2.48.1 From nobody Tue Oct 7 18:26:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A627C28507E; Mon, 7 Jul 2025 21:03:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Introduce `ufshcd_dme_rmw` API to read, modify, and write DME attributes in UFS host controllers using a mask and value. Signed-off-by: Nitin Rawat --- include/ufs/ufshcd.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 9b3515cee711..fe4bb248484c 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -1498,6 +1498,32 @@ static inline int ufshcd_vops_phy_initialization(str= uct ufs_hba *hba) return 0; } +/** + * ufshcd_dme_rmw - get modify set a dme attribute + * @hba - per adapter instance + * @mask - mask to apply on read value + * @val - actual value to write + * @attr - dme attribute + */ +static inline int ufshcd_dme_rmw(struct ufs_hba *hba, u32 mask, + u32 val, u32 attr) +{ + u32 cfg =3D 0; + int err =3D 0; + + err =3D ufshcd_dme_get(hba, UIC_ARG_MIB(attr), &cfg); + if (err) + goto out; + + cfg &=3D ~mask; + cfg |=3D (val & mask); + + err =3D ufshcd_dme_set(hba, UIC_ARG_MIB(attr), cfg); + +out: + return err; +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, -- 2.48.1 From nobody Tue Oct 7 18:26:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8225728724E; 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charset="utf-8" Enable internal clock gating for QUnipro by setting the following attributes to 1 during host controller initialization: - DL_VS_CLK_CFG - PA_VS_CLK_CFG_REG - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN This change is necessary to support the internal clock gating mechanism in Qualcomm UFS host controller. Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++++++++ drivers/ufs/host/ufs-qcom.h | 9 +++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index dfdc52333a96..25b5f83b049c 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -558,11 +558,32 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba = *hba) */ static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) { + int err =3D 0; + + /* Enable UTP internal clock gating */ ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2); /* Ensure that HW clock gating is enabled before next operations */ ufshcd_readl(hba, REG_UFS_CFG2); + + /* Enable Unipro internal clock gating */ + err =3D ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK, + DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG); + if (err) + goto out; + + err =3D ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK, + PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG); + if (err) + goto out; + + err =3D ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, + DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, + DME_VS_CORE_CLK_CTRL); +out: + if (err) + dev_err(hba->dev, "hw clk gating enabled failed\n"); } static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 0a5cfc2dd4f7..e0e129af7c16 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -24,6 +24,15 @@ #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B +/* bit and mask definitions for PA_VS_CLK_CFG_REG attribute */ +#define PA_VS_CLK_CFG_REG 0x9004 +#define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0) + +/* bit and mask definitions for DL_VS_CLK_CFG attribute */ +#define DL_VS_CLK_CFG 0xA00B +#define DL_VS_CLK_CFG_MASK GENMASK(9, 0) +#define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) + /* QCOM UFS host controller vendor specific registers */ enum { REG_UFS_SYS1CLK_1US =3D 0xC0, -- 2.48.1