From nobody Tue Oct 7 18:22:21 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A0AB21507F; Mon, 7 Jul 2025 20:18:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751919527; cv=none; b=TgmsNihrkG6PrpEMvHsahUlu3udfWBh+bDKWK2LAaR2xUTYOrgV8RmmxhWU1EFhUIuARayf3vo9I5XEi/6XDUaD/IOjrcB01W6NXnJjRUChsAUDVvPK44UvpDcgxsC6X0iIhB+BFW/OThwMxWgCJq+lvxvi1nTouYhVKIBjYF+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751919527; c=relaxed/simple; bh=Tn6v3UPbVoyPyh7UO946RFT7Ewk6J0+oBiv59RBuMqM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=seXz8qXDaaM57EDM1qqouKuUSXt8Rf1+G3izNAX3iofb4s/hhf8/j382WDVXYbeVe9pSYNEY2X7OrdKa21n2CPnp0sIvt+oDoPjeba7X5jkLZ+PrGv1r6dlaahLtF3crjuNbVy8O+zjKdV2wt7F5OUI6UOwr3YroqTM4l7lV5JE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DZb6B9xj; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DZb6B9xj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751919525; x=1783455525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Tn6v3UPbVoyPyh7UO946RFT7Ewk6J0+oBiv59RBuMqM=; b=DZb6B9xjo8a6a3vUGZu+pTHVWzRriEDqivt9qdq3Pjrk8/873Z5du/AS V/0LSQUF2uDzmpKbe3L8Ta6T9OcVrYCfQkjdNcLmttHoa1lT29ulfHSbN uoptmISt6cnED85a0bHXWhW4XZFJtqZfNBO1aL/Gu6dbJHvsYtz2QQUC3 3jct156dnjRWHD7ngDJ8rURGFvmuk8jK+25MnSrZ30P1kQ9ta8bRy+vAv ghIWp57STDqRxsHAuiE2uMY6iadqNy0GZbzgxULk0GWifI4YiiFcBuqXd sInM5NYUgGwkSaBh47AVnJ5xWqu9S0AgoADOJyRo8UQ6Sn/JTTVzArTK1 A==; X-CSE-ConnectionGUID: 6RmxwCpbTliIrk/Xf+1Riw== X-CSE-MsgGUID: nJbdArKxSjanxFu8zBh91w== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="53362311" X-IronPort-AV: E=Sophos;i="6.16,295,1744095600"; d="scan'208";a="53362311" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2025 13:18:44 -0700 X-CSE-ConnectionGUID: UnWDz/KEQjeEIkRKKGPRIQ== X-CSE-MsgGUID: OBCcFeLwQUWZHXHn7fN0LQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,295,1744095600"; d="scan'208";a="159343671" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa003.fm.intel.com with ESMTP; 07 Jul 2025 13:18:44 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: dapeng1.mi@linux.intel.com, Kan Liang Subject: [PATCH V4 1/4] perf/x86/intel/uncore: Support MSR portal for discovery tables Date: Mon, 7 Jul 2025 13:17:47 -0700 Message-Id: <20250707201750.616527-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250707201750.616527-1-kan.liang@linux.intel.com> References: <20250707201750.616527-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang Starting from the Panther Lake, the discovery table mechanism is also supported in client platforms. The difference is that the portal of the global discovery table is retrieved from an MSR. The layout of discovery tables are the same as the server platforms. Factor out __parse_discovery_table() to parse discover tables. The uncore PMON is Die scope. Need to parse the discovery tables for each die. Reviewed-by: Dapeng Mi Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_discovery.c | 87 ++++++++++++++++++------ arch/x86/events/intel/uncore_discovery.h | 3 + 2 files changed, 70 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 571e44b49691..8680f66c3e34 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -273,32 +273,15 @@ uncore_ignore_unit(struct uncore_unit_discovery *unit= , int *ignore) return false; } =20 -static int parse_discovery_table(struct pci_dev *dev, int die, - u32 bar_offset, bool *parsed, - int *ignore) +static int __parse_discovery_table(resource_size_t addr, int die, + bool *parsed, int *ignore) { struct uncore_global_discovery global; struct uncore_unit_discovery unit; void __iomem *io_addr; - resource_size_t addr; unsigned long size; - u32 val; int i; =20 - pci_read_config_dword(dev, bar_offset, &val); - - if (val & ~PCI_BASE_ADDRESS_MEM_MASK & ~PCI_BASE_ADDRESS_MEM_TYPE_64) - return -EINVAL; - - addr =3D (resource_size_t)(val & PCI_BASE_ADDRESS_MEM_MASK); -#ifdef CONFIG_PHYS_ADDR_T_64BIT - if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) =3D=3D PCI_BASE_ADDRESS_MEM_TY= PE_64) { - u32 val2; - - pci_read_config_dword(dev, bar_offset + 4, &val2); - addr |=3D ((resource_size_t)val2) << 32; - } -#endif size =3D UNCORE_DISCOVERY_GLOBAL_MAP_SIZE; io_addr =3D ioremap(addr, size); if (!io_addr) @@ -341,7 +324,32 @@ static int parse_discovery_table(struct pci_dev *dev, = int die, return 0; } =20 -bool intel_uncore_has_discovery_tables(int *ignore) +static int parse_discovery_table(struct pci_dev *dev, int die, + u32 bar_offset, bool *parsed, + int *ignore) +{ + resource_size_t addr; + u32 val; + + pci_read_config_dword(dev, bar_offset, &val); + + if (val & ~PCI_BASE_ADDRESS_MEM_MASK & ~PCI_BASE_ADDRESS_MEM_TYPE_64) + return -EINVAL; + + addr =3D (resource_size_t)(val & PCI_BASE_ADDRESS_MEM_MASK); +#ifdef CONFIG_PHYS_ADDR_T_64BIT + if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) =3D=3D PCI_BASE_ADDRESS_MEM_TY= PE_64) { + u32 val2; + + pci_read_config_dword(dev, bar_offset + 4, &val2); + addr |=3D ((resource_size_t)val2) << 32; + } +#endif + + return __parse_discovery_table(addr, die, parsed, ignore); +} + +static bool intel_uncore_has_discovery_tables_pci(int *ignore) { u32 device, val, entry_id, bar_offset; int die, dvsec =3D 0, ret =3D true; @@ -390,6 +398,45 @@ bool intel_uncore_has_discovery_tables(int *ignore) return ret; } =20 +static bool intel_uncore_has_discovery_tables_msr(int *ignore) +{ + unsigned long *die_mask; + bool parsed =3D false; + int cpu, die; + u64 base; + + die_mask =3D kcalloc(BITS_TO_LONGS(uncore_max_dies()), + sizeof(unsigned long), GFP_KERNEL); + if (!die_mask) + return false; + + cpus_read_lock(); + for_each_online_cpu(cpu) { + die =3D topology_logical_die_id(cpu); + if (__test_and_set_bit(die, die_mask)) + continue; + + if (rdmsrq_safe_on_cpu(cpu, UNCORE_DISCOVERY_MSR, &base)) + continue; + + if (!base) + continue; + + __parse_discovery_table(base, die, &parsed, ignore); + } + + cpus_read_unlock(); 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charset="utf-8" From: Kan Liang For a server platform, the MMIO map size is always 0x4000. However, a client platform may have a smaller map size. Make the map size customizable. Reviewed-by: Dapeng Mi Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_discovery.c | 2 +- arch/x86/events/intel/uncore_snbep.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 8680f66c3e34..142cf714bfe2 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -650,7 +650,7 @@ void intel_generic_uncore_mmio_init_box(struct intel_un= core_box *box) } =20 addr =3D unit->addr; - box->io_addr =3D ioremap(addr, UNCORE_GENERIC_MMIO_SIZE); + box->io_addr =3D ioremap(addr, type->mmio_map_size); if (!box->io_addr) { pr_warn("Uncore type %d box %d: ioremap error for 0x%llx.\n", type->type_id, unit->id, (unsigned long long)addr); diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 76d96df1475a..2f5c2eb1ce0c 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6408,6 +6408,8 @@ static void uncore_type_customized_copy(struct intel_= uncore_type *to_type, to_type->get_topology =3D from_type->get_topology; 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d="scan'208";a="159343675" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa003.fm.intel.com with ESMTP; 07 Jul 2025 13:18:44 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: dapeng1.mi@linux.intel.com, Kan Liang Subject: [PATCH V4 3/4] perf/x86/intel/uncore: Add Panther Lake support Date: Mon, 7 Jul 2025 13:17:49 -0700 Message-Id: <20250707201750.616527-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250707201750.616527-1-kan.liang@linux.intel.com> References: <20250707201750.616527-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The Panther Lake supports CBOX, MC, sNCU, and HBO uncore PMON. The CBOX is similar to Lunar Lake. The only difference is the number of CBOX. The other three uncore PMON can be retrieved from the discovery table. The global control register resides in the sNCU. The global freeze bit is set by default. It must be cleared before monitoring any uncore counters. Reviewed-by: Dapeng Mi Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore.c | 7 +++ arch/x86/events/intel/uncore.h | 2 + arch/x86/events/intel/uncore_discovery.h | 4 ++ arch/x86/events/intel/uncore_snb.c | 71 ++++++++++++++++++++++++ arch/x86/events/intel/uncore_snbep.c | 2 +- 5 files changed, 85 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 5811e172f721..8a4f5a86e18d 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1806,6 +1806,12 @@ static const struct intel_uncore_init_fun lnl_uncore= _init __initconst =3D { .mmio_init =3D lnl_uncore_mmio_init, }; =20 +static const struct intel_uncore_init_fun ptl_uncore_init __initconst =3D { + .cpu_init =3D ptl_uncore_cpu_init, + .mmio_init =3D ptl_uncore_mmio_init, + .use_discovery =3D true, +}; + static const struct intel_uncore_init_fun icx_uncore_init __initconst =3D { .cpu_init =3D icx_uncore_cpu_init, .pci_init =3D icx_uncore_pci_init, @@ -1887,6 +1893,7 @@ static const struct x86_cpu_id intel_uncore_match[] _= _initconst =3D { X86_MATCH_VFM(INTEL_ARROWLAKE_U, &mtl_uncore_init), X86_MATCH_VFM(INTEL_ARROWLAKE_H, &mtl_uncore_init), X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_uncore_init), + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &ptl_uncore_init), X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_uncore_init), X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_uncore_init), X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_uncore_init), diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 3dcb88c0ecfa..d8815fff7588 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -612,10 +612,12 @@ void tgl_uncore_cpu_init(void); void adl_uncore_cpu_init(void); void lnl_uncore_cpu_init(void); void mtl_uncore_cpu_init(void); +void ptl_uncore_cpu_init(void); void tgl_uncore_mmio_init(void); void tgl_l_uncore_mmio_init(void); void adl_uncore_mmio_init(void); void lnl_uncore_mmio_init(void); +void ptl_uncore_mmio_init(void); int snb_pci2phy_map_init(int devid); =20 /* uncore_snbep.c */ diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 690f737e6837..dff75c98e22f 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -171,3 +171,7 @@ bool intel_generic_uncore_assign_hw_event(struct perf_e= vent *event, struct intel_uncore_box *box); void uncore_find_add_unit(struct intel_uncore_discovery_unit *node, struct rb_root *root, u16 *num_units); +struct intel_uncore_type ** +uncore_get_uncores(enum uncore_access_type type_id, int num_extra, + struct intel_uncore_type **extra, int max_num_types, + struct intel_uncore_type **uncores); diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index edb7fd50efe0..817dddc1454d 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -1854,3 +1854,74 @@ void lnl_uncore_mmio_init(void) } =20 /* end of Lunar Lake MMIO uncore support */ + +/* Panther Lake uncore support */ + +#define UNCORE_PTL_MAX_NUM_UNCORE_TYPES 42 +#define UNCORE_PTL_TYPE_IMC 6 +#define UNCORE_PTL_TYPE_SNCU 34 +#define UNCORE_PTL_TYPE_HBO 41 + +#define PTL_UNCORE_GLOBAL_CTL_OFFSET 0x380 + +static struct intel_uncore_type ptl_uncore_imc =3D { + .name =3D "imc", + .mmio_map_size =3D 0xf00, +}; + +static void ptl_uncore_sncu_init_box(struct intel_uncore_box *box) +{ + intel_generic_uncore_mmio_init_box(box); + + /* Clear the global freeze bit */ + if (box->io_addr) + writel(0, box->io_addr + PTL_UNCORE_GLOBAL_CTL_OFFSET); +} + +static struct intel_uncore_ops ptl_uncore_sncu_ops =3D { + .init_box =3D ptl_uncore_sncu_init_box, + .exit_box =3D uncore_mmio_exit_box, + .disable_box =3D intel_generic_uncore_mmio_disable_box, + .enable_box =3D intel_generic_uncore_mmio_enable_box, + .disable_event =3D intel_generic_uncore_mmio_disable_event, + .enable_event =3D intel_generic_uncore_mmio_enable_event, + .read_counter =3D uncore_mmio_read_counter, +}; + +static struct intel_uncore_type ptl_uncore_sncu =3D { + .name =3D "sncu", + .ops =3D &ptl_uncore_sncu_ops, + .mmio_map_size =3D 0xf00, +}; + +static struct intel_uncore_type ptl_uncore_hbo =3D { + .name =3D "hbo", + .mmio_map_size =3D 0xf00, +}; + +static struct intel_uncore_type *ptl_uncores[UNCORE_PTL_MAX_NUM_UNCORE_TYP= ES] =3D { + [UNCORE_PTL_TYPE_IMC] =3D &ptl_uncore_imc, + [UNCORE_PTL_TYPE_SNCU] =3D &ptl_uncore_sncu, + [UNCORE_PTL_TYPE_HBO] =3D &ptl_uncore_hbo, +}; + +void ptl_uncore_mmio_init(void) +{ + uncore_mmio_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, + UNCORE_PTL_MAX_NUM_UNCORE_TYPES, + ptl_uncores); +} + +static struct intel_uncore_type *ptl_msr_uncores[] =3D { + &mtl_uncore_cbox, + NULL +}; + +void ptl_uncore_cpu_init(void) +{ + mtl_uncore_cbox.num_boxes =3D 6; + mtl_uncore_cbox.ops =3D &lnl_uncore_msr_ops; + uncore_msr_uncores =3D ptl_msr_uncores; +} + +/* end of Panther Lake uncore support */ diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 2f5c2eb1ce0c..b19c262d47f5 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6412,7 +6412,7 @@ static void uncore_type_customized_copy(struct intel_= uncore_type *to_type, to_type->mmio_map_size =3D from_type->mmio_map_size; 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d="scan'208";a="159343676" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa003.fm.intel.com with ESMTP; 07 Jul 2025 13:18:44 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: dapeng1.mi@linux.intel.com, Kan Liang Subject: [PATCH V4 4/4] perf/x86/intel/uncore: Add iMC freerunning for Panther Lake Date: Mon, 7 Jul 2025 13:17:50 -0700 Message-Id: <20250707201750.616527-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250707201750.616527-1-kan.liang@linux.intel.com> References: <20250707201750.616527-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang PTL uncore imc freerunning counters are the same as the previous HW. Reviewed-by: Dapeng Mi Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_snb.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index 817dddc1454d..a8c4afc9cdff 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -1905,9 +1905,17 @@ static struct intel_uncore_type *ptl_uncores[UNCORE_= PTL_MAX_NUM_UNCORE_TYPES] =3D [UNCORE_PTL_TYPE_HBO] =3D &ptl_uncore_hbo, }; =20 +#define UNCORE_PTL_MMIO_EXTRA_UNCORES 1 + +static struct intel_uncore_type *ptl_mmio_extra_uncores[UNCORE_PTL_MMIO_EX= TRA_UNCORES] =3D { + &adl_uncore_imc_free_running, +}; + void ptl_uncore_mmio_init(void) { - uncore_mmio_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, + uncore_mmio_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MMIO, + UNCORE_PTL_MMIO_EXTRA_UNCORES, + ptl_mmio_extra_uncores, UNCORE_PTL_MAX_NUM_UNCORE_TYPES, ptl_uncores); } --=20 2.38.1