From nobody Tue Oct 7 18:25:19 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29CBA230BC9; Mon, 7 Jul 2025 16:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907221; cv=none; b=lNE3H5qab+1IUdV24XSb29wWc7505heed0TQdxb9YZkd5XCoxFYDiG6TqpVtj8gre7HGeohVJ4Cs8yzXUHSY3uiaHB7zlrVFE1d5TVJL8yDOakQKcNDyHSNenmQMWfMtsPvTzYz8G2IbPAvj3esL2DOW/QZZh+vTWkpA3HsE+yA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907221; c=relaxed/simple; bh=fyzQhFsUd32Xtyioz+AW/2SgTMkJKNT0SjViBBy68L8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Dgb/JcSAXSNMfAPtM4v0Z5vbPKxkqvw9t8R5mZGbE3uQIu4TLzX8HESH38305T7ma+reCy6QlrAomKnSUzOxt6E3XQNWmw521GLv60tCBHUJx+uCh5DDZtSpRt/sC2C6yrzU9XYcxrDM7vdpMKUucrUf0KGDcWAwVJXw3+xMONs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id D6D911F00036; Mon, 7 Jul 2025 16:53:36 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 6D66FACAEF2; Mon, 7 Jul 2025 16:53:36 +0000 (UTC) X-Spam-Level: ** Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id CF175ACAEE1; Mon, 7 Jul 2025 16:52:08 +0000 (UTC) From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Paul Kocialkowski , Andre Przywara Subject: [PATCH v2 1/4] Revert "pinctrl: sunxi: Fix a100 emac pin function name" Date: Mon, 7 Jul 2025 18:51:52 +0200 Message-ID: <20250707165155.581579-2-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250707165155.581579-1-paulk@sys-base.io> References: <20250707165155.581579-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While the A100/A133 chips only expose a single EMAC, the sun50iw10 die that they share actually has two such controllers. One specific package, the T509 is reported to expose both ports. Since we want to keep the pinctrl function names unique accross packages of the same die to share a single common base dtsi, keep the emac0 naming in order to allow the introduction of the emac1 function in the future. Note that the original commit also breaks the ABI between the driver and the device-tree. It's however unlikely that anybody would have complained about that since the a100/a133 port is still very early and experimental. Fixes: d4775ba60b55 ("pinctrl: sunxi: Fix a100 emac pin function name") Signed-off-by: Paul Kocialkowski --- drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/= sunxi/pinctrl-sun50i-a100.c index 95b764ee1c0d..b97de80ae2f3 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ - SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ - SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ - SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ SUNXI_FUNCTION(0x3, "cir0"), /* OUT */ - SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */ + SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart3"), /* TX */ SUNXI_FUNCTION(0x3, "spi1"), /* CS */ - SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "uart3"), /* RX */ SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ SUNXI_FUNCTION(0x4, "ledc"), - SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x5, "emac"), /* TXCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ SUNXI_FUNCTION(0x4, "spdif"), /* OUT */ - SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */ SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */ - SUNXI_FUNCTION(0x5, "emac"), /* MDC */ + SUNXI_FUNCTION(0x5, "emac0"), /* MDC */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */ SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */ - SUNXI_FUNCTION(0x5, "emac"), /* MDIO */ + SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */ SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */ - SUNXI_FUNCTION(0x5, "emac"), /* EPHY */ + SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */ - SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */ - SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */ SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */ - SUNXI_FUNCTION(0x5, "emac"), /* RXCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */ SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */ - SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "cir0"), /* OUT */ SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */ SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */ - SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), SUNXI_FUNCTION(0x0, "gpio_in"), --=20 2.49.0 From nobody Tue Oct 7 18:25:19 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEE3C2264A1; Mon, 7 Jul 2025 16:54:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907253; cv=none; b=b+FqzVRMqUatlmViJfmPqTGpJveVorIUolfKxsO9EDiiRwBlV7Y4zwldCXmsURKmv1O7cbWWRbt2E/FTbvpqC2yIVNA4lBw7vJ/iCMYi9B68E8weDqlOTWxcFL1Xag6qp7tKm2bUmByaOesG0RIhwQE+Wal3cXv2Nwc0buEinmg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907253; c=relaxed/simple; bh=dSDtzgHJhb5nkTok5hdWeyc72epjdPSgyP5Q3UFWO2c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qxsvzmcqLkrN6Hl7w/cHEpChIaNbwMa6VMx3Z6vh8CBq2N0sBRHPTBf/V8AVE+CGYM5C4BfqdxCJtOLRH1EJK0QnLdy9ZcPKFswJt+CJ43dACc//Hh5vu69RXgWBOBCLlk0fbye7PKOh6CL8orGR9s0f2ogrGrLCpyHi0ifM2Ao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id F30621F00036; Mon, 7 Jul 2025 16:54:09 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 747B4ACAEF1; Mon, 7 Jul 2025 16:54:09 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id 25322ACAEE3; Mon, 7 Jul 2025 16:52:09 +0000 (UTC) From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Paul Kocialkowski , Andre Przywara Subject: [PATCH v2 2/4] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII Date: Mon, 7 Jul 2025 18:51:53 +0200 Message-ID: <20250707165155.581579-3-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250707165155.581579-1-paulk@sys-base.io> References: <20250707165155.581579-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A100/A133 supports both RGMII and RMII for its Ethernet MAC (EMAC) controller. Add corresponding pin definitions. Note that the sun50iw10 die actually includes two ethernet controllers, the second of which is rarely exposed to pins. Call the first controller "emac0" to distinguish it from the second that may be added later. Signed-off-by: Paul Kocialkowski Reviewed-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-a100.dtsi index bd366389b238..7d5be0975371 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -236,6 +236,21 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; =20 + rgmii0_pins: rgmii0-pins { + pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH9", "PH10", + "PH14", "PH15", "PH16", "PH17", "PH18"; + function =3D "emac0"; + drive-strength =3D <40>; + }; + + rmii0_pins: rmii0-pins { + pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH9", "PH10"; + function =3D "emac0"; + drive-strength =3D <40>; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; function =3D "uart0"; --=20 2.49.0 From nobody Tue Oct 7 18:25:19 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23DA02248BE; Mon, 7 Jul 2025 16:54:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907286; cv=none; b=ROUEo7OCIshUsPNBe0M3ETRxwU8k668x2SD+JG75hhAoxhrd/uu/fwXxylRL3WlUm9ll2iHlwDFWEJGTqkD5OR6e03GYHhl9HpJUBtOtPw7/BHVAaOyE81pTHOaJ4nvzARJijWlgo4OCOy58kRU4wsrRrgGgzHHZK0q16cjih5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907286; c=relaxed/simple; bh=0seKsdu78KnTo7icy4rcHTT6ILJuEucr44ksvECQsas=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qRSuhayEOfG68aTJpr3bplWPwOpUx6S48PK6ydQjw6kIi8XdeJIN9LSb4Xem5Q5JvIQHGX6bFQSvKP5zZBbixJrsw+bJuuG03ZGNqp4Ef7rQa5rpC7I73jMuMMo9xslzWhYsCXQrECuiDI14awIvhgpB2eG39d6x+xTo1x6md7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 3E05A1F0003D; Mon, 7 Jul 2025 16:54:43 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id BB1FBACAEF9; Mon, 7 Jul 2025 16:54:42 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id 6C9C4ACAEE4; Mon, 7 Jul 2025 16:52:09 +0000 (UTC) From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Paul Kocialkowski , Andre Przywara Subject: [PATCH v2 3/4] arm64: dts: allwinner: a100: Add EMAC support Date: Mon, 7 Jul 2025 18:51:54 +0200 Message-ID: <20250707165155.581579-4-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250707165155.581579-1-paulk@sys-base.io> References: <20250707165155.581579-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A100/A133 Ethernet MAC (EMAC) is compatible with the A64 one and needs access to the syscon register for control of the top-level integration of the unit. Note that there are two such controllers on the sun50iw10 die, which are the same unit with a different top-level syscon register offset. Signed-off-by: Paul Kocialkowski Reviewed-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-a100.dtsi index 7d5be0975371..bb5f9e4f3d42 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -420,6 +420,26 @@ i2c3: i2c@5002c00 { #size-cells =3D <0>; }; =20 + emac0: ethernet@5020000 { + compatible =3D "allwinner,sun50i-a100-emac", + "allwinner,sun50i-a64-emac"; + reg =3D <0x5020000 0x10000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&ccu CLK_BUS_EMAC>; + clock-names =3D "stmmaceth"; + resets =3D <&ccu RST_BUS_EMAC>; + reset-names =3D "stmmaceth"; + syscon =3D <&syscon>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + ths: thermal-sensor@5070400 { compatible =3D "allwinner,sun50i-a100-ths"; reg =3D <0x05070400 0x100>; --=20 2.49.0 From nobody Tue Oct 7 18:25:19 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27284235072; Mon, 7 Jul 2025 16:55:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907329; cv=none; b=ECa4E0zSL6MNT7pePcZMm2eZpchb04BEx3gQcZNP5qD9EpYm1d9RZdlAqPYRhsFMIrZcMx10lBs8GQKgfMctVSqM8lFqTCtnonchbSuUxtdWwixW0X+Aq7r6tCFcwlQETWacxf3+8tmW2g563STNyAlWPwVIlCKNIIchCya0xcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907329; c=relaxed/simple; bh=fmYsyqOj7xyzuv9dYNoPWOc7xZpihZk5OLNjpTm9Yjw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lBsRYO/tnguNT19xEbJu6loB/TEmct2A+1pKr5g90R+rD2PjJhUZDRLBZu3mNzOnKwhMx9nEbd1yTPgta75cR1G3WxytygXwoNdTBhcbEQnX0NOSIRNrYctc5PrLNHrA+6Ufnp94g/cHeDSyXlLel8havhEBZeFq1QHe3ZUxlp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 54B341F00036; Mon, 7 Jul 2025 16:55:26 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id D0712ACAEFE; Mon, 7 Jul 2025 16:55:25 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id C1D24ACAEE5; Mon, 7 Jul 2025 16:52:09 +0000 (UTC) From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Paul Kocialkowski , Andre Przywara Subject: [PATCH v2 4/4] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support Date: Mon, 7 Jul 2025 18:51:55 +0200 Message-ID: <20250707165155.581579-5-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250707165155.581579-1-paulk@sys-base.io> References: <20250707165155.581579-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Liontron H-A133L board features an Ethernet controller with a JLSemi JL1101 PHY. Its reset pin is tied to the PH12 GPIO. Note that the reset pin must be handled as a bus-wide reset GPIO in order to let the MDIO core properly reset it before trying to read its identification registers. There's no other device on the MDIO bus. The datasheet of the PHY mentions that the reset signal must be held for 1 ms to take effect. Make it 2 ms (and the same for post-delay) to be on the safe side without wasting too much time during boot. Signed-off-by: Paul Kocialkowski Reviewed-by: Andre Przywara Tested-by: Andre Przywara --- .../sun50i-a133-liontron-h-a133l.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts= b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts index fe77178d3e33..90a50910f07b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts @@ -65,6 +65,25 @@ &ehci1 { status =3D "okay"; }; =20 +&emac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rmii0_pins>; + phy-handle =3D <&rmii_phy>; + phy-mode =3D "rmii"; + status =3D "okay"; +}; + +&mdio0 { + reset-gpios =3D <&pio 7 12 GPIO_ACTIVE_LOW>; /* PH12 */ + reset-delay-us =3D <2000>; + reset-post-delay-us =3D <2000>; + + rmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + &mmc0 { vmmc-supply =3D <®_dcdc1>; cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ --=20 2.49.0