From nobody Tue Oct 7 19:55:43 2025 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F6E9255F22; Mon, 7 Jul 2025 16:55:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907358; cv=none; b=nDTky3ZoEX4ouWsts2S4OUY/4Mte4B65ES8xrvInlNUJr02KCKQvMVoq8FUtaov96MzRDQtX6Bhw3J4jnHXf5LUqHsSZRpJ2Aq2rD+XD6wc74HH0XQO2AJZyDQgkHSLu7Aze4FrdHbwuCG2SphM631QZ4XPhsSiQtwWeOkOv8Zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751907358; c=relaxed/simple; bh=HTYtfIZaU0IISaNC8EoPJlLRQ0RpkF34zxfeQMah8mw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tH7RjmWu9yC+57CYzZ3F494bqzbzwrbXZriOuOrOw/ugdk19CG9eM4txUrPb221p+ldXXHypAWW023oZzYlcWm8UgxCJ1WxDiHboGsmfm0SQuVcaxbLmBL72yJ3waEY9FDHAUxPEXf92KguQe37MNTsw9QxqRT9FUudxCMvyp2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=yveiteqG; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="yveiteqG" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=FBkOzD22uC8TIZOltlSVNHsJqb3ZyD7/5ACUKJRygzc=; b=yveiteqGRw+GqinEANa2wqFgJC NNpONaZ55YGsw8HuCGIfqEktn/gV9sC16ymuH5WCeG70RYOSpsYsZBHpyNLk9oOp5GgcBNxHc2w7s pfXFhhEavvPZYn7gywwDbQpMhpLu97n0XlUqA8+zBYhyIQy2fVsT3YyNKR+qwbQBk9YNlMzzgsLFk XtcatsDyQqbxq8SlHKfFgiodjFVamhh2mPD8wjDcPQeEFuzMrhahHsKLXtJz0qyzoYv3s3/c280Wz 6YwQ/2jtexiXlZWSuMUk8aNJkozqr+++nogYOt6M1+wTZxnt7xp0BKpbitr46Jev5LtQeWLcqA4YN V4iaKzVA==; Received: from i53875bf5.versanet.de ([83.135.91.245] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1uYp1y-0004yl-7q; Mon, 07 Jul 2025 18:49:26 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, hjc@rock-chips.com, andy.yan@rock-chips.com, andyshrk@163.com, nicolas.frattaroli@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 13/13] arm64: dts: rockchip: add dm-m10r800-v3s overlay for roc-rk3576-pc Date: Mon, 7 Jul 2025 18:49:06 +0200 Message-ID: <20250707164906.1445288-14-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250707164906.1445288-1-heiko@sntech.de> References: <20250707164906.1445288-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT-overlay for the DM-M10R800-V3S display module when connected to the ROC-RK3576-PC board. It contains a bestar,bsd1218-a101kl68 display and a Goodix GT911 touchscreen in one enclosed case. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rk3576-roc-pc-dm-m10r800-v3s.dtso | 134 ++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-roc-pc-dm-m10r800-v= 3s.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 4bf84622db47..f320dd2b5f6f 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-= io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-roc-pc-dm-m10r800-v3s.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-rock-4d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3582-radxa-e52c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-sige7.dtb @@ -225,6 +226,10 @@ rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=3D rk3568-wolfvi= sion-pf5.dtb \ rk3568-wolfvision-pf5-display-vz.dtbo \ rk3568-wolfvision-pf5-io-expander.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-roc-pc-dm-m10r800-v3s.dtb +rk3576-roc-pc-dm-m10r800-v3s-dtbs :=3D rk3576-roc-pc.dtb \ + rk3576-roc-pc-dm-m10r800-v3s.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-wifi.dtb rk3588-edgeble-neu6a-wifi-dtbs :=3D rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6a-wifi.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc-dm-m10r800-v3s.dtso= b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc-dm-m10r800-v3s.dtso new file mode 100644 index 000000000000..2817cc585c3a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc-dm-m10r800-v3s.dtso @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Heiko Stuebner + * + * DM-M10R800-V3S display module for ROC-RK3576-PC + * https://en.t-firefly.com/doc/download/303.html + * + * DT-overlay for the DM-M10R800-V3S display module when connected to a + * ROC-RK3576-PC board. It contains a bestar,bsd1218-a101kl68 display + * and a Goodix GT911 touchscreen in one enclosed case. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +&{/} { + backlight: backlight { + compatible =3D "pwm-backlight"; + enable-gpios =3D <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mipi_bl_en>; + pwms =3D <&pwm1_6ch_1 0 50000 1>; + }; + + vcc_tp: regulator-vcc-tp { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-tp"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + vin-supply =3D <&vcc5v0_device_s0>; + }; +}; + +&dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "bestar,bsd1218-a101kl68", "ilitek,ili9881c"; + reg =3D <0>; + backlight =3D <&backlight>; + power-supply =3D <&vcc3v3_lcd_s0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcd_reset_l>; + reset-gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; + + port { + mipi_panel_in: endpoint { + remote-endpoint =3D <&dsi_out_panel>; + }; + }; + }; +}; + +&dsi_in { + dsi_in_vp1: endpoint { + remote-endpoint =3D <&vp1_out_dsi>; + }; +}; + +&dsi_out { + dsi_out_panel: endpoint { + remote-endpoint =3D <&mipi_panel_in>; + }; +}; + +&i2c0 { + /* GT911 is limited to 400KHz */ + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0m1_xfer>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + irq-gpios =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&touch_int>, <&touch_reset>; + reset-gpios =3D <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&vcc_tp>; + VDDIO-supply =3D <&vcc3v3_lcd_s0>; + }; +}; + +&mipidcphy { + status =3D "okay"; +}; + +&pinctrl { + dsi { + lcd_reset_l: lcd-reset-l { + rockchip,pins =3D <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipi_bl_en: mipi-bl-en { + rockchip,pins =3D <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch_reset: touch-reset { + rockchip,pins =3D <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1_6ch_1 { + status =3D "okay"; +}; + +&vp1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + vp1_out_dsi: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg =3D ; + remote-endpoint =3D <&dsi_in_vp1>; + }; +}; --=20 2.47.2