From nobody Tue Oct 7 21:39:56 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A2DD29AB07; Mon, 7 Jul 2025 10:56:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751885785; cv=none; b=YZQvzSinhdjDjrfsyl8h5tCJn6ksm1NqzIPOSHHta4UjiT/HPNZ9SPg0DDl9CKe02Wi3iHy+8hyKQFBx2grnsGBXCqwwwXjTc/8rTK6q+ZErOXa23MJcFMCfq9dJTceTZx9M766L8Tm5v0cw7fhEHYsJCUS7RUvRmkN7FFphCuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751885785; c=relaxed/simple; bh=E24fd2LUiWtQTIC0yzAWsk85AKwpl4E7zLlCUOz8BTY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ILjDAYrVf453oYkREXRSRke0MnYphRbFNTks+cjV4sB5qpFzfz8aZAOYPE67fL1KQ37PuKhgZlo0Dzn5TgwcKjbbP0nvKWwJp0nM4TQrlDzIokG40ZYR9os+xGdtEcPU2K7Xf7DcxT7D3d6QUQIZP9u1m1QVVN16d7wV5iB1XrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=RJh83awn; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="RJh83awn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1751885781; bh=E24fd2LUiWtQTIC0yzAWsk85AKwpl4E7zLlCUOz8BTY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RJh83awn/4Min+y0Oc+V8OVIxs/FsenObGN84rpvffRiAb/KS+nFquaaH/9SBC4Az 44sBhR09/9Tk2OaBxKrBGINqh5qWhr7KdC8TNdkj6RKGFRgUU9dOwaexmjnLINDQUy fWCzCY1Yb1YjT0lfeLnv47F1+1vmODqyPzdQ9Lm68cRnnuz2p1XDsDLly4wI7LVs+u 44reRsb4pMOgDDPQ9+vBxEaBCDh9sMvHXwP1smUs3CpDAqmUpsUbORdSAosa4fKFUH elRDKGfJc4E3nIbjEGDjKMsxjuioHQk4s78QEPazoGsoTGN4PbGssyCsSYUEgPN9Fn W5+EE25WlO1Sg== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id E871C17E11EC; Mon, 7 Jul 2025 12:56:20 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ulf.hansson@linaro.org, y.oudjana@protonmail.com, fshao@chromium.org, wenst@chromium.org, lihongbo22@huawei.com, mandyjh.liu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v2 06/10] pmdomain: mediatek: Move ctl sequences out of power_on/off functions Date: Mon, 7 Jul 2025 12:56:01 +0200 Message-ID: <20250707105605.98248-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250707105605.98248-1-angelogioacchino.delregno@collabora.com> References: <20250707105605.98248-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In preparation to support power domains of new SoCs and the modem power domains for both new and already supported chips, move the generic control power sequences out of the scpsys_power_on() and scpsys_power_off() and put them in new scpsys_ctl_pwrseq_on(), scpsys_ctl_pewseq_off() functions. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 57 ++++++++++++++-------- 1 file changed, 38 insertions(+), 19 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index dd7f5f377271..92a3b523002b 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -244,11 +244,45 @@ static int scpsys_regulator_disable(struct regulator = *supply) return supply ? regulator_disable(supply) : 0; } =20 +static int scpsys_ctl_pwrseq_on(struct scpsys_domain *pd) +{ + struct scpsys *scpsys =3D pd->scpsys; + bool tmp; + int ret; + + /* subsys power on */ + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); + + /* wait until PWR_ACK =3D 1 */ + ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DE= LAY_US, + MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + + return 0; +} + +static void scpsys_ctl_pwrseq_off(struct scpsys_domain *pd) +{ + struct scpsys *scpsys =3D pd->scpsys; + + /* subsys power off */ + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); +} + static int scpsys_power_on(struct generic_pm_domain *genpd) { struct scpsys_domain *pd =3D container_of(genpd, struct scpsys_domain, ge= npd); struct scpsys *scpsys =3D pd->scpsys; - bool tmp; int ret; =20 ret =3D scpsys_regulator_enable(pd->supply); @@ -263,20 +297,10 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) regmap_clear_bits(scpsys->base, pd->data->ext_buck_iso_offs, pd->data->ext_buck_iso_mask); =20 - /* subsys power on */ - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); - - /* wait until PWR_ACK =3D 1 */ - ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DE= LAY_US, - MTK_POLL_TIMEOUT); - if (ret < 0) + ret =3D scpsys_ctl_pwrseq_on(pd); + if (ret) goto err_pwr_ack; =20 - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - /* * In few Mediatek platforms(e.g. MT6779), the bus protect policy is * stricter, which leads to bus protect release must be prior to bus @@ -342,12 +366,7 @@ static int scpsys_power_off(struct generic_pm_domain *= genpd) =20 clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); =20 - /* subsys power off */ - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); - regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); - regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + scpsys_ctl_pwrseq_off(pd); =20 /* wait until PWR_ACK =3D 0 */ ret =3D readx_poll_timeout(scpsys_domain_is_on, pd, tmp, !tmp, MTK_POLL_D= ELAY_US, --=20 2.49.0