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Mon, 7 Jul 2025 15:31:58 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Jul 2025 15:31:58 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , , , , , Subject: [PATCH v7 12/12] media: mediatek: jpeg: add jpeg smmu sid setting Date: Mon, 7 Jul 2025 15:31:45 +0800 Message-ID: <20250707073146.3581-13-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250707073146.3581-1-kyrie.wu@mediatek.com> References: <20250707073146.3581-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add a configuration to set jpeg dec & enc smmu sid Signed-off-by: Kyrie Wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 37 +++++++++++++++++++ .../platform/mediatek/jpeg/mtk_jpeg_core.h | 15 ++++++++ .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 23 ++++++++++++ .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 23 ++++++++++++ 4 files changed, 98 insertions(+) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.c index 1b6d691186f4..50aee7fe5142 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1614,6 +1615,20 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg= _dev *jpeg) return IRQ_HANDLED; } =20 +static void mtk_jpeg_enc_set_smmu_sid(struct mtk_jpegenc_comp_dev *jpeg) +{ + struct mtk_jpeg_dev *mjpeg =3D jpeg->master_dev; + + if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap) + return; + + regmap_update_bits(jpeg->smmu_regmap, JPEG_ENC_SMMU_SID, + JPG_REG_GUSER_ID_MASK << + JPG_REG_ENC_GUSER_ID_SHIFT, + JPG_REG_GUSER_ID_ENC_SID << + JPG_REG_ENC_GUSER_ID_SHIFT); +} + static void mtk_jpegenc_worker(struct work_struct *work) { struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX]; @@ -1675,6 +1690,9 @@ static void mtk_jpegenc_worker(struct work_struct *wo= rk) jpeg_dst_buf->frame_num =3D ctx->total_frame_num; ctx->total_frame_num++; mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base); + + mtk_jpeg_enc_set_smmu_sid(comp_jpeg[hw_id]); + mtk_jpeg_set_enc_dst(ctx, comp_jpeg[hw_id]->reg_base, &dst_buf->vb2_buf); @@ -1702,6 +1720,20 @@ static void mtk_jpegenc_worker(struct work_struct *w= ork) v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); } =20 +static void mtk_jpeg_dec_set_smmu_sid(struct mtk_jpegdec_comp_dev *jpeg) +{ + struct mtk_jpeg_dev *mjpeg =3D jpeg->master_dev; + + if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap) + return; + + regmap_update_bits(jpeg->smmu_regmap, JPEG_DEC_SMMU_SID, + JPG_REG_GUSER_ID_MASK << + JPG_REG_DEC_GUSER_ID_SHIFT, + JPG_REG_GUSER_ID_DEC_SID << + JPG_REG_DEC_GUSER_ID_SHIFT); +} + static void mtk_jpegdec_worker(struct work_struct *work) { struct mtk_jpeg_ctx *ctx =3D container_of(work, struct mtk_jpeg_ctx, @@ -1785,6 +1817,9 @@ static void mtk_jpegdec_worker(struct work_struct *wo= rk) jpeg_dst_buf->frame_num =3D ctx->total_frame_num; ctx->total_frame_num++; mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base); + + mtk_jpeg_dec_set_smmu_sid(comp_jpeg[hw_id]); + mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base, jpeg->variant->support_34bit, &jpeg_src_buf->dec_param, @@ -1944,6 +1979,7 @@ static struct mtk_jpeg_variant mtk8196_jpegenc_drvdat= a =3D { .cap_q_default_fourcc =3D V4L2_PIX_FMT_JPEG, .multi_core =3D true, .jpeg_worker =3D mtk_jpegenc_worker, + .support_smmu =3D true, }; =20 static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata =3D { @@ -1970,6 +2006,7 @@ static const struct mtk_jpeg_variant mtk8196_jpegdec_= drvdata =3D { .cap_q_default_fourcc =3D V4L2_PIX_FMT_YUV420M, .multi_core =3D true, .jpeg_worker =3D mtk_jpegdec_worker, + .support_smmu =3D true, }; =20 static const struct of_device_id mtk_jpeg_match[] =3D { diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.h index 33f7fbc4ca5e..6e8304680393 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -11,6 +11,7 @@ =20 #include #include +#include #include #include #include @@ -34,6 +35,14 @@ =20 #define MTK_JPEG_MAX_EXIF_SIZE (64 * 1024) =20 +#define JPEG_DEC_SMMU_SID 0 +#define JPEG_ENC_SMMU_SID 0 +#define JPG_REG_GUSER_ID_MASK 0x7 +#define JPG_REG_GUSER_ID_DEC_SID 0x4 +#define JPG_REG_GUSER_ID_ENC_SID 0x5 +#define JPG_REG_DEC_GUSER_ID_SHIFT 8 +#define JPG_REG_ENC_GUSER_ID_SHIFT 4 + #define MTK_JPEG_ADDR_MASK GENMASK(1, 0) =20 /** @@ -65,6 +74,7 @@ enum mtk_jpeg_ctx_state { * @multi_core: mark jpeg hw is multi_core or not * @jpeg_worker: jpeg dec or enc worker * @support_34bit: flag to check support for 34-bit DMA address + * @support_smmu: flag to check if support smmu */ struct mtk_jpeg_variant { struct clk_bulk_data *clks; @@ -82,6 +92,7 @@ struct mtk_jpeg_variant { bool multi_core; void (*jpeg_worker)(struct work_struct *work); bool support_34bit; + bool support_smmu; }; =20 struct mtk_jpeg_src_buf { @@ -150,6 +161,7 @@ struct mtk_jpegdec_clk { * @hw_param: jpeg encode hw parameters * @hw_state: record hw state * @hw_lock: spinlock protecting the hw device resource + * @smmu_regmap: SMMU registers mapping */ struct mtk_jpegenc_comp_dev { struct device *dev; @@ -163,6 +175,7 @@ struct mtk_jpegenc_comp_dev { enum mtk_jpeg_hw_state hw_state; /* spinlock protecting the hw device resource */ spinlock_t hw_lock; + struct regmap *smmu_regmap; }; =20 /** @@ -177,6 +190,7 @@ struct mtk_jpegenc_comp_dev { * @hw_param: jpeg decode hw parameters * @hw_state: record hw state * @hw_lock: spinlock protecting hw + * @smmu_regmap: SMMU registers mapping */ struct mtk_jpegdec_comp_dev { struct device *dev; @@ -190,6 +204,7 @@ struct mtk_jpegdec_comp_dev { enum mtk_jpeg_hw_state hw_state; /* spinlock protecting the hw device resource */ spinlock_t hw_lock; + struct regmap *smmu_regmap; }; =20 /** diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index e453a1634f33..da753a636eaa 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -624,6 +624,25 @@ static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_= comp_dev *dev) return 0; } =20 +static int mtk_jpegdec_smmu_init(struct mtk_jpegdec_comp_dev *dev) +{ + struct mtk_jpeg_dev *master_dev =3D dev->master_dev; + + if (!master_dev->variant->support_smmu) + return 0; + + dev->smmu_regmap =3D + syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node, + "mediatek,smmu-config"); + if (IS_ERR(dev->smmu_regmap)) { + return dev_err_probe(dev->dev, PTR_ERR(dev->smmu_regmap), + "mmap smmu_base failed(%ld)\n", + PTR_ERR(dev->smmu_regmap)); + } + + return 0; +} + static int mtk_jpegdec_hw_probe(struct platform_device *pdev) { struct mtk_jpegdec_clk *jpegdec_clk; @@ -677,6 +696,10 @@ static int mtk_jpegdec_hw_probe(struct platform_device= *pdev) dev->master_dev =3D master_dev; master_dev->max_hw_count++; =20 + ret =3D mtk_jpegdec_smmu_init(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); ret =3D devm_clk_bulk_get(dev->dev, diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index f30dccc93ecf..5e8a5cb4850e 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -348,6 +348,25 @@ static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_= comp_dev *dev) return 0; } =20 +static int mtk_jpegenc_smmu_init(struct mtk_jpegenc_comp_dev *dev) +{ + struct mtk_jpeg_dev *master_dev =3D dev->master_dev; + + if (!master_dev->variant->support_smmu) + return 0; + + dev->smmu_regmap =3D + syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node, + "mediatek,smmu-config"); + if (IS_ERR(dev->smmu_regmap)) { + return dev_err_probe(dev->dev, PTR_ERR(dev->smmu_regmap), + "mmap smmu_base failed(%ld)\n", + PTR_ERR(dev->smmu_regmap)); + } + + return 0; +} + static int mtk_jpegenc_hw_probe(struct platform_device *pdev) { struct mtk_jpegenc_clk *jpegenc_clk; @@ -399,6 +418,10 @@ static int mtk_jpegenc_hw_probe(struct platform_device= *pdev) dev->master_dev =3D master_dev; master_dev->max_hw_count++; =20 + ret =3D mtk_jpegenc_smmu_init(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); ret =3D devm_clk_bulk_get(dev->dev, --=20 2.46.0