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Mon, 7 Jul 2025 09:32:09 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 7 Jul 2025 09:32:09 +0800 From: shangyao lin To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Shangyao Lin , , , , , , , , Subject: [PATCH v2 03/13] dt-bindings: media: mediatek: add cam-raw binding Date: Mon, 7 Jul 2025 09:31:44 +0800 Message-ID: <20250707013154.4055874-4-shangyao.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250707013154.4055874-1-shangyao.lin@mediatek.com> References: <20250707013154.4055874-1-shangyao.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "shangyao.lin" Add camera isp7x module device document. --- Changes in v2: - Rename binding file to mediatek,mt8188-cam-raw.yaml - Various fixes per review comments - Update maintainers list Signed-off-by: shangyao.lin --- .../mediatek/mediatek,mt8188-cam-raw.yaml | 156 ++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100755 Documentation/devicetree/bindings/media/mediatek/mediat= ek,mt8188-cam-raw.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,mt81= 88-cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek= ,mt8188-cam-raw.yaml new file mode 100755 index 000000000000..dfedb229e79c --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,mt8188-cam-= raw.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2024 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The cam-raw unit of MediaTek ISP system + +maintainers: + - Shangyao Lin + - Shu-hsiang Yang + - Shun-yi Wang + - Teddy Chen + +description: + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC. + +properties: + compatible: + const: mediatek,mt8188-cam-raw + + reg: + minItems: 1 + maxItems: 2 + description: + Base address and optional inner base address of the cam-raw hardware= block. + + reg-names: + items: + - const: base + - const: inner_base + minItems: 1 + maxItems: 2 + description: + Names for each register region. Must be "base" and optionally "inner= _base". + + mediatek,larbs: + description: + List of phandles to the local arbiters in the current SoCs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 32 + + interrupts: + minItems: 1 + description: Interrupts for the cam-raw block. + + dma-ranges: + minItems: 1 + description: Address information of IOMMU mapping to memory. + + power-domains: + minItems: 1 + description: Power domains for the cam-raw block. + + clocks: + minItems: 4 + maxItems: 16 + description: List of phandles to the clocks required by the cam-raw bl= ock. + + clock-names: + items: + - const: camsys_cam2mm0_cgpdn + - const: camsys_cam2mm1_cgpdn + - const: camsys_cam2sys_cgpdn + - const: camsys_cam_cgpdn + - const: camsys_camtg_cgpdn + - const: camsys_rawa_larbx_cgpdn + - const: camsys_rawa_cam_cgpdn + - const: camsys_rawa_camtg_cgpdn + - const: topckgen_top_cam + - const: topckgen_top_camtg + - const: topckgen_top_camtm + minItems: 4 + maxItems: 16 + description: Names of the clocks, must match the order of the clocks p= roperty. + + iommus: + minItems: 1 + maxItems: 32 + description: Points to the respective IOMMU block with master port as = argument. + +required: + - compatible + - reg + - reg-names + - interrupts + - power-domains + - clocks + - clock-names + - iommus + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + raw@16030000 { + compatible =3D "mediatek,mt8188-cam-raw"; + reg =3D <0 0x16030000 0 0x8000>, + <0 0x16038000 0 0x8000>; + reg-names =3D "base", "inner_base"; + interrupts =3D ; + dma-ranges =3D <0x2 0x0 0x0 0x40000000 0x1 0x0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_CAM_SUBA>; + clocks =3D <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>, + <&camsys CLK_CAM_MAIN_CAM>, + <&camsys CLK_CAM_MAIN_CAMTG>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_CAMTG>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CAMTG>, + <&topckgen CLK_TOP_CAMTM>; + clock-names =3D "camsys_cam2mm0_cgpdn", + "camsys_cam2mm1_cgpdn", + "camsys_cam2sys_cgpdn", + "camsys_cam_cgpdn", + "camsys_camtg_cgpdn", + "camsys_rawa_larbx_cgpdn", + "camsys_rawa_cam_cgpdn", + "camsys_rawa_camtg_cgpdn", + "topckgen_top_cam", + "topckgen_top_camtg", + "topckgen_top_camtm"; + iommus =3D <&vpp_iommu M4U_PORT_L16A_IMGO_R1>, + <&vpp_iommu M4U_PORT_L16A_CQI_R1>, + <&vpp_iommu M4U_PORT_L16A_CQI_R2>, + <&vpp_iommu M4U_PORT_L16A_BPCI_R1>, + <&vpp_iommu M4U_PORT_L16A_LSCI_R1>, + <&vpp_iommu M4U_PORT_L16A_RAWI_R2>, + <&vpp_iommu M4U_PORT_L16A_RAWI_R3>, + <&vpp_iommu M4U_PORT_L16A_UFDI_R2>, + <&vpp_iommu M4U_PORT_L16A_UFDI_R3>, + <&vpp_iommu M4U_PORT_L16A_RAWI_R4>, + <&vpp_iommu M4U_PORT_L16A_RAWI_R5>, + <&vpp_iommu M4U_PORT_L16A_AAI_R1>, + <&vpp_iommu M4U_PORT_L16A_UFDI_R5>, + <&vpp_iommu M4U_PORT_L16A_FHO_R1>, + <&vpp_iommu M4U_PORT_L16A_AAO_R1>, + <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>, + <&vpp_iommu M4U_PORT_L16A_FLKO_R1>; + }; + }; + +... \ No newline at end of file --=20 2.18.0