From nobody Sat Feb 7 08:07:40 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12E961A2C0B; Mon, 7 Jul 2025 01:18:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751851124; cv=none; b=DOPRxLmU8jGYnAA7o4jFGIPMFu5zFLmdZKq6M5Ok6WRlvTJ15FZRa4Nnwv99EH9RWeWosU5ywUpTvk80kJywOPQImhPo+nFnh1oktDpzaFhRAEP8E18wm6U3/sSTphHCjv9xJtvCpsncFTMfjWfQBh01VXRoTTVmE/Yxg8PSads= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751851124; c=relaxed/simple; bh=nx+4yfd9amSKz8Vz+UsLsXfmfgGbrOOOX1pI9xGm/uo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K/vHuhrfXQrzSy8RrLEvyj9o0mOgHE7IaQaQNcmdH93YCNt5fT44KWvUw29Tqeq0W+TGR9+PWtaYrSlj0PHwdi1wqIJO+xnRhOFatNn6v2AuOw90WUmMUlfattsRfMNGJmvDcc/WlV4/I5Oqx+SfMbimYcvT3DvO5fezvCBS0+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 7 Jul 2025 09:18:27 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 7 Jul 2025 09:18:27 +0800 From: Ryan Chen To: ryan_chen , Michael Turquette , Stephen Boyd , Philipp Zabel , Joel Stanley , Andrew Jeffery , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , , , , , Mo Elbadry , "Rom Lemarchand" , William Kennington , "Yuxiao Zhang" , , , , Subject: [PATCH v11 2/3] reset: aspeed: register AST2700 reset auxiliary bus device Date: Mon, 7 Jul 2025 09:18:25 +0800 Message-ID: <20250707011826.3719229-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250707011826.3719229-1-ryan_chen@aspeedtech.com> References: <20250707011826.3719229-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AST2700 reset driver is registered as an auxiliary device due to reset and clock controller share the same register region. Signed-off-by: Ryan Chen Reviewed-by: Philipp Zabel --- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-aspeed.c | 253 +++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 drivers/reset/reset-aspeed.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d85be5899da6..76918f714eff 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -22,6 +22,13 @@ config RESET_A10SR This option enables support for the external reset functions for peripheral PHYs on the Altera Arria10 System Resource Chip. =20 +config RESET_ASPEED + tristate "ASPEED Reset Driver" + depends on ARCH_ASPEED || COMPILE_TEST + select AUXILIARY_BUS + help + This enables the reset controller driver for AST2700. + config RESET_ATH79 bool "AR71xx Reset Driver" if COMPILE_TEST default ATH79 diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 91e6348e3351..3c40a4e44f6b 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -6,6 +6,7 @@ obj-y +=3D starfive/ obj-y +=3D sti/ obj-y +=3D tegra/ obj-$(CONFIG_RESET_A10SR) +=3D reset-a10sr.o +obj-$(CONFIG_RESET_ASPEED) +=3D reset-aspeed.o obj-$(CONFIG_RESET_ATH79) +=3D reset-ath79.o obj-$(CONFIG_RESET_AXS10X) +=3D reset-axs10x.o obj-$(CONFIG_RESET_BCM6345) +=3D reset-bcm6345.o diff --git a/drivers/reset/reset-aspeed.c b/drivers/reset/reset-aspeed.c new file mode 100644 index 000000000000..dd2f860a69d7 --- /dev/null +++ b/drivers/reset/reset-aspeed.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024 ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define SCU0_RESET_CTRL1 0x200 +#define SCU0_RESET_CTRL2 0x220 +#define SCU1_RESET_CTRL1 0x200 +#define SCU1_RESET_CTRL2 0x220 +#define SCU1_PCIE3_CTRL 0x908 + +struct ast2700_reset_signal { + bool dedicated_clr; /* dedicated reset clr offset */ + u32 offset, bit; +}; + +struct aspeed_reset_info { + unsigned int nr_resets; + const struct ast2700_reset_signal *signal; +}; + +struct aspeed_reset { + struct reset_controller_dev rcdev; + struct aspeed_reset_info *info; + spinlock_t lock; /* Protect read-modify-write cycle */ + void __iomem *base; +}; + +static const struct ast2700_reset_signal ast2700_reset0_signals[] =3D { + [SCU0_RESET_SDRAM] =3D { true, SCU0_RESET_CTRL1, BIT(0) }, + [SCU0_RESET_DDRPHY] =3D { true, SCU0_RESET_CTRL1, BIT(1) }, + [SCU0_RESET_RSA] =3D { true, SCU0_RESET_CTRL1, BIT(2) }, + [SCU0_RESET_SHA3] =3D { true, SCU0_RESET_CTRL1, BIT(3) }, + [SCU0_RESET_HACE] =3D { true, SCU0_RESET_CTRL1, BIT(4) }, + [SCU0_RESET_SOC] =3D { true, SCU0_RESET_CTRL1, BIT(5) }, + [SCU0_RESET_VIDEO] =3D { true, SCU0_RESET_CTRL1, BIT(6) }, + [SCU0_RESET_2D] =3D { true, SCU0_RESET_CTRL1, BIT(7) }, + [SCU0_RESET_PCIS] =3D { true, SCU0_RESET_CTRL1, BIT(8) }, + [SCU0_RESET_RVAS0] =3D { true, SCU0_RESET_CTRL1, BIT(9) }, + [SCU0_RESET_RVAS1] =3D { true, SCU0_RESET_CTRL1, BIT(10) }, + [SCU0_RESET_SM3] =3D { true, SCU0_RESET_CTRL1, BIT(11) }, + [SCU0_RESET_SM4] =3D { true, SCU0_RESET_CTRL1, BIT(12) }, + [SCU0_RESET_CRT0] =3D { true, SCU0_RESET_CTRL1, BIT(13) }, + [SCU0_RESET_ECC] =3D { true, SCU0_RESET_CTRL1, BIT(14) }, + [SCU0_RESET_DP_PCI] =3D { true, SCU0_RESET_CTRL1, BIT(15) }, + [SCU0_RESET_UFS] =3D { true, SCU0_RESET_CTRL1, BIT(16) }, + [SCU0_RESET_EMMC] =3D { true, SCU0_RESET_CTRL1, BIT(17) }, + [SCU0_RESET_PCIE1RST] =3D { true, SCU0_RESET_CTRL1, BIT(18) }, + [SCU0_RESET_PCIE1RSTOE] =3D { true, SCU0_RESET_CTRL1, BIT(19) }, + [SCU0_RESET_PCIE0RST] =3D { true, SCU0_RESET_CTRL1, BIT(20) }, + [SCU0_RESET_PCIE0RSTOE] =3D { true, SCU0_RESET_CTRL1, BIT(21) }, + [SCU0_RESET_JTAG] =3D { true, SCU0_RESET_CTRL1, BIT(22) }, + [SCU0_RESET_MCTP0] =3D { true, SCU0_RESET_CTRL1, BIT(23) }, + [SCU0_RESET_MCTP1] =3D { true, SCU0_RESET_CTRL1, BIT(24) }, + [SCU0_RESET_XDMA0] =3D { true, SCU0_RESET_CTRL1, BIT(25) }, + [SCU0_RESET_XDMA1] =3D { true, SCU0_RESET_CTRL1, BIT(26) }, + [SCU0_RESET_H2X1] =3D { true, SCU0_RESET_CTRL1, BIT(27) }, + [SCU0_RESET_DP] =3D { true, SCU0_RESET_CTRL1, BIT(28) }, + [SCU0_RESET_DP_MCU] =3D { true, SCU0_RESET_CTRL1, BIT(29) }, + [SCU0_RESET_SSP] =3D { true, SCU0_RESET_CTRL1, BIT(30) }, + [SCU0_RESET_H2X0] =3D { true, SCU0_RESET_CTRL1, BIT(31) }, + [SCU0_RESET_PORTA_VHUB] =3D { true, SCU0_RESET_CTRL2, BIT(0) }, + [SCU0_RESET_PORTA_PHY3] =3D { true, SCU0_RESET_CTRL2, BIT(1) }, + [SCU0_RESET_PORTA_XHCI] =3D { true, SCU0_RESET_CTRL2, BIT(2) }, + [SCU0_RESET_PORTB_VHUB] =3D { true, SCU0_RESET_CTRL2, BIT(3) }, + [SCU0_RESET_PORTB_PHY3] =3D { true, SCU0_RESET_CTRL2, BIT(4) }, + [SCU0_RESET_PORTB_XHCI] =3D { true, SCU0_RESET_CTRL2, BIT(5) }, + [SCU0_RESET_PORTA_VHUB_EHCI] =3D { true, SCU0_RESET_CTRL2, BIT(6) }, + [SCU0_RESET_PORTB_VHUB_EHCI] =3D { true, SCU0_RESET_CTRL2, BIT(7) }, + [SCU0_RESET_UHCI] =3D { true, SCU0_RESET_CTRL2, BIT(8) }, + [SCU0_RESET_TSP] =3D { true, SCU0_RESET_CTRL2, BIT(9) }, + [SCU0_RESET_E2M0] =3D { true, SCU0_RESET_CTRL2, BIT(10) }, + [SCU0_RESET_E2M1] =3D { true, SCU0_RESET_CTRL2, BIT(11) }, + [SCU0_RESET_VLINK] =3D { true, SCU0_RESET_CTRL2, BIT(12) }, +}; + +static const struct ast2700_reset_signal ast2700_reset1_signals[] =3D { + [SCU1_RESET_LPC0] =3D { true, SCU1_RESET_CTRL1, BIT(0) }, + [SCU1_RESET_LPC1] =3D { true, SCU1_RESET_CTRL1, BIT(1) }, + [SCU1_RESET_MII] =3D { true, SCU1_RESET_CTRL1, BIT(2) }, + [SCU1_RESET_PECI] =3D { true, SCU1_RESET_CTRL1, BIT(3) }, + [SCU1_RESET_PWM] =3D { true, SCU1_RESET_CTRL1, BIT(4) }, + [SCU1_RESET_MAC0] =3D { true, SCU1_RESET_CTRL1, BIT(5) }, + [SCU1_RESET_MAC1] =3D { true, SCU1_RESET_CTRL1, BIT(6) }, + [SCU1_RESET_MAC2] =3D { true, SCU1_RESET_CTRL1, BIT(7) }, + [SCU1_RESET_ADC] =3D { true, SCU1_RESET_CTRL1, BIT(8) }, + [SCU1_RESET_SD] =3D { true, SCU1_RESET_CTRL1, BIT(9) }, + [SCU1_RESET_ESPI0] =3D { true, SCU1_RESET_CTRL1, BIT(10) }, + [SCU1_RESET_ESPI1] =3D { true, SCU1_RESET_CTRL1, BIT(11) }, + [SCU1_RESET_JTAG1] =3D { true, SCU1_RESET_CTRL1, BIT(12) }, + [SCU1_RESET_SPI0] =3D { true, SCU1_RESET_CTRL1, BIT(13) }, + [SCU1_RESET_SPI1] =3D { true, SCU1_RESET_CTRL1, BIT(14) }, + [SCU1_RESET_SPI2] =3D { true, SCU1_RESET_CTRL1, BIT(15) }, + [SCU1_RESET_I3C0] =3D { true, SCU1_RESET_CTRL1, BIT(16) }, + [SCU1_RESET_I3C1] =3D { true, SCU1_RESET_CTRL1, BIT(17) }, + [SCU1_RESET_I3C2] =3D { true, SCU1_RESET_CTRL1, BIT(18) }, + [SCU1_RESET_I3C3] =3D { true, SCU1_RESET_CTRL1, BIT(19) }, + [SCU1_RESET_I3C4] =3D { true, SCU1_RESET_CTRL1, BIT(20) }, + [SCU1_RESET_I3C5] =3D { true, SCU1_RESET_CTRL1, BIT(21) }, + [SCU1_RESET_I3C6] =3D { true, SCU1_RESET_CTRL1, BIT(22) }, + [SCU1_RESET_I3C7] =3D { true, SCU1_RESET_CTRL1, BIT(23) }, + [SCU1_RESET_I3C8] =3D { true, SCU1_RESET_CTRL1, BIT(24) }, + [SCU1_RESET_I3C9] =3D { true, SCU1_RESET_CTRL1, BIT(25) }, + [SCU1_RESET_I3C10] =3D { true, SCU1_RESET_CTRL1, BIT(26) }, + [SCU1_RESET_I3C11] =3D { true, SCU1_RESET_CTRL1, BIT(27) }, + [SCU1_RESET_I3C12] =3D { true, SCU1_RESET_CTRL1, BIT(28) }, + [SCU1_RESET_I3C13] =3D { true, SCU1_RESET_CTRL1, BIT(29) }, + [SCU1_RESET_I3C14] =3D { true, SCU1_RESET_CTRL1, BIT(30) }, + [SCU1_RESET_I3C15] =3D { true, SCU1_RESET_CTRL1, BIT(31) }, + [SCU1_RESET_MCU0] =3D { true, SCU1_RESET_CTRL2, BIT(0) }, + [SCU1_RESET_MCU1] =3D { true, SCU1_RESET_CTRL2, BIT(1) }, + [SCU1_RESET_H2A_SPI1] =3D { true, SCU1_RESET_CTRL2, BIT(2) }, + [SCU1_RESET_H2A_SPI2] =3D { true, SCU1_RESET_CTRL2, BIT(3) }, + [SCU1_RESET_UART0] =3D { true, SCU1_RESET_CTRL2, BIT(4) }, + [SCU1_RESET_UART1] =3D { true, SCU1_RESET_CTRL2, BIT(5) }, + [SCU1_RESET_UART2] =3D { true, SCU1_RESET_CTRL2, BIT(6) }, + [SCU1_RESET_UART3] =3D { true, SCU1_RESET_CTRL2, BIT(7) }, + [SCU1_RESET_I2C_FILTER] =3D { true, SCU1_RESET_CTRL2, BIT(8) }, + [SCU1_RESET_CALIPTRA] =3D { true, SCU1_RESET_CTRL2, BIT(9) }, + [SCU1_RESET_XDMA] =3D { true, SCU1_RESET_CTRL2, BIT(10) }, + [SCU1_RESET_FSI] =3D { true, SCU1_RESET_CTRL2, BIT(12) }, + [SCU1_RESET_CAN] =3D { true, SCU1_RESET_CTRL2, BIT(13) }, + [SCU1_RESET_MCTP] =3D { true, SCU1_RESET_CTRL2, BIT(14) }, + [SCU1_RESET_I2C] =3D { true, SCU1_RESET_CTRL2, BIT(15) }, + [SCU1_RESET_UART6] =3D { true, SCU1_RESET_CTRL2, BIT(16) }, + [SCU1_RESET_UART7] =3D { true, SCU1_RESET_CTRL2, BIT(17) }, + [SCU1_RESET_UART8] =3D { true, SCU1_RESET_CTRL2, BIT(18) }, + [SCU1_RESET_UART9] =3D { true, SCU1_RESET_CTRL2, BIT(19) }, + [SCU1_RESET_LTPI0] =3D { true, SCU1_RESET_CTRL2, BIT(20) }, + [SCU1_RESET_VGAL] =3D { true, SCU1_RESET_CTRL2, BIT(21) }, + [SCU1_RESET_LTPI1] =3D { true, SCU1_RESET_CTRL2, BIT(22) }, + [SCU1_RESET_ACE] =3D { true, SCU1_RESET_CTRL2, BIT(23) }, + [SCU1_RESET_E2M] =3D { true, SCU1_RESET_CTRL2, BIT(24) }, + [SCU1_RESET_UHCI] =3D { true, SCU1_RESET_CTRL2, BIT(25) }, + [SCU1_RESET_PORTC_USB2UART] =3D { true, SCU1_RESET_CTRL2, BIT(26) }, + [SCU1_RESET_PORTC_VHUB_EHCI] =3D { true, SCU1_RESET_CTRL2, BIT(27) }, + [SCU1_RESET_PORTD_USB2UART] =3D { true, SCU1_RESET_CTRL2, BIT(28) }, + [SCU1_RESET_PORTD_VHUB_EHCI] =3D { true, SCU1_RESET_CTRL2, BIT(29) }, + [SCU1_RESET_H2X] =3D { true, SCU1_RESET_CTRL2, BIT(30) }, + [SCU1_RESET_I3CDMA] =3D { true, SCU1_RESET_CTRL2, BIT(31) }, + [SCU1_RESET_PCIE2RST] =3D { false, SCU1_PCIE3_CTRL, BIT(0) }, +}; + +static inline struct aspeed_reset *to_aspeed_reset(struct reset_controller= _dev *rcdev) +{ + return container_of(rcdev, struct aspeed_reset, rcdev); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, unsigne= d long id) +{ + struct aspeed_reset *rc =3D to_aspeed_reset(rcdev); + void __iomem *reg_offset =3D rc->base + rc->info->signal[id].offset; + + if (rc->info->signal[id].dedicated_clr) { + writel(rc->info->signal[id].bit, reg_offset); + } else { + guard(spinlock_irqsave)(&rc->lock); + writel(readl(reg_offset) & ~rc->info->signal[id].bit, reg_offset); + } + + return 0; +} + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, unsig= ned long id) +{ + struct aspeed_reset *rc =3D to_aspeed_reset(rcdev); + void __iomem *reg_offset =3D rc->base + rc->info->signal[id].offset; + + if (rc->info->signal[id].dedicated_clr) { + writel(rc->info->signal[id].bit, reg_offset + 0x04); + } else { + guard(spinlock_irqsave)(&rc->lock); + writel(readl(reg_offset) | rc->info->signal[id].bit, reg_offset); + } + + return 0; +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, unsigne= d long id) +{ + struct aspeed_reset *rc =3D to_aspeed_reset(rcdev); + void __iomem *reg_offset =3D rc->base + rc->info->signal[id].offset; + + return (readl(reg_offset) & rc->info->signal[id].bit) ? 1 : 0; +} + +static const struct reset_control_ops aspeed_reset_ops =3D { + .assert =3D aspeed_reset_assert, + .deassert =3D aspeed_reset_deassert, + .status =3D aspeed_reset_status, +}; + +static int aspeed_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct aspeed_reset *reset; + struct device *dev =3D &adev->dev; + + reset =3D devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + spin_lock_init(&reset->lock); + + reset->info =3D (struct aspeed_reset_info *)id->driver_data; + reset->rcdev.owner =3D THIS_MODULE; + reset->rcdev.nr_resets =3D reset->info->nr_resets; + reset->rcdev.ops =3D &aspeed_reset_ops; + reset->rcdev.of_node =3D dev->parent->of_node; + reset->rcdev.dev =3D dev; + reset->rcdev.of_reset_n_cells =3D 1; + reset->base =3D (void __iomem *)adev->dev.platform_data; + + return devm_reset_controller_register(dev, &reset->rcdev); +} + +static const struct aspeed_reset_info ast2700_reset0_info =3D { + .nr_resets =3D ARRAY_SIZE(ast2700_reset0_signals), + .signal =3D ast2700_reset0_signals, +}; + +static const struct aspeed_reset_info ast2700_reset1_info =3D { + .nr_resets =3D ARRAY_SIZE(ast2700_reset1_signals), + .signal =3D ast2700_reset1_signals, +}; + +static const struct auxiliary_device_id aspeed_reset_ids[] =3D { + { .name =3D "clk_ast2700.reset0", .driver_data =3D (kernel_ulong_t)&ast27= 00_reset0_info }, + { .name =3D "clk_ast2700.reset1", .driver_data =3D (kernel_ulong_t)&ast27= 00_reset1_info }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, aspeed_reset_ids); + +static struct auxiliary_driver aspeed_reset_driver =3D { + .probe =3D aspeed_reset_probe, + .id_table =3D aspeed_reset_ids, +}; + +module_auxiliary_driver(aspeed_reset_driver); + +MODULE_AUTHOR("Ryan Chen "); +MODULE_DESCRIPTION("ASPEED SoC Reset Controller Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1