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Sun, 06 Jul 2025 23:19:12 -0700 (PDT) From: Jun Nie Date: Mon, 07 Jul 2025 14:18:05 +0800 Subject: [PATCH v12 10/12] drm/msm/dpu: support SSPP assignment for quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250707-v6-16-rc2-quad-pipe-upstream-v12-10-67e3721e7d83@linaro.org> References: <20250707-v6-16-rc2-quad-pipe-upstream-v12-0-67e3721e7d83@linaro.org> In-Reply-To: <20250707-v6-16-rc2-quad-pipe-upstream-v12-0-67e3721e7d83@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751869084; l=8448; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=ap+2nA3vCpiUHkKg9Lzcj2185wHlDPqznO6jDAEkMDg=; b=WdjAtTQ/uEqcUgnvz4I9409D0A7XE7RG/DditYh1d3IOwvSIkG95L/eVetDcAR+JQKJXuYmPc 7ftE8nLspCUA/w0l5/ZyutRuvx/QN7jdcRHqA3YXiMRzcKfFMhwZfQ8 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, SSPPs are assigned to a maximum of two pipes. However, quad-pipe usage scenarios require four pipes and involve configuring two stages. In quad-pipe case, the first two pipes share a set of mixer configurations and enable multi-rect mode when certain conditions are met. The same applies to the subsequent two pipes. Assign SSPPs to the pipes in each stage using a unified method and to loop the stages accordingly. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 143 +++++++++++++++++++-------= ---- 1 file changed, 89 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 149e7066480b07f9f6d422748d89ffd6f9416f33..ecfebf7a2406d65930075cc2a4b= 8a8a7d40b3d3c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -954,6 +954,30 @@ static int dpu_plane_is_multirect_parallel_capable(str= uct dpu_hw_sspp *sspp, dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth); } =20 +static bool dpu_plane_get_single_pipe(struct dpu_plane_state *pstate, + struct dpu_sw_pipe **single_pipe, + struct dpu_sw_pipe_cfg **single_pipe_cfg, + int *stage_index) +{ + int stage_idx, pipe_idx, i, valid_pipe =3D 0; + + for (stage_idx =3D 0; stage_idx < STAGES_PER_PLANE; stage_idx++) { + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe_idx =3D stage_idx * PIPES_PER_STAGE + i; + if (drm_rect_width(&pstate->pipe_cfg[pipe_idx].src_rect) !=3D 0) { + valid_pipe++; + if (valid_pipe > 1) + return false; + + *single_pipe =3D &pstate->pipe[pipe_idx]; + *single_pipe_cfg =3D &pstate->pipe_cfg[pipe_idx]; + *stage_index =3D stage_idx; + } + } + } + + return valid_pipe =3D=3D 1; +} =20 static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, struct drm_atomic_state *state, @@ -1021,18 +1045,23 @@ static int dpu_plane_try_multirect_shared(struct dp= u_plane_state *pstate, const struct msm_format *fmt, uint32_t max_linewidth) { - struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; - struct dpu_sw_pipe *prev_pipe =3D &prev_adjacent_pstate->pipe[0]; - struct dpu_sw_pipe_cfg *prev_pipe_cfg =3D &prev_adjacent_pstate->pipe_cfg= [0]; + struct dpu_sw_pipe *pipe, *prev_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg, *prev_pipe_cfg; const struct msm_format *prev_fmt =3D msm_framebuffer_format(prev_adjacen= t_pstate->base.fb); + int stage_index, prev_stage_index; u16 max_tile_height =3D 1; =20 - if (prev_adjacent_pstate->pipe[1].sspp !=3D NULL || + if (!dpu_plane_get_single_pipe(pstate, &pipe, &pipe_cfg, &stage_index)) + return false; + + if (!dpu_plane_get_single_pipe(prev_adjacent_pstate, &prev_pipe, + &prev_pipe_cfg, &prev_stage_index) || prev_pipe->multirect_mode !=3D DPU_SSPP_MULTIRECT_NONE) return false; =20 + if (stage_index !=3D prev_stage_index) + return false; + if (!dpu_plane_is_multirect_capable(pipe->sspp, pipe_cfg, fmt) || !dpu_plane_is_multirect_capable(prev_pipe->sspp, prev_pipe_cfg, prev_= fmt)) return false; @@ -1043,11 +1072,6 @@ static int dpu_plane_try_multirect_shared(struct dpu= _plane_state *pstate, if (MSM_FORMAT_IS_UBWC(prev_fmt)) max_tile_height =3D max(max_tile_height, prev_fmt->tile_height); =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->sspp =3D NULL; - if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) && dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth)= && (pipe_cfg->dst_rect.x1 >=3D prev_pipe_cfg->dst_rect.x2 || @@ -1176,6 +1200,44 @@ static int dpu_plane_virtual_atomic_check(struct drm= _plane *plane, return 0; } =20 +static int dpu_plane_assign_resource_in_stage(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + struct drm_plane_state *plane_state, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs) +{ + struct drm_plane *plane =3D plane_state->plane; + struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + struct dpu_sw_pipe *r_pipe =3D pipe + 1; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D pipe_cfg + 1; + + if (drm_rect_width(&pipe_cfg->src_rect) !=3D 0) { + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, req= s); + if (!pipe->sspp) + return -ENODEV; + } + + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0 && + dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, + pipe->sspp, + msm_framebuffer_format(plane_state->fb), + dpu_kms->catalog->caps->max_linewidth)) { + goto stage_assinged; + } + + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { + r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, r= eqs); + if (!r_pipe->sspp) + return -ENODEV; + r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + } + +stage_assinged: + return 0; +} + static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_global_state *global_state, struct drm_atomic_state *state, @@ -1188,11 +1250,9 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, struct dpu_rm_sspp_requirements reqs; struct dpu_plane_state *pstate, *prev_adjacent_pstate; struct dpu_sw_pipe *pipe; - struct dpu_sw_pipe *r_pipe; struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; - int i; + int i, stage_id, ret; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1202,11 +1262,6 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, prev_adjacent_pstate =3D prev_adjacent_plane_state ? to_dpu_plane_state(prev_adjacent_plane_state) : NULL; =20 - pipe =3D &pstate->pipe[0]; - r_pipe =3D &pstate->pipe[1]; - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 @@ -1220,44 +1275,24 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 reqs.rot90 =3D drm_rotation_90_or_270(plane_state->rotation); =20 - if (drm_rect_width(&r_pipe_cfg->src_rect) =3D=3D 0) { - if (!prev_adjacent_pstate || - !dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt, - dpu_kms->catalog->caps->max_linewidth)) { - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &r= eqs); - if (!pipe->sspp) - return -ENODEV; - - r_pipe->sspp =3D NULL; - - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - } - } else { - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &re= qs); - if (!pipe->sspp) - return -ENODEV; - - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, - pipe->sspp, - msm_framebuffer_format(plane_state->fb), - dpu_kms->catalog->caps->max_linewidth)) { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, = &reqs); - if (!r_pipe->sspp) - return -ENODEV; - - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + if (prev_adjacent_pstate && + dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt, + dpu_kms->catalog->caps->max_linewidth)) { + goto assigned; + } =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - } + for (stage_id =3D 0; stage_id < STAGES_PER_PLANE; stage_id++) { + pipe =3D &pstate->pipe[stage_id * PIPES_PER_STAGE]; + pipe_cfg =3D &pstate->pipe_cfg[stage_id * PIPES_PER_STAGE]; + ret =3D dpu_plane_assign_resource_in_stage(pipe, pipe_cfg, + plane_state, + global_state, + crtc, &reqs); + if (ret) + return ret; } =20 +assigned: return dpu_plane_atomic_check_sspp(plane, state, crtc_state); } =20 --=20 2.34.1