From nobody Tue Oct 7 22:58:36 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89F9B1EB1AF; Sun, 6 Jul 2025 18:27:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751826470; cv=none; b=lppIutCDT837tMWq4rhLECTeI+RmCrcL2TVJtQ3btx3e+jR3SdzYDHeUZYWOCOshhS2G4/ep6g8VY0aHtqjwHHt/QR5KxBSafmpaJ4NJax2dbMdPTL9yc9rGxf1vl+OYy/zI0ikKZFDA7Qxf6TR2PaoM0KPUNJDT9JuXouDoJ3o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751826470; c=relaxed/simple; bh=uRAQPW/XAX0Tqz1bC3rL04fGoa2FbtZRBUYo1jwG2sk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u4axR2kegPTIJt/BiXD827swf0+eTSMz7uLtxB96XIDuKVRy2Z0oQVKug/q4OmercV/oWvCXxHgS0skSeECm/4nHZ1z6YdN0tmKYikH09jRhFxvjzHR6qlh+bt/IYOTpHvUQOu+ub5M9RqM7/ii9mAEYCrNe4FazgyLID67FKy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ikDWFnrR; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ikDWFnrR" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id E01EA25B63; Sun, 6 Jul 2025 20:27:46 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id fW7Epcihj-kx; Sun, 6 Jul 2025 20:27:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1751826465; bh=uRAQPW/XAX0Tqz1bC3rL04fGoa2FbtZRBUYo1jwG2sk=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ikDWFnrRp9CZp9CSxDIqSl8wrdd+p32unXN9XSr8Hs2/+BERwhUU2Y6HgqNac+xIS GDG/SCVXCSgD85Pk2MTE189VpvDyB84h5F1dbz9AOdG79RuLVD+AIWAEkAzYKO5XqV xB3z6brS7GfJ+iG9uNpc7mhOgMeEt6Ta5wpcciTdfakr0T+FGg5PgWTpX99xzrX7oS PHafCYawRI/UvYzDfryfbFfmmvEXwMd1p6SryHNyD/BEdFsWPVsaz5JeezTsLOkEwW J9xCjL31xshQ8nh6Hcjmr25b4GM+nfV2SD5SJ/01HBD9lcHuE+V+DpVnfRqla9NGQU 2i1RZiv8/cc3A== From: Kaustabh Chakraborty Date: Sun, 06 Jul 2025 23:55:44 +0530 Subject: [PATCH v3 10/13] drm/bridge: samsung-dsim: add ability to define clock names for every variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250706-exynos7870-dsim-v3-10-9879fb9a644d@disroot.org> References: <20250706-exynos7870-dsim-v3-0-9879fb9a644d@disroot.org> In-Reply-To: <20250706-exynos7870-dsim-v3-0-9879fb9a644d@disroot.org> To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Seung-Woo Kim , Kyungmin Park , Krzysztof Kozlowski , Alim Akhtar Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Kaustabh Chakraborty X-Developer-Signature: v=1; a=ed25519-sha256; t=1751826342; l=8008; i=kauschluss@disroot.org; s=20250202; h=from:subject:message-id; bh=uRAQPW/XAX0Tqz1bC3rL04fGoa2FbtZRBUYo1jwG2sk=; b=qlKkcdPw+G+E3adxMetLXhT8Xm4F1vFtKcC0Migri0bTuR/EVz9jrKq0lOz87UCkFevXsE0PS NVtebD/ujinAdhvjwvA114/bcoRI0Se6tGZQ7/N670vgO1pn60p5d63 X-Developer-Key: i=kauschluss@disroot.org; a=ed25519; pk=h2xeR+V2I1+GrfDPAhZa3M+NWA0Cnbdkkq1bH3ct1hE= Presently, all devices refer to clock names from a single array. The only controlling parameter is the number of clocks (num_clks field of samsung_dsim_driver_data) which uses the first n clocks of that array. As new devices are added, this approach turns out to be cumbersome. Separate the clock names in individual arrays required by each variant, in a struct clk_bulk_data. Add a pointer field to the driver data struct which points to their respective clock names, and rework the clock usage code to use the clk_bulk_* API instead. Signed-off-by: Kaustabh Chakraborty --- drivers/gpu/drm/bridge/samsung-dsim.c | 88 +++++++++++++++++--------------= ---- include/drm/bridge/samsung-dsim.h | 2 +- 2 files changed, 44 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 4b49707730db76aa8fd3ab973b02507436750889..b6b3bbcbd0f438e5e1d3faf18f8= c2d532a4ecc93 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -219,23 +219,31 @@ #define DSI_XFER_TIMEOUT_MS 100 #define DSI_RX_FIFO_EMPTY 0x30800002 =20 -#define OLD_SCLK_MIPI_CLK_NAME "pll_clk" - #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000= 000000ULL) =20 -static const char *const clk_names[5] =3D { - "bus_clk", - "sclk_mipi", - "phyclk_mipidphy0_bitclkdiv8", - "phyclk_mipidphy0_rxclkesc0", - "sclk_rgb_vclk_to_dsim0" -}; - enum samsung_dsim_transfer_type { EXYNOS_DSI_TX, EXYNOS_DSI_RX, }; =20 +static struct clk_bulk_data exynos3_clk_bulk_data[] =3D { + { .id =3D "bus_clk" }, + { .id =3D "pll_clk" }, +}; + +static struct clk_bulk_data exynos4_clk_bulk_data[] =3D { + { .id =3D "bus_clk" }, + { .id =3D "sclk_mipi" }, +}; + +static struct clk_bulk_data exynos5433_clk_bulk_data[] =3D { + { .id =3D "bus_clk" }, + { .id =3D "sclk_mipi" }, + { .id =3D "phyclk_mipidphy0_bitclkdiv8" }, + { .id =3D "phyclk_mipidphy0_rxclkesc0" }, + { .id =3D "sclk_rgb_vclk_to_dsim0" }, +}; + enum reg_idx { DSIM_STATUS_REG, /* Status register (legacy) */ DSIM_LINK_STATUS_REG, /* Link status register */ @@ -408,7 +416,8 @@ static const struct samsung_dsim_driver_data exynos3_ds= i_driver_data =3D { .has_legacy_status_reg =3D 1, .has_freqband =3D 1, .has_clklane_stop =3D 1, - .num_clks =3D 2, + .clk_data =3D exynos3_clk_bulk_data, + .num_clks =3D ARRAY_SIZE(exynos3_clk_bulk_data), .max_freq =3D 1000, .wait_for_hdr_fifo =3D 1, .wait_for_reset =3D 1, @@ -439,7 +448,8 @@ static const struct samsung_dsim_driver_data exynos4_ds= i_driver_data =3D { .has_legacy_status_reg =3D 1, .has_freqband =3D 1, .has_clklane_stop =3D 1, - .num_clks =3D 2, + .clk_data =3D exynos4_clk_bulk_data, + .num_clks =3D ARRAY_SIZE(exynos4_clk_bulk_data), .max_freq =3D 1000, .wait_for_hdr_fifo =3D 1, .wait_for_reset =3D 1, @@ -468,7 +478,8 @@ static const struct samsung_dsim_driver_data exynos5_ds= i_driver_data =3D { .reg_ofs =3D exynos_reg_ofs, .plltmr_reg =3D 0x58, .has_legacy_status_reg =3D 1, - .num_clks =3D 2, + .clk_data =3D exynos3_clk_bulk_data, + .num_clks =3D ARRAY_SIZE(exynos3_clk_bulk_data), .max_freq =3D 1000, .wait_for_hdr_fifo =3D 1, .wait_for_reset =3D 1, @@ -497,7 +508,8 @@ static const struct samsung_dsim_driver_data exynos5433= _dsi_driver_data =3D { .plltmr_reg =3D 0xa0, .has_legacy_status_reg =3D 1, .has_clklane_stop =3D 1, - .num_clks =3D 5, + .clk_data =3D exynos5433_clk_bulk_data, + .num_clks =3D ARRAY_SIZE(exynos5433_clk_bulk_data), .max_freq =3D 1500, .wait_for_hdr_fifo =3D 1, .wait_for_reset =3D 0, @@ -526,7 +538,8 @@ static const struct samsung_dsim_driver_data exynos5422= _dsi_driver_data =3D { .plltmr_reg =3D 0xa0, .has_legacy_status_reg =3D 1, .has_clklane_stop =3D 1, - .num_clks =3D 2, + .clk_data =3D exynos3_clk_bulk_data, + .num_clks =3D ARRAY_SIZE(exynos3_clk_bulk_data), .max_freq =3D 1500, .wait_for_hdr_fifo =3D 1, .wait_for_reset =3D 1, @@ -555,7 +568,8 @@ static const struct samsung_dsim_driver_data imx8mm_dsi= _driver_data =3D { .plltmr_reg =3D 0xa0, .has_legacy_status_reg =3D 1, .has_clklane_stop =3D 1, - .num_clks =3D 2, + .clk_data =3D exynos4_clk_bulk_data, + .num_clks =3D ARRAY_SIZE(exynos4_clk_bulk_data), .max_freq =3D 2100, .wait_for_hdr_fifo =3D 1, .wait_for_reset =3D 0, @@ -2021,7 +2035,7 @@ int samsung_dsim_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct samsung_dsim *dsi; - int ret, i; + int ret; =20 dsi =3D devm_drm_bridge_alloc(dev, struct samsung_dsim, bridge, &samsung_= dsim_bridge_funcs); if (IS_ERR(dsi)) @@ -2045,23 +2059,11 @@ int samsung_dsim_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to get regulators\n"); =20 - dsi->clks =3D devm_kcalloc(dev, dsi->driver_data->num_clks, - sizeof(*dsi->clks), GFP_KERNEL); - if (!dsi->clks) - return -ENOMEM; - - for (i =3D 0; i < dsi->driver_data->num_clks; i++) { - dsi->clks[i] =3D devm_clk_get(dev, clk_names[i]); - if (IS_ERR(dsi->clks[i])) { - if (strcmp(clk_names[i], "sclk_mipi") =3D=3D 0) { - dsi->clks[i] =3D devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME); - if (!IS_ERR(dsi->clks[i])) - continue; - } - - dev_info(dev, "failed to get the clock: %s\n", clk_names[i]); - return PTR_ERR(dsi->clks[i]); - } + ret =3D devm_clk_bulk_get(dev, dsi->driver_data->num_clks, + dsi->driver_data->clk_data); + if (ret) { + dev_err(dev, "failed to get clocks in bulk (%d)\n", ret); + return ret; } =20 dsi->reg_base =3D devm_platform_ioremap_resource(pdev, 0); @@ -2134,7 +2136,7 @@ static int samsung_dsim_suspend(struct device *dev) { struct samsung_dsim *dsi =3D dev_get_drvdata(dev); const struct samsung_dsim_driver_data *driver_data =3D dsi->driver_data; - int ret, i; + int ret; =20 usleep_range(10000, 20000); =20 @@ -2150,8 +2152,7 @@ static int samsung_dsim_suspend(struct device *dev) =20 phy_power_off(dsi->phy); =20 - for (i =3D driver_data->num_clks - 1; i > -1; i--) - clk_disable_unprepare(dsi->clks[i]); + clk_bulk_disable_unprepare(driver_data->num_clks, driver_data->clk_data); =20 ret =3D regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); if (ret < 0) @@ -2164,7 +2165,7 @@ static int samsung_dsim_resume(struct device *dev) { struct samsung_dsim *dsi =3D dev_get_drvdata(dev); const struct samsung_dsim_driver_data *driver_data =3D dsi->driver_data; - int ret, i; + int ret; =20 ret =3D regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); if (ret < 0) { @@ -2172,11 +2173,9 @@ static int samsung_dsim_resume(struct device *dev) return ret; } =20 - for (i =3D 0; i < driver_data->num_clks; i++) { - ret =3D clk_prepare_enable(dsi->clks[i]); - if (ret < 0) - goto err_clk; - } + ret =3D clk_bulk_prepare_enable(driver_data->num_clks, driver_data->clk_d= ata); + if (ret < 0) + goto err_clk; =20 ret =3D phy_power_on(dsi->phy); if (ret < 0) { @@ -2187,8 +2186,7 @@ static int samsung_dsim_resume(struct device *dev) return 0; =20 err_clk: - while (--i > -1) - clk_disable_unprepare(dsi->clks[i]); + clk_bulk_disable_unprepare(driver_data->num_clks, driver_data->clk_data); regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); =20 return ret; diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index 04ed11787bbd22503f7221cad1a491a4e5e66781..eb9fdbab1b34074923daa0aa044= 3c33c5b99ae42 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -58,6 +58,7 @@ struct samsung_dsim_driver_data { unsigned int has_clklane_stop:1; unsigned int has_broken_fifoctrl_emptyhdr:1; unsigned int has_sfrctrl:1; + struct clk_bulk_data *clk_data; unsigned int num_clks; unsigned int min_freq; unsigned int max_freq; @@ -104,7 +105,6 @@ struct samsung_dsim { =20 void __iomem *reg_base; struct phy *phy; - struct clk **clks; struct clk *pll_clk; struct regulator_bulk_data supplies[2]; int irq; --=20 2.49.0