From nobody Tue Oct 7 21:29:00 2025 Received: from smtpout1.mo534.mail-out.ovh.net (smtpout1.mo534.mail-out.ovh.net [51.210.94.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EDE517A5BE for ; Sat, 5 Jul 2025 23:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=51.210.94.140 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751758762; cv=none; b=RPpqW2VJYbwjBf+SJyU428KjfZfSWlsXqrqcBgUUfFMWUlYLQHEV/erPG4eSiR/vbMhYBjNu3pc4fOY5nvRfyfe0dKFX40omLrAVk1lEGPEjMivOehamooIWP0OcVAZ/uw2IdYQg/SDJDbhycjgTNRdBTaLOZolo9a273+0jhus= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751758762; c=relaxed/simple; bh=mOs+XewepzXvG+nOgkKT9IVP0KnAjus+b4UwbPplEhE=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=VfMxClZLHCt6YMoM/A179ggQzjOJznOlslZHL+RUoRQGIe9qRqG4Xb++3lRC968kBR4g07h5aGepIZ3+qS6MyzZyysI7EyWemOGhv70I90EOBYsAWhkWJOlBA5qWEduTxqnmDC4WwLMLl8AAgePgN9vA4Zit1u5vlEDWiK8BDRw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=orca.pet; spf=pass smtp.mailfrom=orca.pet; arc=none smtp.client-ip=51.210.94.140 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=orca.pet Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=orca.pet Received: from director3.derp.mail-out.ovh.net (director3.derp.mail-out.ovh.net [152.228.215.222]) by mo534.mail-out.ovh.net (Postfix) with ESMTPS id 4bZRcp57x5z6CM3; Sat, 5 Jul 2025 23:32:42 +0000 (UTC) Received: from director3.derp.mail-out.ovh.net (director3.derp.mail-out.ovh.net. [127.0.0.1]) by director3.derp.mail-out.ovh.net (inspect_sender_mail_agent) with SMTP for ; Sat, 5 Jul 2025 23:32:42 +0000 (UTC) Received: from mta10.priv.ovhmail-u1.ea.mail.ovh.net (unknown [10.110.188.134]) by director3.derp.mail-out.ovh.net (Postfix) with ESMTPS id 4bZRcp3r0Tz5wFR; Sat, 5 Jul 2025 23:32:42 +0000 (UTC) Received: from orca.pet (unknown [10.1.6.6]) by mta10.priv.ovhmail-u1.ea.mail.ovh.net (Postfix) with ESMTPSA id 04055DA3D52; Sat, 5 Jul 2025 23:32:41 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-102R004e742e852-2cb6-4def-8a10-6135a02faf00, 6309C3B5282082938C1B0D62F70632481A582291) smtp.auth=marcos@orca.pet X-OVh-ClientIp: 147.156.42.5 From: Marcos Del Sol Vives To: linux-kernel@vger.kernel.org Cc: marcos@orca.pet, Bjorn Helgaas , linux-pci@vger.kernel.org Subject: [PATCH] pci: disable MSI on RDC PCI to PCI-E bridges Date: Sun, 6 Jul 2025 01:32:08 +0200 Message-Id: <20250705233209.721507-1-marcos@orca.pet> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 13121800464492353126 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgddvjeefjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffoggfgsedtkeertdertddtnecuhfhrohhmpeforghrtghoshcuffgvlhcuufholhcugghivhgvshcuoehmrghrtghoshesohhrtggrrdhpvghtqeenucggtffrrghtthgvrhhnpefghffgfeevgffhteevvefghfelffejvdejkeeijeegieduvdffteeijeejjefggeenucfkphepuddvjedrtddrtddruddpudegjedrudehiedrgedvrdehnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepuddvjedrtddrtddruddpmhgrihhlfhhrohhmpehmrghrtghoshesohhrtggrrdhpvghtpdhnsggprhgtphhtthhopeegpdhrtghpthhtohepsghhvghlghgrrghssehgohhoghhlvgdrtghomhdprhgtphhtthhopehmrghrtghoshesohhrtggrrdhpvghtpdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhugidqphgtihesvhhgvghrrdhkvghrnhgvlhdrohhrghdpoffvtefjohhsthepmhhoheefgegmpdhmohguvgepshhmthhpohhuth Content-Type: text/plain; charset="utf-8" These bridges, present on Vortex86DX3 and Vortex86EX2 SoCs, do not support MSIs. If enabled, interrupts generated by PCI-E devices never reach the processor. I have contacted the manufacturer (DM&P) and they confirmed that PCI MSIs need to be disabled for them. Signed-off-by: Marcos Del Sol Vives --- drivers/pci/quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d7f4ee634263..f610ea45ca9e 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2715,6 +2715,7 @@ static void quirk_disable_msi(struct pci_dev *dev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, = quirk_disable_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); =20 /* * The APC bridge device in AMD 780 family northbridges has some random --=20 2.34.1