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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384c0558sm526274e87.209.2025.07.05.03.02.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jul 2025 03:02:47 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 05 Jul 2025 13:02:35 +0300 Subject: [PATCH v4 10/10] drm/msm: enable separate binding of GPU and display devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250705-msm-gpu-split-v4-10-fb470c481131@oss.qualcomm.com> References: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> In-Reply-To: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5219; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=fG270cxV/2q7kQa6T4r/dHwrEGN9NSQeGPoJADDDa3w=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoaPg0D8TLyxpxyMP5ZOm6f/GyJWsJzX6ZcuA4r FCYCYgTH++JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaGj4NAAKCRCLPIo+Aiko 1QvtB/0f5DxO5BvqdVoPXZaDjS6R3QfljCGAuivAD4aP8SahrZOkfS8yC5L+862G61Kl1A0QwoZ pOocaIuIDTdq3a2U7PP1gDB79IUrNh+Jj5YkWOqE0q2d+jiaVlcdhySbrYhXm3Nfwwbw79DKeBg r8J2pylstkUlBHQtdm2Z+0gLbp2cNQEISwi9xHI3cO8f6KVtAmYoPgbSJclsfyHnk65kB2qUo1K WVd+P+dJJgmrk/YI9ID0FrmiBvXoputJ5iXF0V75jZ6KK9QtWOGFiNml93xgpea+j8Xk/JkzaZd f/1Uz7I8ICTvR7k6pPB2lA5Vjf6xSTcKP41+AHWcspLFx+0k X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA1MDA2NCBTYWx0ZWRfX/sF92FPIgZVK uE7mnA8u5/9wPr6KWBRw34y38d1nckLYnwjSfmi3LHXltmyQthG+xnWhaBlj9j342nN13x86stn ES4IbVy0biaFXa7Cv1sBdYCEBh/MQUSOrP8bgs77CeBp9fmR04VZqd1F9g/jEh7pdzYpa8BZ9nF 78rSA4tDC9RZwrwxndeZpILyvwwcxbzhjwaM+2ZYRrQnTSyG3pcGGvhhXjTVtpFm+xhe9C4hk+d nfpNcCv+OzaPIaDBj6vWjoMtYQzuZhtJQPGbRbWyp6Ldnc+tJZ+uYntSMIT4BofbOPLIy1kyHze aMj0p52KMSb6e3TocKzP94dkQowdgh9Fz34IeWUlWwo0hxlEzxAZmsiJRmeEXAsj1aC7KBVaEIc SeSOO18eMxKkQrH5Tle6JDnSrxoz92km5EA3BO7tG47h4Gza6k/dhl7p2s9lyYp4F/X6xgEo X-Authority-Analysis: v=2.4 cv=dciA3WXe c=1 sm=1 tr=0 ts=6868f84a cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=d3EbUlffPpwbv2rupc8A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: mVHgRqlullSjfvm6IOlKDp-_hXftw5Lu X-Proofpoint-ORIG-GUID: mVHgRqlullSjfvm6IOlKDp-_hXftw5Lu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_07,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507050064 There are cases when we want to have separate DRM devices for GPU and display pipelines. One example is development, when it is beneficial to be able to bind the GPU driver separately, without the display pipeline (and without the hacks adding "amd,imageon" to the compatible string). Another example is some of Qualcomm platforms, which have two MDSS units, but only one GPU. With current approach it is next to impossible to support this usecase properly, while separate binding allows users to have three DRM devices: two for MDSS units and a single headless GPU. Add kernel param msm.separate_gpu_drm, which if set to true forces creation of separate display and GPU DRM devices. Mesa supports this setup by using the kmsro wrapper. The param is disabled by default, in order to be able to test userspace for the compatibility issues. Simple clients are able to handle this setup automatically. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +- drivers/gpu/drm/msm/msm_drv.c | 47 ++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 47 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 99c8d2f4e4b49fda912fa49429399cf207eccead..50945bfe9b4992118f23db3cd17= ac348be9f9c9d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -262,7 +262,8 @@ static const struct component_ops a3xx_ops =3D { =20 static int adreno_probe(struct platform_device *pdev) { - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) + if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || + msm_gpu_no_components()) return msm_gpu_probe(pdev, &a3xx_ops); =20 return component_add(&pdev->dev, &a3xx_ops); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 0ab005a7d5e99e46fe47c9e64514434416898d20..2966ba086b2cdb3232a7fa0445b= 953787cfad2b0 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -54,9 +54,18 @@ static bool modeset =3D true; MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=3Don (default),= 0=3Ddisable)"); module_param(modeset, bool, 0600); =20 +static bool separate_gpu_drm; +MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0= =3Dsingle DRM device for both GPU and display (default), 1=3Dtwo DRM device= s)"); +module_param(separate_gpu_drm, bool, 0400); + DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); =20 +bool msm_gpu_no_components(void) +{ + return separate_gpu_drm; +} + static int msm_drm_uninit(struct device *dev, const struct component_ops *= gpu_ops) { struct platform_device *pdev =3D to_platform_device(dev); @@ -836,6 +845,30 @@ static const struct drm_driver msm_driver =3D { .patchlevel =3D MSM_VERSION_PATCHLEVEL, }; =20 +static const struct drm_driver msm_kms_driver =3D { + .driver_features =3D DRIVER_GEM | + DRIVER_ATOMIC | + DRIVER_MODESET, + .open =3D msm_open, + .postclose =3D msm_postclose, + .dumb_create =3D msm_gem_dumb_create, + .dumb_map_offset =3D msm_gem_dumb_map_offset, + .gem_prime_import_sg_table =3D msm_gem_prime_import_sg_table, +#ifdef CONFIG_DEBUG_FS + .debugfs_init =3D msm_debugfs_init, +#endif + MSM_FBDEV_DRIVER_OPS, + .show_fdinfo =3D msm_show_fdinfo, + .ioctls =3D msm_ioctls, + .num_ioctls =3D ARRAY_SIZE(msm_ioctls), + .fops =3D &fops, + .name =3D "msm-kms", + .desc =3D "MSM Snapdragon DRM", + .major =3D MSM_VERSION_MAJOR, + .minor =3D MSM_VERSION_MINOR, + .patchlevel =3D MSM_VERSION_PATCHLEVEL, +}; + static const struct drm_driver msm_gpu_driver =3D { .driver_features =3D DRIVER_GEM | DRIVER_RENDER | @@ -982,7 +1015,11 @@ static int add_gpu_components(struct device *dev, =20 static int msm_drm_bind(struct device *dev) { - return msm_drm_init(dev, &msm_driver, NULL); + return msm_drm_init(dev, + msm_gpu_no_components() ? + &msm_kms_driver : + &msm_driver, + NULL); } =20 static void msm_drm_unbind(struct device *dev) @@ -1018,9 +1055,11 @@ int msm_drv_probe(struct device *master_dev, return ret; } =20 - ret =3D add_gpu_components(master_dev, &match); - if (ret) - return ret; + if (!msm_gpu_no_components()) { + ret =3D add_gpu_components(master_dev, &match); + if (ret) + return ret; + } =20 /* on all devices that I am aware of, iommu's which can map * any address the cpu can see are used: diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e3dfaa156307dcd8bb675f865985a0888be8fb87..9875ca62e9adb12dca9bcc74e28= 25b0364372a54 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -554,4 +554,6 @@ void msm_kms_shutdown(struct platform_device *pdev); =20 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); =20 +bool msm_gpu_no_components(void); + #endif /* __MSM_DRV_H__ */ --=20 2.39.5