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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384c0558sm526274e87.209.2025.07.05.03.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jul 2025 03:02:31 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 05 Jul 2025 13:02:26 +0300 Subject: [PATCH v4 01/10] drm/msm: move wq handling to KMS code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250705-msm-gpu-split-v4-1-fb470c481131@oss.qualcomm.com> References: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> In-Reply-To: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7299; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=BlPzvety+GReSb5ljsBIzhJtL2i+9ttmfQU5dRgJaXM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoaPgzHuOQATM2sXKXLoo1JJqXX4FG29PDSjVg5 /7l6d0HDWGJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaGj4MwAKCRCLPIo+Aiko 1TYkB/wL94YGKmC+l+nvVDramZxf1vgXqJIEqFNHI2UNNiH3A4n+2rHYDJqz7d7pniEC/WkS6ao jkhi+kNKJTS3ZHshb0283AIUka8ZK88syYytcrsagud8pvsS3XBpO9Q4UR5lGt6zr2jRWPCpYSR wxudm8oah5WwNeAkGf16d9Y569OBjxpERYcRL+yM/zKCIDmCfrfqHDPpEcODw0UJNbzcoDT1mBx XbCQ9beycTskjWmxXT+h1B0YxVEtoID0RLROaxTJ82WG04LnyCPq8M1a2qNNVgZkIsZ0AwP7oMg AcMytt6BjC9V4vkhpnicKLLZLnfr2HjBUbPcYzYYJ932KZ22 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=GdQXnRXL c=1 sm=1 tr=0 ts=6868f83b cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=T1fEnJx6pJBI0EFA4NgA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: 43LR18i-CWw-0ZSARq5mzD1GGs21m6G_ X-Proofpoint-ORIG-GUID: 43LR18i-CWw-0ZSARq5mzD1GGs21m6G_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA1MDA2NCBTYWx0ZWRfX2AIMIinM9BSg uqZBdHXMoVtBeBUy2qXZpZRWLh0jiHbBaz5oUUUrS8F4vdrFmzLZlftwjj9K9TGos+hG8wvUWHq HmnNXYu9MUgAB+ZoA/HhVSGOD+Hk85dRTblbdafNd4OLs6daJZ9TVWMyNQmigLzTM59jhxJ789S VZx8BxsWRIJXuDBTAMdaRpUgtO6l7H4iNYlrT+Kks2Tkk+iqdy7gte2wcMyin/dHW2d36WdoZGb W2Xdp8ocLLYwaUNx9a2O42CDOR85J1+YyIWJ7ZDE3+1eJ5alrtHi0PmRRLMWrXn+aTPF+wu9vuh yZ+pV5C1LOnqWNUN0jskEUPngLfxQ+04s1qdDoE+0qo5RKtxoUTHE4mXXCPGTR2frZfoxD4kJXj G5eYsOrnhgAQhFc/Y4PuIh+kaPGngbimbh54IBCehWOybceRshPOCPuFOmgEm35vlZgpizUg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_07,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 clxscore=1015 spamscore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 malwarescore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507050064 The global workqueue is only used for vblanks inside KMS code. Move allocation / flushing / deallcation of it to msm_kms.c Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 2 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 +- drivers/gpu/drm/msm/msm_drv.c | 21 ++------------------- drivers/gpu/drm/msm/msm_drv.h | 2 -- drivers/gpu/drm/msm/msm_kms.c | 11 +++++++++-- drivers/gpu/drm/msm/msm_kms.h | 8 ++++++++ 7 files changed, 22 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 078d3674ff411cf07614ae68889d8d0147453d10..f7abe8ba73ef0899ff1985ebf26= 571b7c459a52f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -980,7 +980,7 @@ static int dpu_encoder_resource_control(struct drm_enco= der *drm_enc, return 0; } =20 - queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, + queue_delayed_work(priv->kms->wq, &dpu_enc->delayed_off_work, msecs_to_jiffies(dpu_enc->idle_timeout)); =20 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/ms= m/disp/mdp4/mdp4_crtc.c index 0133c0c01a0bcd619089a5565719d764d88b63f8..2ee03ce2fd398be4f5b101be09c= 6dfb495324128 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c @@ -511,7 +511,7 @@ static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, u= int32_t irqstatus) =20 if (pending & PENDING_CURSOR) { update_cursor(crtc); - drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq); + drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->kms->wq); } } =20 diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/ms= m/disp/mdp5/mdp5_crtc.c index 298861f373b04cb4f7a37c42d0648a1c40d2aad1..4c4900a7beda8f7bd3184230a1c= 1b5f7ebd0c588 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -1196,7 +1196,7 @@ static void mdp5_crtc_vblank_irq(struct mdp_irq *irq,= uint32_t irqstatus) } =20 if (pending & PENDING_CURSOR) - drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq); + drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->kms->wq); } =20 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 2283a377cda14fc08aaab71e093b71f8e3954eec..8f79f5b9a61eb39dbd63b4ff225= b96e63ee9a5dd 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -77,13 +77,6 @@ static int msm_drm_uninit(struct device *dev) drm_atomic_helper_shutdown(ddev); } =20 - /* We must cancel and cleanup any pending vblank enable/disable - * work before msm_irq_uninstall() to avoid work re-enabling an - * irq after uninstall has disabled it. - */ - - flush_workqueue(priv->wq); - msm_gem_shrinker_cleanup(ddev); =20 msm_perf_debugfs_cleanup(priv); @@ -97,8 +90,6 @@ static int msm_drm_uninit(struct device *dev) ddev->dev_private =3D NULL; drm_dev_put(ddev); =20 - destroy_workqueue(priv->wq); - return 0; } =20 @@ -119,12 +110,6 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) ddev->dev_private =3D priv; priv->dev =3D ddev; =20 - priv->wq =3D alloc_ordered_workqueue("msm", 0); - if (!priv->wq) { - ret =3D -ENOMEM; - goto err_put_dev; - } - INIT_LIST_HEAD(&priv->objects); mutex_init(&priv->obj_lock); =20 @@ -149,7 +134,7 @@ static int msm_drm_init(struct device *dev, const struc= t drm_driver *drv) if (priv->kms_init) { ret =3D drmm_mode_config_init(ddev); if (ret) - goto err_destroy_wq; + goto err_put_dev; } =20 dma_set_max_seg_size(dev, UINT_MAX); @@ -157,7 +142,7 @@ static int msm_drm_init(struct device *dev, const struc= t drm_driver *drv) /* Bind all our sub-components: */ ret =3D component_bind_all(dev, ddev); if (ret) - goto err_destroy_wq; + goto err_put_dev; =20 ret =3D msm_gem_shrinker_init(ddev); if (ret) @@ -194,8 +179,6 @@ static int msm_drm_init(struct device *dev, const struc= t drm_driver *drv) =20 return ret; =20 -err_destroy_wq: - destroy_workqueue(priv->wq); err_put_dev: drm_dev_put(ddev); =20 diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 2b49c4b800eef039bb49907058c426b152e0f7f1..33d668a18ff3613b40341df540d= 504ffff65b2a7 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -175,8 +175,6 @@ struct msm_drm_private { struct mutex lock; } lru; =20 - struct workqueue_struct *wq; - unsigned int num_crtcs; =20 struct msm_drm_thread event_thread[MAX_CRTCS]; diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index e82b8569a46846fbd212c987f9f0d3e7939e12a2..c6c4d3a89ba829e161b060b52c9= 1f5323cb5a806 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -137,7 +137,7 @@ static int vblank_ctrl_queue_work(struct msm_drm_privat= e *priv, vbl_work->enable =3D enable; vbl_work->priv =3D priv; =20 - queue_work(priv->wq, &vbl_work->work); + queue_work(priv->kms->wq, &vbl_work->work); =20 return 0; } @@ -227,6 +227,13 @@ void msm_drm_kms_uninit(struct device *dev) =20 BUG_ON(!kms); =20 + /* We must cancel and cleanup any pending vblank enable/disable + * work before msm_irq_uninstall() to avoid work re-enabling an + * irq after uninstall has disabled it. + */ + + flush_workqueue(kms->wq); + /* clean up event worker threads */ for (i =3D 0; i < priv->num_crtcs; i++) { if (priv->event_thread[i].worker) @@ -261,7 +268,7 @@ int msm_drm_kms_init(struct device *dev, const struct d= rm_driver *drv) ret =3D priv->kms_init(ddev); if (ret) { DRM_DEV_ERROR(dev, "failed to load kms\n"); - return ret; + goto err_msm_uninit; } =20 /* Enable normalization of plane zpos */ diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 7cdb2eb6770035a8bbed548de3dcbebf94188fff..e48529c0a1554e8b9bf477dd71f= 59286b388de73 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -153,6 +153,8 @@ struct msm_kms { struct mutex commit_lock[MAX_CRTCS]; unsigned pending_crtc_mask; struct msm_pending_timer pending_timers[MAX_CRTCS]; + + struct workqueue_struct *wq; }; =20 static inline int msm_kms_init(struct msm_kms *kms, @@ -165,6 +167,10 @@ static inline int msm_kms_init(struct msm_kms *kms, =20 kms->funcs =3D funcs; =20 + kms->wq =3D alloc_ordered_workqueue("msm", 0); + if (!kms->wq) + return -ENOMEM; + for (i =3D 0; i < ARRAY_SIZE(kms->pending_timers); i++) { ret =3D msm_atomic_init_pending_timer(&kms->pending_timers[i], kms, i); if (ret) { @@ -181,6 +187,8 @@ static inline void msm_kms_destroy(struct msm_kms *kms) =20 for (i =3D 0; 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Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_drv.c | 9 +++------ drivers/gpu/drm/msm/msm_kms.c | 20 ++++++++++++++++++++ drivers/gpu/drm/msm/msm_kms.h | 2 ++ 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 8f79f5b9a61eb39dbd63b4ff225b96e63ee9a5dd..ce22d96033c8efe9210436eff82= 41f52d3c053bd 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -11,7 +11,6 @@ #include #include =20 -#include #include #include #include @@ -74,7 +73,7 @@ static int msm_drm_uninit(struct device *dev) if (ddev->registered) { drm_dev_unregister(ddev); if (priv->kms) - drm_atomic_helper_shutdown(ddev); + msm_drm_kms_unregister(dev); } =20 msm_gem_shrinker_cleanup(ddev); @@ -167,10 +166,8 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) if (ret) goto err_msm_uninit; =20 - if (priv->kms_init) { - drm_kms_helper_poll_init(ddev); - drm_client_setup(ddev, NULL); - } + if (priv->kms_init) + msm_drm_kms_post_init(dev); =20 return 0; =20 diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index c6c4d3a89ba829e161b060b52c91f5323cb5a806..9541dd7f56c9ea0f1d63c77b8ad= 8e7bc8cb46508 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include "disp/msm_disp_snapshot.h" #include "msm_drv.h" @@ -217,6 +218,15 @@ struct drm_gpuvm *msm_kms_init_vm(struct drm_device *d= ev) return vm; } =20 +void msm_drm_kms_unregister(struct device *dev) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct msm_drm_private *priv =3D platform_get_drvdata(pdev); + struct drm_device *ddev =3D priv->dev; + + drm_atomic_helper_shutdown(ddev); +} + void msm_drm_kms_uninit(struct device *dev) { struct platform_device *pdev =3D to_platform_device(dev); @@ -366,3 +376,13 @@ void msm_kms_shutdown(struct platform_device *pdev) if (drm && drm->registered && priv->kms) drm_atomic_helper_shutdown(drm); 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384c0558sm526274e87.209.2025.07.05.03.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jul 2025 03:02:36 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 05 Jul 2025 13:02:28 +0300 Subject: [PATCH v4 03/10] drm/msm/mdp4: get rid of mdp4_crtc.id Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250705-msm-gpu-split-v4-3-fb470c481131@oss.qualcomm.com> References: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> In-Reply-To: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3130; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=7I9SSPEIQPGrnlSdPo9OvtX0dZETia0LBeX4obv+vMM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoaPgzNe0zg+PB6a9Y3of8MKVqFfobTxyaNcWi2 nn50KXTRmqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaGj4MwAKCRCLPIo+Aiko 1RREB/9OJB18bPIclT1wQ2jGSYAG+LMaE5XWr4+F1sbgGdKNnWV6pCa2cT7yR2vPhAvK7ES37OP ywXc4klooDiRDycpDQ4u8w90zVU1SgVmdDD/80bBOwmXMQ9EsniGpil30R5QfjvQD6CAh3VYlaR xMnTLMraL162cF/M6gFyQy+rZYQXsyPgzP3+nlevTYDDPYYwqjzEJlY6N+1MKXywMzeCF1HbcAn SmNFCh4nHglzNYW/i/0AlR7gUsPlf4BcxMzMQISTFD34VgF1I0SQdMASHK8/azSk997wnsD7JJ9 RFbJW+eCVyUaVy8oaxGRCA10C+jRGcCOIKWWmOLhQ1MceZLF X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA1MDA2NCBTYWx0ZWRfX5ZbSUMxhp1VP GnvCTEorPV0DmveFoXlW4zpGrHTjqIxK/77Nvu554PuVbElipVG6dnu4Tssd0Z4OCZXRj80Dx2W aKURxHN5ggwUkluLIAQar4O4om7UOA45sWrhxs1bhRQ3NChu3aSe1vdcl0M1BftLju4Rm0dNkcX 5/odTKI6beCPdmA0xVxgHVltkCWK87Dkqp7AiDQfVmZIIYlxS49bSJQ/LMOg46ptBtaMnUm7qIr fokXRNa6jzHOV1Dk9k6wbPqTjl/oq86DLfu5AzMt2A7DTGgq9OpxOFZFfc3rt24RBrajxZGjTy3 ohJlL/m90+q0p2dFZ3pePNB9n0FOI/FHxpjS0rd5nU+7yTWCqCde6dzTM7FP1R8OwmhL0pBhNi0 zjA2MRy8kgWVLna0KKDL5mnXx8gvvn+0FYGp5Ee43y1AxnRdvGl09QVeJoPcRwUMpNlfzGIH X-Proofpoint-ORIG-GUID: gGT1TJvkEycfyPblcp5ir99VC08TGLR_ X-Authority-Analysis: v=2.4 cv=DNCP4zNb c=1 sm=1 tr=0 ts=6868f840 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=JeS6effYNUkig2QXyjUA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: gGT1TJvkEycfyPblcp5ir99VC08TGLR_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_07,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 spamscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=957 mlxscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507050064 There is no reason to store CRTC id, it's a part of the drm_crtc. Drop this member and use drm_crtc.name for the warning message. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 7 ++----- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 2 +- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/ms= m/disp/mdp4/mdp4_crtc.c index 2ee03ce2fd398be4f5b101be09c6dfb495324128..da53ca88251e7f184f4a7067fda= 16d6b426d3c49 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c @@ -17,7 +17,6 @@ struct mdp4_crtc { struct drm_crtc base; char name[8]; - int id; int ovlp; enum mdp4_dma dma; bool enabled; @@ -539,7 +538,7 @@ static void mdp4_crtc_wait_for_flush_done(struct drm_cr= tc *crtc) mdp4_crtc->flushed_mask), msecs_to_jiffies(50)); if (ret <=3D 0) - dev_warn(dev->dev, "vblank time out, crtc=3D%d\n", mdp4_crtc->id); + dev_warn(dev->dev, "vblank time out, crtc=3D%s\n", mdp4_crtc->base.name); =20 mdp4_crtc->flushed_mask =3D 0; =20 @@ -624,7 +623,7 @@ static void mdp4_crtc_flip_cleanup(struct drm_device *d= ev, void *ptr) =20 /* initialize crtc */ struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, - struct drm_plane *plane, int id, int ovlp_id, + struct drm_plane *plane, int ovlp_id, enum mdp4_dma dma_id) { struct drm_crtc *crtc =3D NULL; @@ -639,8 +638,6 @@ struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, =20 crtc =3D &mdp4_crtc->base; =20 - mdp4_crtc->id =3D id; - mdp4_crtc->ovlp =3D ovlp_id; mdp4_crtc->dma =3D dma_id; =20 diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.c index 9acde91ad6c37369191e85820e58ee22892a61a5..6d938abe29ee7283de2b1535d3d= 0159bf09d6dff 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -339,7 +339,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) goto fail; } =20 - crtc =3D mdp4_crtc_init(dev, plane, priv->num_crtcs, i, + crtc =3D mdp4_crtc_init(dev, plane, i, mdp4_crtcs[i]); if (IS_ERR(crtc)) { DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n", diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.h index f9d988076337cb6fb63af8e76be59b2eb34ab327..fb348583dc84de5c57c77fdf246= 894e9334af514 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h @@ -185,7 +185,7 @@ void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32= _t config); 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 3 --- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 4 +--- drivers/gpu/drm/msm/msm_drv.h | 2 -- drivers/gpu/drm/msm/msm_kms.c | 4 ++-- 5 files changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index e63a62664f39d73033e65adab5a90fd43c844a78..7025f521b70e501eefa69ddcdba= 64d38e0ca5465 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -875,12 +875,11 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_= kms) ret =3D PTR_ERR(crtc); return ret; } - priv->num_crtcs++; } =20 /* All CRTCs are compatible with all encoders */ drm_for_each_encoder(encoder, dev) - encoder->possible_crtcs =3D (1 << priv->num_crtcs) - 1; + encoder->possible_crtcs =3D (1 << dev->mode_config.num_crtc) - 1; =20 return 0; } diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.c index 6d938abe29ee7283de2b1535d3d0159bf09d6dff..1aa7d65afbd0b4e8a231d1d4ff7= a7120e8b7391e 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -297,7 +297,6 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4= _kms, static int modeset_init(struct mdp4_kms *mdp4_kms) { struct drm_device *dev =3D mdp4_kms->dev; - struct msm_drm_private *priv =3D dev->dev_private; struct drm_plane *plane; struct drm_crtc *crtc; int i, ret; @@ -347,8 +346,6 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) ret =3D PTR_ERR(crtc); goto fail; } - - priv->num_crtcs++; } =20 /* diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm= /disp/mdp5/mdp5_kms.c index b6e6bd1f95eebf890a8dced129854e8e19e60c9c..4c9e79fc00e9d8ca8de294c8355= 9e72a2e48d1d2 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -375,7 +375,6 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, static int modeset_init(struct mdp5_kms *mdp5_kms) { struct drm_device *dev =3D mdp5_kms->dev; - struct msm_drm_private *priv =3D dev->dev_private; unsigned int num_crtcs; int i, ret, pi =3D 0, ci =3D 0; struct drm_plane *primary[MAX_BASES] =3D { NULL }; @@ -443,7 +442,6 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); goto fail; } - priv->num_crtcs++; } =20 /* @@ -451,7 +449,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) * crtcs for the encoders */ drm_for_each_encoder(encoder, dev) - encoder->possible_crtcs =3D (1 << priv->num_crtcs) - 1; + encoder->possible_crtcs =3D (1 << dev->mode_config.num_crtc) - 1; =20 return 0; =20 diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 33d668a18ff3613b40341df540d504ffff65b2a7..88ce305792fd89f280b39bd9288= 8a18abd0343e3 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -175,8 +175,6 @@ struct msm_drm_private { struct mutex lock; } lru; =20 - unsigned int num_crtcs; - struct msm_drm_thread event_thread[MAX_CRTCS]; =20 struct notifier_block vmap_notifier; diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 9541dd7f56c9ea0f1d63c77b8ad8e7bc8cb46508..a63d014c19039835de47fb3fb61= 0ce67652b5d2c 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -245,7 +245,7 @@ void msm_drm_kms_uninit(struct device *dev) flush_workqueue(kms->wq); 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Move corresponding data pointers from struct msm_drm_private to struct msm_kms. Suggested-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 32 +++++++++++--------= ---- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 8 +++--- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 13 ++++----- drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c | 12 ++++----- drivers/gpu/drm/msm/dp/dp_display.c | 6 ++--- drivers/gpu/drm/msm/dsi/dsi.c | 4 +-- drivers/gpu/drm/msm/hdmi/hdmi.c | 9 ++++--- drivers/gpu/drm/msm/msm_drv.h | 11 +------- drivers/gpu/drm/msm/msm_kms.h | 6 +++++ 10 files changed, 55 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index f7abe8ba73ef0899ff1985ebf26571b7c459a52f..05e5f3463e30c9a6bd5b7405807= 20ae2bf6b3246 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -264,7 +264,7 @@ bool dpu_encoder_needs_periph_flush(struct dpu_encoder_= phys *phys_enc) mode =3D &phys_enc->cached_mode; =20 return phys_enc->hw_intf->cap->type =3D=3D INTF_DP && - msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]],= mode); + msm_dp_needs_periph_flush(priv->kms->dp[disp_info->h_tile_instance= [0]], mode); } =20 /** @@ -283,9 +283,9 @@ bool dpu_encoder_is_widebus_enabled(const struct drm_en= coder *drm_enc) index =3D disp_info->h_tile_instance[0]; =20 if (disp_info->intf_type =3D=3D INTF_DP) - return msm_dp_wide_bus_available(priv->dp[index]); + return msm_dp_wide_bus_available(priv->kms->dp[index]); else if (disp_info->intf_type =3D=3D INTF_DSI) - return msm_dsi_wide_bus_enabled(priv->dsi[index]); + return msm_dsi_wide_bus_enabled(priv->kms->dsi[index]); =20 return false; } @@ -647,7 +647,7 @@ struct drm_dsc_config *dpu_encoder_get_dsc_config(struc= t drm_encoder *drm_enc) int index =3D dpu_enc->disp_info.h_tile_instance[0]; =20 if (dpu_enc->disp_info.intf_type =3D=3D INTF_DSI) - return msm_dsi_get_dsc_config(priv->dsi[index]); + return msm_dsi_get_dsc_config(priv->kms->dsi[index]); =20 return NULL; } @@ -709,7 +709,8 @@ void dpu_encoder_update_topology(struct drm_encoder *dr= m_enc, if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) topology->num_cdm++; } else if (disp_info->intf_type =3D=3D INTF_DP) { - if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], a= dj_mode)) + if (msm_dp_is_yuv_420_enabled(priv->kms->dp[disp_info->h_tile_instance[0= ]], + adj_mode)) topology->num_cdm++; } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 7025f521b70e501eefa69ddcdba64d38e0ca5465..12dcb32b472497f9e59619db4e8= 10abfbf610c7c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -583,7 +583,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *d= ev, struct msm_display_info info; int i, rc =3D 0; =20 - if (!(priv->dsi[0] || priv->dsi[1])) + if (!(priv->kms->dsi[0] || priv->kms->dsi[1])) return rc; =20 /* @@ -594,26 +594,26 @@ static int _dpu_kms_initialize_dsi(struct drm_device = *dev, * * TODO: Support swapping DSI0 and DSI1 in the bonded setup. */ - for (i =3D 0; i < ARRAY_SIZE(priv->dsi); i++) { + for (i =3D 0; i < ARRAY_SIZE(priv->kms->dsi); i++) { int other =3D (i + 1) % 2; =20 - if (!priv->dsi[i]) + if (!priv->kms->dsi[i]) continue; =20 - if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && - !msm_dsi_is_master_dsi(priv->dsi[i])) + if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i]) && + !msm_dsi_is_master_dsi(priv->kms->dsi[i])) continue; =20 memset(&info, 0, sizeof(info)); info.intf_type =3D INTF_DSI; =20 info.h_tile_instance[info.num_of_h_tiles++] =3D i; - if (msm_dsi_is_bonded_dsi(priv->dsi[i])) + if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i])) info.h_tile_instance[info.num_of_h_tiles++] =3D other; =20 - info.is_cmd_mode =3D msm_dsi_is_cmd_mode(priv->dsi[i]); + info.is_cmd_mode =3D msm_dsi_is_cmd_mode(priv->kms->dsi[i]); =20 - rc =3D dpu_kms_dsi_set_te_source(&info, priv->dsi[i]); + rc =3D dpu_kms_dsi_set_te_source(&info, priv->kms->dsi[i]); if (rc) { DPU_ERROR("failed to identify TE source for dsi display\n"); return rc; @@ -625,15 +625,15 @@ static int _dpu_kms_initialize_dsi(struct drm_device = *dev, return PTR_ERR(encoder); } =20 - rc =3D msm_dsi_modeset_init(priv->dsi[i], dev, encoder); + rc =3D msm_dsi_modeset_init(priv->kms->dsi[i], dev, encoder); if (rc) { DPU_ERROR("modeset_init failed for dsi[%d], rc =3D %d\n", i, rc); break; } =20 - if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { - rc =3D msm_dsi_modeset_init(priv->dsi[other], dev, encoder); + if (msm_dsi_is_bonded_dsi(priv->kms->dsi[i]) && priv->kms->dsi[other]) { + rc =3D msm_dsi_modeset_init(priv->kms->dsi[other], dev, encoder); if (rc) { DPU_ERROR("modeset_init failed for dsi[%d], rc =3D %d\n", other, rc); @@ -655,8 +655,8 @@ static int _dpu_kms_initialize_displayport(struct drm_d= evice *dev, int rc; int i; =20 - for (i =3D 0; i < ARRAY_SIZE(priv->dp); i++) { - if (!priv->dp[i]) + for (i =3D 0; i < ARRAY_SIZE(priv->kms->dp); i++) { + if (!priv->kms->dp[i]) continue; =20 memset(&info, 0, sizeof(info)); @@ -671,7 +671,7 @@ static int _dpu_kms_initialize_displayport(struct drm_d= evice *dev, } =20 yuv_supported =3D !!dpu_kms->catalog->cdm; - rc =3D msm_dp_modeset_init(priv->dp[i], dev, encoder, yuv_supported); + rc =3D msm_dp_modeset_init(priv->kms->dp[i], dev, encoder, yuv_supported= ); if (rc) { DPU_ERROR("modeset_init failed for DP, rc =3D %d\n", rc); return rc; @@ -689,7 +689,7 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *= dev, struct msm_display_info info; int rc; =20 - if (!priv->hdmi) + if (!priv->kms->hdmi) return 0; =20 memset(&info, 0, sizeof(info)); @@ -703,7 +703,7 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *= dev, return PTR_ERR(encoder); } =20 - rc =3D msm_hdmi_modeset_init(priv->hdmi, dev, encoder); + rc =3D msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); if (rc) { DPU_ERROR("modeset_init failed for DP, rc =3D %d\n", rc); return rc; diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.c index 1aa7d65afbd0b4e8a231d1d4ff7a7120e8b7391e..0952c7f18abdca4a7e24e5af8a7= 132456bfec129 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -250,9 +250,9 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4= _kms, /* DTV can be hooked to DMA_E: */ encoder->possible_crtcs =3D 1 << 1; =20 - if (priv->hdmi) { + if (priv->kms->hdmi) { /* Construct bridge/connector for HDMI: */ - ret =3D msm_hdmi_modeset_init(priv->hdmi, dev, encoder); + ret =3D msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); if (ret) { DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret); return ret; @@ -264,7 +264,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4= _kms, /* only DSI1 supported for now */ dsi_id =3D 0; =20 - if (!priv->dsi[dsi_id]) + if (!priv->kms->dsi[dsi_id]) break; =20 encoder =3D mdp4_dsi_encoder_init(dev); @@ -278,7 +278,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4= _kms, /* TODO: Add DMA_S later? */ encoder->possible_crtcs =3D 1 << DMA_P; =20 - ret =3D msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); + ret =3D msm_dsi_modeset_init(priv->kms->dsi[dsi_id], dev, encoder); if (ret) { DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n", ret); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm= /disp/mdp5/mdp5_kms.c index 4c9e79fc00e9d8ca8de294c83559e72a2e48d1d2..5b6ca8dd929e1870b7228af93da= 03886524f5f20 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -312,7 +312,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num); break; case INTF_HDMI: - if (!priv->hdmi) + if (!priv->kms->hdmi) break; =20 ctl =3D mdp5_ctlm_request(ctlm, intf->num); @@ -327,7 +327,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, break; } =20 - ret =3D msm_hdmi_modeset_init(priv->hdmi, dev, encoder); + ret =3D msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); break; case INTF_DSI: { @@ -335,14 +335,14 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_km= s, mdp5_cfg_get_hw_config(mdp5_kms->cfg); int dsi_id =3D get_dsi_id_from_intf(hw_cfg, intf->num); =20 - if ((dsi_id >=3D ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { + if ((dsi_id >=3D ARRAY_SIZE(priv->kms->dsi)) || (dsi_id < 0)) { DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", intf->num); ret =3D -EINVAL; break; } =20 - if (!priv->dsi[dsi_id]) + if (!priv->kms->dsi[dsi_id]) break; =20 ctl =3D mdp5_ctlm_request(ctlm, intf->num); @@ -357,9 +357,10 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, break; } =20 - ret =3D msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); + ret =3D msm_dsi_modeset_init(priv->kms->dsi[dsi_id], dev, encoder); if (!ret) - mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_i= d])); + mdp5_encoder_set_intf_mode(encoder, + msm_dsi_is_cmd_mode(priv->kms->dsi[dsi_id])); =20 break; } diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c b/drivers/gp= u/drm/msm/disp/msm_disp_snapshot_util.c index 07a2c1e872193bc96172c84142bd4ecc93a95a1c..071bcdea80f7114308e5a1e1a98= 9ad0f064a09d2 100644 --- a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c @@ -127,18 +127,18 @@ void msm_disp_snapshot_capture_state(struct msm_disp_= state *disp_state) priv =3D drm_dev->dev_private; kms =3D priv->kms; =20 - for (i =3D 0; i < ARRAY_SIZE(priv->dp); i++) { - if (!priv->dp[i]) + for (i =3D 0; i < ARRAY_SIZE(kms->dp); i++) { + if (!kms->dp[i]) continue; =20 - msm_dp_snapshot(disp_state, priv->dp[i]); + msm_dp_snapshot(disp_state, kms->dp[i]); } =20 - for (i =3D 0; i < ARRAY_SIZE(priv->dsi); i++) { - if (!priv->dsi[i]) + for (i =3D 0; i < ARRAY_SIZE(kms->dsi); i++) { + if (!kms->dsi[i]) continue; =20 - msm_dsi_snapshot(disp_state, priv->dsi[i]); + msm_dsi_snapshot(disp_state, kms->dsi[i]); } =20 if (kms->funcs->snapshot) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 2006e7fe78848531bd121c07ebb449decab66029..d87d47cc7ec3eb757ac192c4110= 00bc50b824c59 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -292,9 +292,7 @@ static int msm_dp_display_bind(struct device *dev, stru= ct device *master, struct drm_device *drm =3D priv->dev; =20 dp->msm_dp_display.drm_dev =3D drm; - priv->dp[dp->id] =3D &dp->msm_dp_display; - - + priv->kms->dp[dp->id] =3D &dp->msm_dp_display; =20 dp->drm_dev =3D drm; dp->aux->drm_dev =3D drm; @@ -328,7 +326,7 @@ static void msm_dp_display_unbind(struct device *dev, s= truct device *master, msm_dp_aux_unregister(dp->aux); dp->drm_dev =3D NULL; dp->aux->drm_dev =3D NULL; - priv->dp[dp->id] =3D NULL; + priv->kms->dp[dp->id] =3D NULL; } =20 static const struct component_ops msm_dp_display_comp_ops =3D { diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 2962158776135d6e3c5b119bf4341c135c8f5248..d8bb40ef820e2b8c8ac933ca01e= 1dc46f087a218 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -136,7 +136,7 @@ static int dsi_bind(struct device *dev, struct device *= master, void *data) msm_dsi->next_bridge =3D ext_bridge; } =20 - priv->dsi[msm_dsi->id] =3D msm_dsi; + priv->kms->dsi[msm_dsi->id] =3D msm_dsi; =20 return 0; } @@ -148,7 +148,7 @@ static void dsi_unbind(struct device *dev, struct devic= e *master, struct msm_dsi *msm_dsi =3D dev_get_drvdata(dev); =20 msm_dsi_tx_buf_free(msm_dsi->host); - priv->dsi[msm_dsi->id] =3D NULL; + priv->kms->dsi[msm_dsi->id] =3D NULL; } =20 static const struct component_ops dsi_ops =3D { diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdm= i.c index 2fd388b892dcb3d83cf57b4616b7a65f9ff674d1..5afac09c0d3347f85a3449207b3= c876aae4dd1e2 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -15,6 +15,7 @@ #include #include =20 +#include "msm_kms.h" #include "hdmi.h" =20 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on) @@ -244,7 +245,7 @@ static int msm_hdmi_bind(struct device *dev, struct dev= ice *master, void *data) err =3D msm_hdmi_init(hdmi); if (err) return err; - priv->hdmi =3D hdmi; + priv->kms->hdmi =3D hdmi; =20 return 0; } @@ -254,9 +255,9 @@ static void msm_hdmi_unbind(struct device *dev, struct = device *master, { struct msm_drm_private *priv =3D dev_get_drvdata(master); =20 - if (priv->hdmi) { - msm_hdmi_destroy(priv->hdmi); - priv->hdmi =3D NULL; + if (priv->kms->hdmi) { + msm_hdmi_destroy(priv->kms->hdmi); + priv->kms->hdmi =3D NULL; } } =20 diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 88ce305792fd89f280b39bd92888a18abd0343e3..e7872b752c6c8e5869927634184= 733796afa1967 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -86,16 +86,6 @@ struct msm_drm_private { /* subordinate devices, if present: */ struct platform_device *gpu_pdev; =20 - /* possibly this should be in the kms component, but it is - * shared by both mdp4 and mdp5.. - */ - struct hdmi *hdmi; - - /* DSI is shared by mdp4 and mdp5 */ - struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; - - struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 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Build corresponding parts conditionally, only selecting them if modeset support is actually required. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 14 +++++ drivers/gpu/drm/msm/Makefile | 19 +++---- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +- drivers/gpu/drm/msm/dp/dp_debug.c | 4 ++ drivers/gpu/drm/msm/msm_debugfs.c | 92 ++++++++++++++++++----------= ---- drivers/gpu/drm/msm/msm_drv.h | 10 +--- drivers/gpu/drm/msm/msm_kms.c | 6 +-- drivers/gpu/drm/msm/msm_kms.h | 30 +++++++++++ 8 files changed, 117 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 8fb99f64a61548eae8ac74cf6cc99ffd2f3c7204..3a0a69f41153c5f32670e07f972= 8d9b9e947be92 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -68,6 +68,14 @@ config DRM_MSM_VALIDATE_XML Validate XML files with register definitions against rules-fd schema. This option is mostly targeting DRM MSM developers. If unsure, say N. =20 +config DRM_MSM_KMS + def_bool n + depends on DRM_MSM + +config DRM_MSM_KMS_FBDEV + def_bool DRM_FBDEV_EMULATION + depends on DRM_MSM_KMS + config DRM_MSM_MDSS bool depends on DRM_MSM @@ -76,6 +84,7 @@ config DRM_MSM_MDSS config DRM_MSM_MDP4 bool "Enable MDP4 support in MSM DRM driver" depends on DRM_MSM + select DRM_MSM_KMS default y help Compile in support for the Mobile Display Processor v4 (MDP4) in @@ -86,6 +95,7 @@ config DRM_MSM_MDP5 bool "Enable MDP5 support in MSM DRM driver" depends on DRM_MSM select DRM_MSM_MDSS + select DRM_MSM_KMS default y help Compile in support for the Mobile Display Processor v5 (MDP5) in @@ -96,6 +106,7 @@ config DRM_MSM_DPU bool "Enable DPU support in MSM DRM driver" depends on DRM_MSM select DRM_MSM_MDSS + select DRM_MSM_KMS select DRM_DISPLAY_DSC_HELPER default y help @@ -106,6 +117,7 @@ config DRM_MSM_DPU config DRM_MSM_DP bool "Enable DisplayPort support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS select DRM_DISPLAY_HDMI_AUDIO_HELPER select RATIONAL default y @@ -117,6 +129,7 @@ config DRM_MSM_DP config DRM_MSM_DSI bool "Enable DSI support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS select DRM_PANEL select DRM_MIPI_DSI select DRM_DISPLAY_DSC_HELPER @@ -172,6 +185,7 @@ config DRM_MSM_DSI_7NM_PHY config DRM_MSM_HDMI bool "Enable HDMI support in MSM DRM driver" depends on DRM_MSM + depends on DRM_MSM_KMS default y select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HDMI_STATE_HELPER diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 514bacd5e4998a60da3fa9cb751220e96af0c2c9..0c0dfb25f01b193b10946fae201= 38caf32cf0ed2 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -100,18 +100,15 @@ msm-display-$(CONFIG_DRM_MSM_DPU) +=3D \ msm-display-$(CONFIG_DRM_MSM_MDSS) +=3D \ msm_mdss.o \ =20 -msm-display-y +=3D \ +msm-display-$(CONFIG_DRM_MSM_KMS) +=3D \ disp/mdp_format.o \ disp/mdp_kms.o \ disp/msm_disp_snapshot.o \ disp/msm_disp_snapshot_util.o \ =20 msm-y +=3D \ - msm_atomic.o \ - msm_atomic_tracepoints.o \ msm_debugfs.o \ msm_drv.o \ - msm_fb.o \ msm_fence.o \ msm_gem.o \ msm_gem_prime.o \ @@ -122,7 +119,6 @@ msm-y +=3D \ msm_gpu_devfreq.o \ msm_io_utils.o \ msm_iommu.o \ - msm_kms.o \ msm_perf.o \ msm_rd.o \ msm_ringbuffer.o \ @@ -130,13 +126,17 @@ msm-y +=3D \ msm_syncobj.o \ msm_gpu_tracepoints.o \ =20 -msm-$(CONFIG_DRM_FBDEV_EMULATION) +=3D msm_fbdev.o +msm-$(CONFIG_DRM_MSM_KMS) +=3D \ + msm_atomic.o \ + msm_atomic_tracepoints.o \ + msm_fb.o \ + msm_kms.o \ =20 -msm-display-$(CONFIG_DEBUG_FS) +=3D \ - dp/dp_debug.o +msm-$(CONFIG_DRM_MSM_KMS_FBDEV) +=3D msm_fbdev.o =20 msm-display-$(CONFIG_DRM_MSM_DP)+=3D dp/dp_aux.o \ dp/dp_ctrl.o \ + dp/dp_debug.o \ dp/dp_display.o \ dp/dp_drm.o \ dp/dp_link.o \ @@ -159,7 +159,8 @@ msm-display-$(CONFIG_DRM_MSM_DSI_14NM_PHY) +=3D dsi/phy= /dsi_phy_14nm.o msm-display-$(CONFIG_DRM_MSM_DSI_10NM_PHY) +=3D dsi/phy/dsi_phy_10nm.o msm-display-$(CONFIG_DRM_MSM_DSI_7NM_PHY) +=3D dsi/phy/dsi_phy_7nm.o =20 -msm-y +=3D $(adreno-y) $(msm-display-y) +msm-y +=3D $(adreno-y) +msm-$(CONFIG_DRM_MSM_KMS) +=3D $(msm-display-y) =20 obj-$(CONFIG_DRM_MSM) +=3D msm.o =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 782aa86208d54cc28c5ad51215ef458483ff3dfb..d4b545448d74657aafc96e9042c= 7756654b4f0e7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -742,7 +742,7 @@ void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32= event) fevent->event =3D event; fevent->crtc =3D crtc; fevent->ts =3D ktime_get(); - kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work); + kthread_queue_work(priv->kms->event_thread[crtc_id].worker, &fevent->work= ); } =20 /** @@ -911,7 +911,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, dev =3D crtc->dev; priv =3D dev->dev_private; =20 - if (crtc->index >=3D ARRAY_SIZE(priv->event_thread)) { + if (crtc->index >=3D ARRAY_SIZE(priv->kms->event_thread)) { DPU_ERROR("invalid crtc index[%d]\n", crtc->index); return; } diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_= debug.c index b65b358e98381488ecd0ecb8648dbe76dd6ff310..cf3838fcd154e67b6bd8f6321a8= 711419543abcb 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -5,6 +5,8 @@ =20 #define pr_fmt(fmt)"[drm-dp] %s: " fmt, __func__ =20 +#ifdef CONFIG_DEBUG_FS + #include #include #include @@ -234,3 +236,5 @@ int msm_dp_debug_init(struct device *dev, struct msm_dp= _panel *panel, =20 return 0; } + +#endif diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_de= bugfs.c index 6af72162cda4c8d4bc8dd4c6473cbc29817bb3c6..4680ccf3e72fa5c31afda5665de= fe71d1f238dac 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -117,6 +117,36 @@ static const struct file_operations msm_gpu_fops =3D { .release =3D msm_gpu_release, }; =20 +#ifdef CONFIG_DRM_MSM_KMS +static int msm_fb_show(struct seq_file *m, void *arg) +{ + struct drm_info_node *node =3D m->private; + struct drm_device *dev =3D node->minor->dev; + struct drm_framebuffer *fb, *fbdev_fb =3D NULL; + + if (dev->fb_helper && dev->fb_helper->fb) { + seq_puts(m, "fbcon "); + fbdev_fb =3D dev->fb_helper->fb; + msm_framebuffer_describe(fbdev_fb, m); + } + + mutex_lock(&dev->mode_config.fb_lock); + list_for_each_entry(fb, &dev->mode_config.fb_list, head) { + if (fb =3D=3D fbdev_fb) + continue; + + seq_puts(m, "user "); + msm_framebuffer_describe(fb, m); + } + mutex_unlock(&dev->mode_config.fb_lock); + + return 0; +} + +static struct drm_info_list msm_kms_debugfs_list[] =3D { + { "fb", msm_fb_show }, +}; + /* * Display Snapshot: */ @@ -180,6 +210,27 @@ static const struct file_operations msm_kms_fops =3D { .release =3D msm_kms_release, }; =20 +static void msm_debugfs_kms_init(struct drm_minor *minor) +{ + struct drm_device *dev =3D minor->dev; + struct msm_drm_private *priv =3D dev->dev_private; + + drm_debugfs_create_files(msm_kms_debugfs_list, + ARRAY_SIZE(msm_kms_debugfs_list), + minor->debugfs_root, minor); + debugfs_create_file("kms", 0400, minor->debugfs_root, + dev, &msm_kms_fops); + + if (priv->kms->funcs->debugfs_init) + priv->kms->funcs->debugfs_init(priv->kms, minor); + +} +#else /* ! CONFIG_DRM_MSM_KMS */ +static void msm_debugfs_kms_init(struct drm_minor *minor) +{ +} +#endif + /* * Other debugfs: */ @@ -267,40 +318,11 @@ static int msm_mm_show(struct seq_file *m, void *arg) return 0; } =20 -static int msm_fb_show(struct seq_file *m, void *arg) -{ - struct drm_info_node *node =3D m->private; - struct drm_device *dev =3D node->minor->dev; - struct drm_framebuffer *fb, *fbdev_fb =3D NULL; - - if (dev->fb_helper && dev->fb_helper->fb) { - seq_printf(m, "fbcon "); - fbdev_fb =3D dev->fb_helper->fb; - msm_framebuffer_describe(fbdev_fb, m); - } - - mutex_lock(&dev->mode_config.fb_lock); - list_for_each_entry(fb, &dev->mode_config.fb_list, head) { - if (fb =3D=3D fbdev_fb) - continue; - - seq_printf(m, "user "); - msm_framebuffer_describe(fb, m); - } - mutex_unlock(&dev->mode_config.fb_lock); - - return 0; -} - static struct drm_info_list msm_debugfs_list[] =3D { {"gem", msm_gem_show}, { "mm", msm_mm_show }, }; =20 -static struct drm_info_list msm_kms_debugfs_list[] =3D { - { "fb", msm_fb_show }, -}; - static int late_init_minor(struct drm_minor *minor) { int ret; @@ -375,20 +397,12 @@ void msm_debugfs_init(struct drm_minor *minor) if (priv->gpu_pdev) msm_debugfs_gpu_init(minor); =20 - if (priv->kms) { - drm_debugfs_create_files(msm_kms_debugfs_list, - ARRAY_SIZE(msm_kms_debugfs_list), - minor->debugfs_root, minor); - debugfs_create_file("kms", S_IRUSR, minor->debugfs_root, - dev, &msm_kms_fops); - } + if (priv->kms) + msm_debugfs_kms_init(minor); =20 debugfs_create_file("shrink", S_IRWXU, minor->debugfs_root, dev, &shrink_fops); =20 - if (priv->kms && priv->kms->funcs->debugfs_init) - priv->kms->funcs->debugfs_init(priv->kms, minor); - fault_create_debugfs_attr("fail_gem_alloc", minor->debugfs_root, &fail_gem_alloc); fault_create_debugfs_attr("fail_gem_iova", minor->debugfs_root, diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e7872b752c6c8e5869927634184733796afa1967..5b276a4540753aa25d46e50f095= 7790ed39474ae 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -70,12 +70,6 @@ enum msm_dsi_controller { =20 #define MSM_GPU_MAX_RINGS 4 =20 -/* Commit/Event thread specific structure */ -struct msm_drm_thread { - struct drm_device *dev; - struct kthread_worker *worker; -}; - struct msm_drm_private { =20 struct drm_device *dev; @@ -165,8 +159,6 @@ struct msm_drm_private { struct mutex lock; } lru; =20 - struct msm_drm_thread event_thread[MAX_CRTCS]; - struct notifier_block vmap_notifier; struct shrinker *shrinker; =20 @@ -272,7 +264,7 @@ struct drm_framebuffer *msm_framebuffer_create(struct d= rm_device *dev, struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, int w, int h, int p, uint32_t format); =20 -#ifdef CONFIG_DRM_FBDEV_EMULATION +#ifdef CONFIG_DRM_MSM_KMS_FBDEV int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes); #define MSM_FBDEV_DRIVER_OPS \ diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index a63d014c19039835de47fb3fb610ce67652b5d2c..6889f1c1e72121dcc735fa460ea= 04cdab11c6705 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -246,8 +246,8 @@ void msm_drm_kms_uninit(struct device *dev) =20 /* clean up event worker threads */ for (i =3D 0; i < MAX_CRTCS; i++) { - if (priv->event_thread[i].worker) - kthread_destroy_worker(priv->event_thread[i].worker); + if (kms->event_thread[i].worker) + kthread_destroy_worker(kms->event_thread[i].worker); } =20 drm_kms_helper_poll_fini(ddev); @@ -300,7 +300,7 @@ int msm_drm_kms_init(struct device *dev, const struct d= rm_driver *drv) struct msm_drm_thread *ev_thread; =20 /* initialize event thread */ - ev_thread =3D &priv->event_thread[drm_crtc_index(crtc)]; + ev_thread =3D &kms->event_thread[drm_crtc_index(crtc)]; ev_thread->dev =3D ddev; ev_thread->worker =3D kthread_run_worker(0, "crtc_event:%d", crtc->base.= id); if (IS_ERR(ev_thread->worker)) { diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index f4eb486531890f3351cf83670be801e8fd3631bb..8a7be7b854deea9b763ec45df27= 5fab77d806e44 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -13,6 +13,8 @@ =20 #include "msm_drv.h" =20 +#ifdef CONFIG_DRM_MSM_KMS + #define MAX_PLANE 4 =20 /* As there are different display controller blocks depending on the @@ -127,6 +129,12 @@ struct msm_pending_timer { unsigned crtc_idx; }; =20 +/* Commit/Event thread specific structure */ +struct msm_drm_thread { + struct drm_device *dev; + struct kthread_worker *worker; +}; + struct msm_kms { const struct msm_kms_funcs *funcs; struct drm_device *dev; @@ -161,6 +169,7 @@ struct msm_kms { struct msm_pending_timer pending_timers[MAX_CRTCS]; =20 struct workqueue_struct *wq; + struct msm_drm_thread event_thread[MAX_CRTCS]; }; =20 static inline int msm_kms_init(struct msm_kms *kms, @@ -210,4 +219,25 @@ void msm_drm_kms_post_init(struct device *dev); void msm_drm_kms_unregister(struct device *dev); void msm_drm_kms_uninit(struct device *dev); =20 +#else /* ! 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Bail out if we are registering a KMS-only device. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_debugfs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_de= bugfs.c index 4680ccf3e72fa5c31afda5665defe71d1f238dac..bbda865addae2e0ef5bb175bec0= ed219cd0d9988 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -325,11 +325,16 @@ static struct drm_info_list msm_debugfs_list[] =3D { =20 static int late_init_minor(struct drm_minor *minor) { + struct drm_device *dev =3D minor->dev; + struct msm_drm_private *priv =3D dev->dev_private; int ret; =20 if (!minor) return 0; =20 + if (!priv->gpu_pdev) + return 0; + ret =3D msm_rd_debugfs_init(minor); if (ret) { DRM_DEV_ERROR(minor->dev->dev, "could not install rd debugfs\n"); --=20 2.39.5 From nobody Tue Oct 7 21:18:30 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0FDC28ECF4 for ; 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Kconfig | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 3a0a69f41153c5f32670e07f9728d9b9e947be92..250246f81ea94f01a016e8938f0= 8e1aa4ce02442 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -15,19 +15,9 @@ config DRM_MSM select IOMMU_IO_PGTABLE select QCOM_MDT_LOADER if ARCH_QCOM select REGULATOR - select DRM_CLIENT_SELECTION - select DRM_DISPLAY_DP_AUX_BUS - select DRM_DISPLAY_DP_HELPER - select DRM_DISPLAY_HELPER - select DRM_BRIDGE_CONNECTOR select DRM_EXEC select DRM_GPUVM - select DRM_KMS_HELPER - select DRM_PANEL - select DRM_BRIDGE - select DRM_PANEL_BRIDGE select DRM_SCHED - select FB_SYSMEM_HELPERS if DRM_FBDEV_EMULATION select SHMEM select TMPFS select QCOM_SCM @@ -71,10 +61,18 @@ config DRM_MSM_VALIDATE_XML config DRM_MSM_KMS def_bool n depends on DRM_MSM + select DRM_BRIDGE + select DRM_BRIDGE_CONNECTOR + select DRM_CLIENT_SELECTION + select DRM_DISPLAY_HELPER + select DRM_KMS_HELPER + select DRM_PANEL + select DRM_PANEL_BRIDGE =20 config DRM_MSM_KMS_FBDEV def_bool DRM_FBDEV_EMULATION depends on DRM_MSM_KMS + select FB_SYSMEM_HELPERS =20 config DRM_MSM_MDSS bool @@ -120,6 +118,8 @@ config DRM_MSM_DP depends on DRM_MSM_KMS select DRM_DISPLAY_HDMI_AUDIO_HELPER select RATIONAL + select DRM_DISPLAY_DP_AUX_BUS + select DRM_DISPLAY_DP_HELPER default y help Compile in support for DP driver in MSM DRM driver. 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384c0558sm526274e87.209.2025.07.05.03.02.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jul 2025 03:02:46 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 05 Jul 2025 13:02:34 +0300 Subject: [PATCH v4 09/10] drm/msm: rework binding of Imageon GPUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250705-msm-gpu-split-v4-9-fb470c481131@oss.qualcomm.com> References: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> In-Reply-To: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8542; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=DzVL9H2k4LmoWJqL5HQzeipbdtWihS0FDl5ptM9m0fA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoaPg0eMjLyvJMK+TxcHhy9pdiAsiUTlm6MifqZ c3uwA+QjZiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaGj4NAAKCRCLPIo+Aiko 1YtSCACgGZ5QYELXU4AiIrnS/jr+LAdjV5d6L0QR1eduMI//qmyenSXFOtVLVd9g5sRA4p70Y2K SuS/xaPD/qyhdpiwrgHkj44Onl/7mPvOwR2GMRU/ZYYJ+ePZcGQTFrlUFVlSqte1x7lJnuW7jj7 UW1WGphJnViSsFZEcUSiYycMDXcQ9Tzreo0xJkmkjqvFIEgUOnlZIqCn5DDyKq8vZ5nuPIkT6Wq n47SJ20oR3Rodm8Zo1m3Ceae8fgjUfEcvf4tn3cl/BecB5gFYTZ94+T12XKkw0Lh4zfnTWxd3Od lch8V3i2sR52g9PmGf5gfPP0A+mqtarYQylLOL9H16BWSiXa X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA1MDA2NCBTYWx0ZWRfXzah2C89PB6w1 0h4OFoXgrszV76YbVdSsJ9mFjSJpnlkT4kRVNDIk7Oa7uBycDV5HN+ED0H2mBxYjsGvVn/QDBBZ 8eFpdyIfdgf1elNvhKNYcv5Fi0Iqt/wyl7tYxYVc9HyN1T84xHLKhQp+fRlYbAJXzC5MRVTzxNT vyBbktkrF6tTc8JBYzA8U/GNbA0KS5bOjL0hPNsphbl0YzdccJY6uBpPd74ZxSKuB+3ZekWRt6M 6RZc7lJ/kSfqMVpuEHtBr2KX7FV9nTiJefgIDl6XjJRxXmqOExzSdAiZfloSiuQaH6Jl/uP6W05 NynBz0KpYAlkdz4MATr6a9Lf5EoMLeDjmw2mAt6VWHKrmXmTT/maNC8PYGUkSAJqp79XXC5z9tL 3fCC8u4h3bSnCzvQte4g4s3UXngxore5wgKZlLxLuPZMHeRS3x7sPuwbVf3WVp47hBwpWzI8 X-Authority-Analysis: v=2.4 cv=dciA3WXe c=1 sm=1 tr=0 ts=6868f849 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=WrGWoQF6NLblfNs28g4A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: gCUI2ls75JKrjeOk9oNqXnVsxJqHHRIf X-Proofpoint-ORIG-GUID: gCUI2ls75JKrjeOk9oNqXnVsxJqHHRIf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_07,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507050064 Currently the msm driver creates an extra interim platform device for Imageon GPUs. This is not ideal, as the device doesn't have corresponding OF node. If the headless mode is used for newer GPUs, then the msm_use_mmu() function can not detect corresponding IOMMU devices. Also the DRM device (although it's headless) is created with modesetting flags being set. To solve all these issues, rework the way the Imageon devices are bound. Remove the interim device, don't register a component and instead use a cut-down version of the normal functions to probe or remove the driver. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 36 +++--------- drivers/gpu/drm/msm/msm_drv.c | 91 ++++++++++++++++++++------= ---- drivers/gpu/drm/msm/msm_drv.h | 4 ++ 3 files changed, 72 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 27dbbb3020812f6fb7cff85a4e77c4ee471df470..99c8d2f4e4b49fda912fa494293= 99cf207eccead 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -260,42 +260,22 @@ static const struct component_ops a3xx_ops =3D { .unbind =3D adreno_unbind, }; =20 -static void adreno_device_register_headless(void) -{ - /* on imx5, we don't have a top-level mdp/dpu node - * this creates a dummy node for the driver for that case - */ - struct platform_device_info dummy_info =3D { - .parent =3D NULL, - .name =3D "msm", - .id =3D -1, - .res =3D NULL, - .num_res =3D 0, - .data =3D NULL, - .size_data =3D 0, - .dma_mask =3D ~0, - }; - platform_device_register_full(&dummy_info); -} - static int adreno_probe(struct platform_device *pdev) { - - int ret; - - ret =3D component_add(&pdev->dev, &a3xx_ops); - if (ret) - return ret; - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) - adreno_device_register_headless(); + return msm_gpu_probe(pdev, &a3xx_ops); =20 - return 0; + return component_add(&pdev->dev, &a3xx_ops); } =20 static void adreno_remove(struct platform_device *pdev) { - component_del(&pdev->dev, &a3xx_ops); + struct msm_drm_private *priv =3D platform_get_drvdata(pdev); + + if (priv->kms_init) + component_del(&pdev->dev, &a3xx_ops); + else + msm_gpu_remove(pdev, &a3xx_ops); } =20 static void adreno_shutdown(struct platform_device *pdev) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index ce22d96033c8efe9210436eff8241f52d3c053bd..0ab005a7d5e99e46fe47c9e6451= 4434416898d20 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -57,7 +57,7 @@ module_param(modeset, bool, 0600); DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); =20 -static int msm_drm_uninit(struct device *dev) +static int msm_drm_uninit(struct device *dev, const struct component_ops *= gpu_ops) { struct platform_device *pdev =3D to_platform_device(dev); struct msm_drm_private *priv =3D platform_get_drvdata(pdev); @@ -84,7 +84,10 @@ static int msm_drm_uninit(struct device *dev) if (priv->kms) msm_drm_kms_uninit(dev); =20 - component_unbind_all(dev, ddev); + if (gpu_ops) + gpu_ops->unbind(dev, dev, NULL); + else + component_unbind_all(dev, ddev); =20 ddev->dev_private =3D NULL; drm_dev_put(ddev); @@ -92,7 +95,8 @@ static int msm_drm_uninit(struct device *dev) return 0; } =20 -static int msm_drm_init(struct device *dev, const struct drm_driver *drv) +static int msm_drm_init(struct device *dev, const struct drm_driver *drv, + const struct component_ops *gpu_ops) { struct msm_drm_private *priv =3D dev_get_drvdata(dev); struct drm_device *ddev; @@ -139,7 +143,10 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) dma_set_max_seg_size(dev, UINT_MAX); =20 /* Bind all our sub-components: */ - ret =3D component_bind_all(dev, ddev); + if (gpu_ops) + ret =3D gpu_ops->bind(dev, dev, NULL); + else + ret =3D component_bind_all(dev, ddev); if (ret) goto err_put_dev; =20 @@ -151,11 +158,6 @@ static int msm_drm_init(struct device *dev, const stru= ct drm_driver *drv) ret =3D msm_drm_kms_init(dev, drv); if (ret) goto err_msm_uninit; - } else { - /* valid only for the dummy headless case, where of_node=3DNULL */ - WARN_ON(dev->of_node); - ddev->driver_features &=3D ~DRIVER_MODESET; - ddev->driver_features &=3D ~DRIVER_ATOMIC; } =20 ret =3D drm_dev_register(ddev, 0); @@ -172,7 +174,7 @@ static int msm_drm_init(struct device *dev, const struc= t drm_driver *drv) return 0; =20 err_msm_uninit: - msm_drm_uninit(dev); + msm_drm_uninit(dev, gpu_ops); =20 return ret; =20 @@ -834,6 +836,28 @@ static const struct drm_driver msm_driver =3D { .patchlevel =3D MSM_VERSION_PATCHLEVEL, }; =20 +static const struct drm_driver msm_gpu_driver =3D { + .driver_features =3D DRIVER_GEM | + DRIVER_RENDER | + DRIVER_SYNCOBJ_TIMELINE | + DRIVER_SYNCOBJ, + .open =3D msm_open, + .postclose =3D msm_postclose, + .gem_prime_import_sg_table =3D msm_gem_prime_import_sg_table, +#ifdef CONFIG_DEBUG_FS + .debugfs_init =3D msm_debugfs_init, +#endif + .show_fdinfo =3D msm_show_fdinfo, + .ioctls =3D msm_ioctls, + .num_ioctls =3D ARRAY_SIZE(msm_ioctls), + .fops =3D &fops, + .name =3D "msm", + .desc =3D "MSM Snapdragon DRM", + .major =3D MSM_VERSION_MAJOR, + .minor =3D MSM_VERSION_MINOR, + .patchlevel =3D MSM_VERSION_PATCHLEVEL, +}; + /* * Componentized driver support: */ @@ -958,12 +982,12 @@ static int add_gpu_components(struct device *dev, =20 static int msm_drm_bind(struct device *dev) { - return msm_drm_init(dev, &msm_driver); + return msm_drm_init(dev, &msm_driver, NULL); } =20 static void msm_drm_unbind(struct device *dev) { - msm_drm_uninit(dev); + msm_drm_uninit(dev, NULL); } =20 const struct component_master_ops msm_drm_ops =3D { @@ -1012,29 +1036,34 @@ int msm_drv_probe(struct device *master_dev, return 0; } =20 -/* - * Platform driver: - * Used only for headlesss GPU instances - */ - -static int msm_pdev_probe(struct platform_device *pdev) +int msm_gpu_probe(struct platform_device *pdev, + const struct component_ops *ops) { - return msm_drv_probe(&pdev->dev, NULL, NULL); + struct msm_drm_private *priv; + int ret; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + + /* on all devices that I am aware of, iommu's which can map + * any address the cpu can see are used: + */ + ret =3D dma_set_mask_and_coherent(&pdev->dev, ~0); + if (ret) + return ret; + + return msm_drm_init(&pdev->dev, &msm_gpu_driver, ops); } =20 -static void msm_pdev_remove(struct platform_device *pdev) +void msm_gpu_remove(struct platform_device *pdev, + const struct component_ops *ops) { - component_master_del(&pdev->dev, &msm_drm_ops); + msm_drm_uninit(&pdev->dev, ops); } =20 -static struct platform_driver msm_platform_driver =3D { - .probe =3D msm_pdev_probe, - .remove =3D msm_pdev_remove, - .driver =3D { - .name =3D "msm", - }, -}; - static int __init msm_drm_register(void) { if (!modeset) @@ -1049,13 +1078,13 @@ static int __init msm_drm_register(void) adreno_register(); msm_mdp4_register(); msm_mdss_register(); - return platform_driver_register(&msm_platform_driver); + + return 0; } =20 static void __exit msm_drm_unregister(void) { DBG("fini"); - platform_driver_unregister(&msm_platform_driver); msm_mdss_unregister(); msm_mdp4_unregister(); msm_dp_unregister(); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 5b276a4540753aa25d46e50f0957790ed39474ae..e3dfaa156307dcd8bb675f86598= 5a0888be8fb87 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -543,6 +543,10 @@ extern const struct component_master_ops msm_drm_ops; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384c0558sm526274e87.209.2025.07.05.03.02.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jul 2025 03:02:47 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 05 Jul 2025 13:02:35 +0300 Subject: [PATCH v4 10/10] drm/msm: enable separate binding of GPU and display devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250705-msm-gpu-split-v4-10-fb470c481131@oss.qualcomm.com> References: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> In-Reply-To: <20250705-msm-gpu-split-v4-0-fb470c481131@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5219; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=fG270cxV/2q7kQa6T4r/dHwrEGN9NSQeGPoJADDDa3w=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoaPg0D8TLyxpxyMP5ZOm6f/GyJWsJzX6ZcuA4r FCYCYgTH++JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaGj4NAAKCRCLPIo+Aiko 1QvtB/0f5DxO5BvqdVoPXZaDjS6R3QfljCGAuivAD4aP8SahrZOkfS8yC5L+862G61Kl1A0QwoZ pOocaIuIDTdq3a2U7PP1gDB79IUrNh+Jj5YkWOqE0q2d+jiaVlcdhySbrYhXm3Nfwwbw79DKeBg r8J2pylstkUlBHQtdm2Z+0gLbp2cNQEISwi9xHI3cO8f6KVtAmYoPgbSJclsfyHnk65kB2qUo1K WVd+P+dJJgmrk/YI9ID0FrmiBvXoputJ5iXF0V75jZ6KK9QtWOGFiNml93xgpea+j8Xk/JkzaZd f/1Uz7I8ICTvR7k6pPB2lA5Vjf6xSTcKP41+AHWcspLFx+0k X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA1MDA2NCBTYWx0ZWRfX/sF92FPIgZVK uE7mnA8u5/9wPr6KWBRw34y38d1nckLYnwjSfmi3LHXltmyQthG+xnWhaBlj9j342nN13x86stn ES4IbVy0biaFXa7Cv1sBdYCEBh/MQUSOrP8bgs77CeBp9fmR04VZqd1F9g/jEh7pdzYpa8BZ9nF 78rSA4tDC9RZwrwxndeZpILyvwwcxbzhjwaM+2ZYRrQnTSyG3pcGGvhhXjTVtpFm+xhe9C4hk+d nfpNcCv+OzaPIaDBj6vWjoMtYQzuZhtJQPGbRbWyp6Ldnc+tJZ+uYntSMIT4BofbOPLIy1kyHze aMj0p52KMSb6e3TocKzP94dkQowdgh9Fz34IeWUlWwo0hxlEzxAZmsiJRmeEXAsj1aC7KBVaEIc SeSOO18eMxKkQrH5Tle6JDnSrxoz92km5EA3BO7tG47h4Gza6k/dhl7p2s9lyYp4F/X6xgEo X-Authority-Analysis: v=2.4 cv=dciA3WXe c=1 sm=1 tr=0 ts=6868f84a cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=d3EbUlffPpwbv2rupc8A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: mVHgRqlullSjfvm6IOlKDp-_hXftw5Lu X-Proofpoint-ORIG-GUID: mVHgRqlullSjfvm6IOlKDp-_hXftw5Lu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_07,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507050064 There are cases when we want to have separate DRM devices for GPU and display pipelines. One example is development, when it is beneficial to be able to bind the GPU driver separately, without the display pipeline (and without the hacks adding "amd,imageon" to the compatible string). Another example is some of Qualcomm platforms, which have two MDSS units, but only one GPU. With current approach it is next to impossible to support this usecase properly, while separate binding allows users to have three DRM devices: two for MDSS units and a single headless GPU. Add kernel param msm.separate_gpu_drm, which if set to true forces creation of separate display and GPU DRM devices. Mesa supports this setup by using the kmsro wrapper. The param is disabled by default, in order to be able to test userspace for the compatibility issues. Simple clients are able to handle this setup automatically. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +- drivers/gpu/drm/msm/msm_drv.c | 47 ++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 47 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 99c8d2f4e4b49fda912fa49429399cf207eccead..50945bfe9b4992118f23db3cd17= ac348be9f9c9d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -262,7 +262,8 @@ static const struct component_ops a3xx_ops =3D { =20 static int adreno_probe(struct platform_device *pdev) { - if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) + if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") || + msm_gpu_no_components()) return msm_gpu_probe(pdev, &a3xx_ops); =20 return component_add(&pdev->dev, &a3xx_ops); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 0ab005a7d5e99e46fe47c9e64514434416898d20..2966ba086b2cdb3232a7fa0445b= 953787cfad2b0 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -54,9 +54,18 @@ static bool modeset =3D true; MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=3Don (default),= 0=3Ddisable)"); module_param(modeset, bool, 0600); =20 +static bool separate_gpu_drm; +MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0= =3Dsingle DRM device for both GPU and display (default), 1=3Dtwo DRM device= s)"); +module_param(separate_gpu_drm, bool, 0400); + DECLARE_FAULT_ATTR(fail_gem_alloc); DECLARE_FAULT_ATTR(fail_gem_iova); =20 +bool msm_gpu_no_components(void) +{ + return separate_gpu_drm; +} + static int msm_drm_uninit(struct device *dev, const struct component_ops *= gpu_ops) { struct platform_device *pdev =3D to_platform_device(dev); @@ -836,6 +845,30 @@ static const struct drm_driver msm_driver =3D { .patchlevel =3D MSM_VERSION_PATCHLEVEL, }; =20 +static const struct drm_driver msm_kms_driver =3D { + .driver_features =3D DRIVER_GEM | + DRIVER_ATOMIC | + DRIVER_MODESET, + .open =3D msm_open, + .postclose =3D msm_postclose, + .dumb_create =3D msm_gem_dumb_create, + .dumb_map_offset =3D msm_gem_dumb_map_offset, + .gem_prime_import_sg_table =3D msm_gem_prime_import_sg_table, +#ifdef CONFIG_DEBUG_FS + .debugfs_init =3D msm_debugfs_init, +#endif + MSM_FBDEV_DRIVER_OPS, + .show_fdinfo =3D msm_show_fdinfo, + .ioctls =3D msm_ioctls, + .num_ioctls =3D ARRAY_SIZE(msm_ioctls), + .fops =3D &fops, + .name =3D "msm-kms", + .desc =3D "MSM Snapdragon DRM", + .major =3D MSM_VERSION_MAJOR, + .minor =3D MSM_VERSION_MINOR, + .patchlevel =3D MSM_VERSION_PATCHLEVEL, +}; + static const struct drm_driver msm_gpu_driver =3D { .driver_features =3D DRIVER_GEM | DRIVER_RENDER | @@ -982,7 +1015,11 @@ static int add_gpu_components(struct device *dev, =20 static int msm_drm_bind(struct device *dev) { - return msm_drm_init(dev, &msm_driver, NULL); + return msm_drm_init(dev, + msm_gpu_no_components() ? + &msm_kms_driver : + &msm_driver, + NULL); } =20 static void msm_drm_unbind(struct device *dev) @@ -1018,9 +1055,11 @@ int msm_drv_probe(struct device *master_dev, return ret; } =20 - ret =3D add_gpu_components(master_dev, &match); - if (ret) - return ret; + if (!msm_gpu_no_components()) { + ret =3D add_gpu_components(master_dev, &match); + if (ret) + return ret; + } =20 /* on all devices that I am aware of, iommu's which can map * any address the cpu can see are used: diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e3dfaa156307dcd8bb675f865985a0888be8fb87..9875ca62e9adb12dca9bcc74e28= 25b0364372a54 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -554,4 +554,6 @@ void msm_kms_shutdown(struct platform_device *pdev); =20 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); =20 +bool msm_gpu_no_components(void); + #endif /* __MSM_DRV_H__ */ --=20 2.39.5