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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384ba7aesm524758e87.205.2025.07.05.02.55.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jul 2025 02:55:24 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 05 Jul 2025 12:55:19 +0300 Subject: [PATCH] iommu/arm-smmu: disable PRR on some of SMMU-500 platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250705-iommu-fix-prr-v1-1-ef725033651c@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAIb2aGgC/x2MQQqAMAzAviI9W+jUKfgV8aCuag/T0aEIsr87P IaQvBBZhSP0xQvKt0Q5jwymLGDZp2NjFJcZKqosdWRRTu8vXOXBoIotUWPNbFxNDeQmKGf1/4Y xpQ8xpLz/XwAAAA== X-Change-ID: 20250705-iommu-fix-prr-600451b1d304 To: Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Bibek Kumar Patro Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10232; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=JGeBWNQ7SOUaSfLmBoBeYMzuXj2s3WsyaN23v9zFEIk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoaPaKIp4CP7PdrUdGM0f7ikogTsm54Xj4B8Ly/ 667pqXwivCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaGj2igAKCRCLPIo+Aiko 1TcMB/0YzadNI5OfscFm2/tsfVF/roOdhAwrj2xq47UPIKm2lX84xxhCD9BUPSpvpa4CI14tkuG BDFllzG6FQ4IOkM3QVwgMUM/xSZoyRYtkYerIWS0kw+RvSNM3wBc+KAr5K+yCVaB7QDbkUje64C z3oWcyjdHQ11J089A7Kpq4Iq3tQqAWM0VOOm6r6FyluezFKGfa2FbrjjI41HQatMghTbKoMXZm1 vM3yX40xhnuP4dQhVCEjv5bl+DGcJN3tPXfGrNy8LnkTYip39OG7yf4TY3Q186q56OEkCH9nd7K eYhDOR7EUhoAD5GuN0ijtzp/s6MrFqBQ/vAbtLk5+bOJ/rVi X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA1MDA2MyBTYWx0ZWRfX+/IF+Pi69A/s 0wJQ6Ld/tVZY3MaCDkijcw5Iy0+eH0sP0803Gp+UZ60GtvdVyouznJmgfafFI5mBNzPJXheAr9l LtCV+K6ocNKoCJf6gTOXRaHsJ0PF0ET5rCRWWuno+H1WKQINX/m04A7NdqWmBekhoB9uKxV2U5a 9GybSDezZzfu1CKKDjQf6fFUNM+BphXS+QnLVekzT3JBjIzW9A9Bi3QlMk9Bv2CFUFca8se1sQX zg9OZRtsmMeLyuRoiuHG8/khRqY8VK9G0VGUpQ5X4fkIebL6iUWSoTF58PZsvLu75bxt8iasxHl Vf+zERq3UtIaWY0LhvKQaq0vP4wBnNKO704PmP++fGew+C/VgxVoJuy/xwfdTZtI03K9ua2crn/ 9PRme87PtTsZwtzQmpoQYYgXLbejql9EqlEtHuWwPK5C/w+RHB6R8RVgFyrdSEy7cpn8MDKB X-Proofpoint-GUID: 9ifrXHX5N2iGE3cAmmAhDrVRYz7zpJA4 X-Proofpoint-ORIG-GUID: 9ifrXHX5N2iGE3cAmmAhDrVRYz7zpJA4 X-Authority-Analysis: v=2.4 cv=SOBCVPvH c=1 sm=1 tr=0 ts=6868f68f cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=XLurikqG2CS-mm0B5QcA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_07,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 bulkscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507050063 On some of the platforms (e.g. SM8250 / QRB5165-RB5) using PRR bits resets the device, most likely because of the hyp limitations. Disable PRR support on that platform. Instead of adding more compatible checks, set PRR-related callbacks through the match data, making it easier for other platforms to apply the same workaround. Fixes: 7f2ef1bfc758 ("iommu/arm-smmu: Add support for PRR bit setup") Signed-off-by: Dmitry Baryshkov --- I currently don't have access to other devices from these generations. It might be necessary to apply the same workaround to other platforms. --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 134 ++++++++++++++++++-------= ---- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 11 ++- 2 files changed, 91 insertions(+), 54 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 62874b18f6459ad9a8b0542ab81c24e3e745c53d..f1cb30cd99af6020a8b472f11d4= 999ad70d0bce0 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -55,6 +55,11 @@ static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_de= vice *smmu) return container_of(smmu, struct qcom_smmu, smmu); } =20 +static const struct qcom_smmu_impl *to_qcom_smmu_impl(const struct arm_smm= u_impl *base) +{ + return container_of(base, struct qcom_smmu_impl, base); +} + static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, int sync, int status) { @@ -313,9 +318,9 @@ static void qcom_smmu_set_actlr_dev(struct device *dev,= struct arm_smmu_device * static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_doma= in, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { - const struct device_node *np =3D smmu_domain->smmu->dev->of_node; struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct qcom_smmu *qsmmu =3D to_qcom_smmu(smmu); + const struct qcom_smmu_impl *qsmmu_impl =3D to_qcom_smmu_impl(smmu->impl); const struct of_device_id *client_match; int cbndx =3D smmu_domain->cfg.cbndx; struct adreno_smmu_priv *priv; @@ -351,14 +356,8 @@ static int qcom_adreno_smmu_init_context(struct arm_sm= mu_domain *smmu_domain, priv->set_ttbr0_cfg =3D qcom_adreno_smmu_set_ttbr0_cfg; priv->get_fault_info =3D qcom_adreno_smmu_get_fault_info; priv->set_stall =3D qcom_adreno_smmu_set_stall; - priv->set_prr_bit =3D NULL; - priv->set_prr_addr =3D NULL; - - if (of_device_is_compatible(np, "qcom,smmu-500") && - of_device_is_compatible(np, "qcom,adreno-smmu")) { - priv->set_prr_bit =3D qcom_adreno_smmu_set_prr_bit; - priv->set_prr_addr =3D qcom_adreno_smmu_set_prr_addr; - } + priv->set_prr_bit =3D qsmmu_impl->set_prr_bit; + priv->set_prr_addr =3D qsmmu_impl->set_prr_addr; =20 return 0; } @@ -558,65 +557,89 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_= device *smmu) return ret; } =20 -static const struct arm_smmu_impl qcom_smmu_v2_impl =3D { - .init_context =3D qcom_smmu_init_context, - .cfg_probe =3D qcom_smmu_cfg_probe, - .def_domain_type =3D qcom_smmu_def_domain_type, - .write_s2cr =3D qcom_smmu_write_s2cr, - .tlb_sync =3D qcom_smmu_tlb_sync, +static const struct qcom_smmu_impl qcom_smmu_v2_impl =3D { + .base =3D { + .init_context =3D qcom_smmu_init_context, + .cfg_probe =3D qcom_smmu_cfg_probe, + .def_domain_type =3D qcom_smmu_def_domain_type, + .write_s2cr =3D qcom_smmu_write_s2cr, + .tlb_sync =3D qcom_smmu_tlb_sync, + }, }; =20 -static const struct arm_smmu_impl qcom_smmu_500_impl =3D { - .init_context =3D qcom_smmu_init_context, - .cfg_probe =3D qcom_smmu_cfg_probe, - .def_domain_type =3D qcom_smmu_def_domain_type, - .reset =3D arm_mmu500_reset, - .write_s2cr =3D qcom_smmu_write_s2cr, - .tlb_sync =3D qcom_smmu_tlb_sync, +static const struct qcom_smmu_impl qcom_smmu_500_impl =3D { + .base =3D { + .init_context =3D qcom_smmu_init_context, + .cfg_probe =3D qcom_smmu_cfg_probe, + .def_domain_type =3D qcom_smmu_def_domain_type, + .reset =3D arm_mmu500_reset, + .write_s2cr =3D qcom_smmu_write_s2cr, + .tlb_sync =3D qcom_smmu_tlb_sync, #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG - .context_fault =3D qcom_smmu_context_fault, - .context_fault_needs_threaded_irq =3D true, + .context_fault =3D qcom_smmu_context_fault, + .context_fault_needs_threaded_irq =3D true, #endif + }, }; =20 -static const struct arm_smmu_impl sdm845_smmu_500_impl =3D { - .init_context =3D qcom_smmu_init_context, - .cfg_probe =3D qcom_smmu_cfg_probe, - .def_domain_type =3D qcom_smmu_def_domain_type, - .reset =3D qcom_sdm845_smmu500_reset, - .write_s2cr =3D qcom_smmu_write_s2cr, - .tlb_sync =3D qcom_smmu_tlb_sync, +static const struct qcom_smmu_impl sdm845_smmu_500_impl =3D { + .base =3D { + .init_context =3D qcom_smmu_init_context, + .cfg_probe =3D qcom_smmu_cfg_probe, + .def_domain_type =3D qcom_smmu_def_domain_type, + .reset =3D qcom_sdm845_smmu500_reset, + .write_s2cr =3D qcom_smmu_write_s2cr, + .tlb_sync =3D qcom_smmu_tlb_sync, #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG - .context_fault =3D qcom_smmu_context_fault, - .context_fault_needs_threaded_irq =3D true, + .context_fault =3D qcom_smmu_context_fault, + .context_fault_needs_threaded_irq =3D true, #endif + }, +}; + +static const struct qcom_smmu_impl qcom_adreno_smmu_v2_impl =3D { + .base =3D { + .init_context =3D qcom_adreno_smmu_init_context, + .cfg_probe =3D qcom_adreno_smmuv2_cfg_probe, + .def_domain_type =3D qcom_smmu_def_domain_type, + .alloc_context_bank =3D qcom_adreno_smmu_alloc_context_bank, + .write_sctlr =3D qcom_adreno_smmu_write_sctlr, + .tlb_sync =3D qcom_smmu_tlb_sync, + .context_fault_needs_threaded_irq =3D true, + }, }; =20 -static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl =3D { - .init_context =3D qcom_adreno_smmu_init_context, - .cfg_probe =3D qcom_adreno_smmuv2_cfg_probe, - .def_domain_type =3D qcom_smmu_def_domain_type, - .alloc_context_bank =3D qcom_adreno_smmu_alloc_context_bank, - .write_sctlr =3D qcom_adreno_smmu_write_sctlr, - .tlb_sync =3D qcom_smmu_tlb_sync, - .context_fault_needs_threaded_irq =3D true, +static const struct qcom_smmu_impl qcom_adreno_smmu_500_noprr_impl =3D { + .base =3D { + .init_context =3D qcom_adreno_smmu_init_context, + .def_domain_type =3D qcom_smmu_def_domain_type, + .reset =3D arm_mmu500_reset, + .alloc_context_bank =3D qcom_adreno_smmu_alloc_context_bank, + .write_sctlr =3D qcom_adreno_smmu_write_sctlr, + .tlb_sync =3D qcom_smmu_tlb_sync, + .context_fault_needs_threaded_irq =3D true, + }, }; =20 -static const struct arm_smmu_impl qcom_adreno_smmu_500_impl =3D { - .init_context =3D qcom_adreno_smmu_init_context, - .def_domain_type =3D qcom_smmu_def_domain_type, - .reset =3D arm_mmu500_reset, - .alloc_context_bank =3D qcom_adreno_smmu_alloc_context_bank, - .write_sctlr =3D qcom_adreno_smmu_write_sctlr, - .tlb_sync =3D qcom_smmu_tlb_sync, - .context_fault_needs_threaded_irq =3D true, +static const struct qcom_smmu_impl qcom_adreno_smmu_500_impl =3D { + .base =3D { + .init_context =3D qcom_adreno_smmu_init_context, + .def_domain_type =3D qcom_smmu_def_domain_type, + .reset =3D arm_mmu500_reset, + .alloc_context_bank =3D qcom_adreno_smmu_alloc_context_bank, + .write_sctlr =3D qcom_adreno_smmu_write_sctlr, + .tlb_sync =3D qcom_smmu_tlb_sync, + .context_fault_needs_threaded_irq =3D true, + }, + .set_prr_bit =3D qcom_adreno_smmu_set_prr_bit, + .set_prr_addr =3D qcom_adreno_smmu_set_prr_addr, }; =20 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *sm= mu, const struct qcom_smmu_match_data *data) { const struct device_node *np =3D smmu->dev->of_node; - const struct arm_smmu_impl *impl; + const struct qcom_smmu_impl *impl; struct qcom_smmu *qsmmu; =20 if (!data) @@ -639,7 +662,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct = arm_smmu_device *smmu, if (!qsmmu) return ERR_PTR(-ENOMEM); =20 - qsmmu->smmu.impl =3D impl; + qsmmu->smmu.impl =3D &impl->base; qsmmu->data =3D data; =20 return &qsmmu->smmu; @@ -686,6 +709,13 @@ static const struct qcom_smmu_match_data qcom_smmu_500= _impl0_data =3D { .client_match =3D qcom_smmu_actlr_client_of_match, }; =20 +static const struct qcom_smmu_match_data qcom_smmu_500_impl0_noprr_data = =3D { + .impl =3D &qcom_smmu_500_impl, + .adreno_impl =3D &qcom_adreno_smmu_500_noprr_impl, + .cfg =3D &qcom_smmu_impl0_cfg, + .client_match =3D qcom_smmu_actlr_client_of_match, +}; + /* * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they= need * special handling and can not be covered by the qcom,smmu-500 entry. @@ -712,7 +742,7 @@ static const struct of_device_id __maybe_unused qcom_sm= mu_impl_of_match[] =3D { { .compatible =3D "qcom,sm6375-smmu-500", .data =3D &qcom_smmu_500_impl0_= data }, { .compatible =3D "qcom,sm7150-smmu-v2", .data =3D &qcom_smmu_v2_data }, { .compatible =3D "qcom,sm8150-smmu-500", .data =3D &qcom_smmu_500_impl0_= data }, - { .compatible =3D "qcom,sm8250-smmu-500", .data =3D &qcom_smmu_500_impl0_= data }, + { .compatible =3D "qcom,sm8250-smmu-500", .data =3D &qcom_smmu_500_impl0_= noprr_data }, { .compatible =3D "qcom,sm8350-smmu-500", .data =3D &qcom_smmu_500_impl0_= data }, { .compatible =3D "qcom,sm8450-smmu-500", .data =3D &qcom_smmu_500_impl0_= data }, { .compatible =3D "qcom,smmu-500", .data =3D &qcom_smmu_500_impl0_data }, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.h index 8addd453f5f1c9659fbfbc68a84a3ab1267b356e..e805ad604339463b706a43e359c= cca657d42a602 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -24,10 +24,17 @@ struct qcom_smmu_config { const u32 *reg_offset; }; =20 +struct qcom_smmu_impl { + struct arm_smmu_impl base; + + void (*set_prr_bit)(const void *cookie, bool set); + void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr); +}; + struct qcom_smmu_match_data { const struct qcom_smmu_config *cfg; - const struct arm_smmu_impl *impl; - const struct arm_smmu_impl *adreno_impl; + const struct qcom_smmu_impl *impl; + const struct qcom_smmu_impl *adreno_impl; const struct of_device_id * const client_match; }; =20 --- base-commit: 7244e36657076b597ac21d118be9c0b0f15fc622 change-id: 20250705-iommu-fix-prr-600451b1d304 Best regards, --=20 With best wishes Dmitry