From nobody Tue Oct 7 23:11:00 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52F282E5B0E for ; Fri, 4 Jul 2025 18:23:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751653419; cv=none; b=rFek+XamjVBGFQ14KGrRLjpff/Q9gWXzDZBTVTcPbhLzJdRUzbjSFPgI3qnDoZfq1qwKME9fqA7T4fWuhd+Egn+ZOXxpCr2/t1jACk39Poii/Y+WD1ewyvKau+YS3nVjO7DNkzcc9shPXsY5eJwkhZ5PIIN2/vRX0g5pa8K6qoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751653419; c=relaxed/simple; bh=QDnDb76IB5cOO7Oj5BeJE57yrKBAbkTyH3I1FS1TFms=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=swlaPYvIpqYSpMtOwGY4B7xTm/ASwN0HnOAZotNWZOvb28oCbh7MIVcrcikHGt1aTpsy+Wf0lrOULVpQ05JJcYm0ROr/5A9YkBpQC3xpjNJbARm/eyLtTizIqWcVhcXpy2yaluHNqSOgPu5odArNdnbQce276noEmMkLz6k+kyo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=eS9r6DZm; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="eS9r6DZm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751653416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UsJURyjjbtHkbrtJZhJxshTMpqcubkZSbmM3PovDAa8=; b=eS9r6DZmTc4RDFjXLyOZUdC6sw5oWJAfCy8NqQ/9qiP5Yf9ausj+i6QUjwEGwhVZM2FAo0 FPOYVDLAL+fsTo/FrO1+4Y92H2/sQLFyonZ1waESZwhRy45hJ9xy1C2MbqZu+nwaGaKNvp zD38Dpbl9hUmqjeXYIT7cgaYS9ZMWBg= Received: from mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-647-Z43aqMSxNAqY29FMbpkLSA-1; Fri, 04 Jul 2025 14:23:33 -0400 X-MC-Unique: Z43aqMSxNAqY29FMbpkLSA-1 X-Mimecast-MFC-AGG-ID: Z43aqMSxNAqY29FMbpkLSA_1751653410 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 9473E1955EC6; Fri, 4 Jul 2025 18:23:30 +0000 (UTC) Received: from p16v.redhat.com (unknown [10.45.226.37]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 9EB9219560A7; Fri, 4 Jul 2025 18:23:23 +0000 (UTC) From: Ivan Vecera To: Jiri Pirko , netdev@vger.kernel.org Cc: Prathosh Satish , Vadim Fedorenko , Arkadiusz Kubalewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Jason Gunthorpe , Shannon Nelson , Dave Jiang , Jonathan Cameron , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Michal Schmidt , Petr Oros Subject: [PATCH net-next v13 10/12] dpll: zl3073x: Add support to get/set priority on input pins Date: Fri, 4 Jul 2025 20:22:00 +0200 Message-ID: <20250704182202.1641943-11-ivecera@redhat.com> In-Reply-To: <20250704182202.1641943-1-ivecera@redhat.com> References: <20250704182202.1641943-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" Add support for getting and setting input pin priority. Implement required callbacks and set appropriate capability for input pins. Although the pin priority make sense only if the DPLL is running in automatic mode we have to expose this capability unconditionally because input pins (references) are shared between all DPLLs where one of them can run in automatic mode while the other one not. Co-developed-by: Prathosh Satish Signed-off-by: Prathosh Satish Signed-off-by: Ivan Vecera --- drivers/dpll/zl3073x/dpll.c | 88 +++++++++++++++++++++++++++++++++++++ drivers/dpll/zl3073x/prop.c | 1 + 2 files changed, 89 insertions(+) diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index 70c452a877ef4..406b3e48f2518 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -287,6 +287,56 @@ zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin= , u8 *prio) return rc; } =20 +/** + * zl3073x_dpll_ref_prio_set - set priority for given input pin + * @pin: pointer to pin + * @prio: place to store priority + * + * Sets priority for the given input pin. + * + * Return: 0 on success, <0 on error + */ +static int +zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio) +{ + struct zl3073x_dpll *zldpll =3D pin->dpll; + struct zl3073x_dev *zldev =3D zldpll->dev; + u8 ref, ref_prio; + int rc; + + guard(mutex)(&zldev->multiop_lock); + + /* Read DPLL configuration into mailbox */ + rc =3D zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, + ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); + if (rc) + return rc; + + /* Read reference priority - one value shared between P&N pins */ + ref =3D zl3073x_input_pin_ref_get(pin->id); + rc =3D zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio); + if (rc) + return rc; + + /* Update nibble according pin type */ + if (zl3073x_dpll_is_p_pin(pin)) { + ref_prio &=3D ~ZL_DPLL_REF_PRIO_REF_P; + ref_prio |=3D FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); + } else { + ref_prio &=3D ~ZL_DPLL_REF_PRIO_REF_N; + ref_prio |=3D FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); + } + + /* Update reference priority */ + rc =3D zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio); + if (rc) + return rc; + + /* Commit configuration */ + return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR, + ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); +} + /** * zl3073x_dpll_ref_state_get - get status for given input pin * @pin: pointer to pin @@ -400,6 +450,42 @@ zl3073x_dpll_input_pin_state_on_dpll_set(const struct = dpll_pin *dpll_pin, return rc; } =20 +static int +zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin= _priv, + const struct dpll_device *dpll, void *dpll_priv, + u32 *prio, struct netlink_ext_ack *extack) +{ + struct zl3073x_dpll_pin *pin =3D pin_priv; + + *prio =3D pin->prio; + + return 0; +} + +static int +zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin= _priv, + const struct dpll_device *dpll, void *dpll_priv, + u32 prio, struct netlink_ext_ack *extack) +{ + struct zl3073x_dpll_pin *pin =3D pin_priv; + int rc; + + if (prio > ZL_DPLL_REF_PRIO_MAX) + return -EINVAL; + + /* If the pin is selectable then update HW registers */ + if (pin->selectable) { + rc =3D zl3073x_dpll_ref_prio_set(pin, prio); + if (rc) + return rc; + } + + /* Save priority */ + pin->prio =3D prio; + + return 0; +} + static int zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, void *pin_priv, @@ -493,6 +579,8 @@ zl3073x_dpll_mode_get(const struct dpll_device *dpll, v= oid *dpll_priv, =20 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops =3D { .direction_get =3D zl3073x_dpll_pin_direction_get, + .prio_get =3D zl3073x_dpll_input_pin_prio_get, + .prio_set =3D zl3073x_dpll_input_pin_prio_set, .state_on_dpll_get =3D zl3073x_dpll_input_pin_state_on_dpll_get, .state_on_dpll_set =3D zl3073x_dpll_input_pin_state_on_dpll_set, }; diff --git a/drivers/dpll/zl3073x/prop.c b/drivers/dpll/zl3073x/prop.c index c3224e78cbf01..4cf7e8aefcb37 100644 --- a/drivers/dpll/zl3073x/prop.c +++ b/drivers/dpll/zl3073x/prop.c @@ -205,6 +205,7 @@ struct zl3073x_pin_props *zl3073x_pin_props_get(struct = zl3073x_dev *zldev, if (dir =3D=3D DPLL_PIN_DIRECTION_INPUT) { props->dpll_props.type =3D DPLL_PIN_TYPE_EXT; props->dpll_props.capabilities =3D + DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; } else { props->dpll_props.type =3D DPLL_PIN_TYPE_GNSS; --=20 2.49.0