From nobody Tue Oct 7 22:38:30 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 76F4E2D836C for ; Fri, 4 Jul 2025 17:38:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751650734; cv=none; b=FoSEqneZs/KtaZAJ2eP6xfGFVEHnO5Jd9nId3EL6VcCKuXBhTuBo7OLyE0wExLEfKjotjSyc7pva7MJNiqLSNgo5cIpe3o9oZR6K89YuEPr/qyR1OOFXOEZVHG2+P4xMjpLfnV1vHnYCe3O8OiGhF1b8FG7laKhRxBdbiWuteHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751650734; c=relaxed/simple; bh=DeyYRSfQ/lwQqK11+x5uwOymJAVJfjFoaJqop4D4/wY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Npk2Z9PsyQYGPomIMfvXq9Jx9Sml7FGQ07+lVUgayptg5GufApkpxlSQnjx9BqPYHIMYrCWXAFsqiIVnrrCtJb707glZcmGoVe73HQclBMHmHo+d2aUZhg3suCUAYKv2w1UG22In800mqxk3Em0pqeICbW5rjzg4AN9cDoHS4d4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D83652A31; Fri, 4 Jul 2025 10:38:37 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2F0A23F66E; Fri, 4 Jul 2025 10:38:50 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , Jonathan Cameron , Catalin Marinas , WillDeaconwill@kernel.org, James Morse Subject: [PATCH v2 1/3] cacheinfo: Set cache 'id' based on DT data Date: Fri, 4 Jul 2025 17:38:24 +0000 Message-Id: <20250704173826.13025-2-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250704173826.13025-1-james.morse@arm.com> References: <20250704173826.13025-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rob Herring Use the minimum CPU h/w id of the CPUs associated with the cache for the cache 'id'. This will provide a stable id value for a given system. As we need to check all possible CPUs, we can't use the shared_cpu_map which is just online CPUs. As there's not a cache to CPUs mapping in DT, we have to walk all CPU nodes and then walk cache levels. The cache_id exposed to user-space has historically been 32 bits, and is too late to change. This value is parsed into a u32 by user-space libraries such as libvirt: https://github.com/libvirt/libvirt/blob/master/src/util/virresctrl.c#L1588 Give up on assigning cache-id's if a CPU h/w id greater than 32 bits is found. Cc: Greg Kroah-Hartman Cc: "Rafael J. Wysocki" Signed-off-by: Rob Herring [ ben: converted to use the __free cleanup idiom ] Signed-off-by: Ben Horgan [ morse: Add checks to give up if a value larger than 32 bits is seen. ] Signed-off-by: James Morse Reviewed-by: Gavin Shan Reviewed-by: Jonathan Cameron --- Use as a 32bit value has also been seen in DPDK patches here: http://inbox.dpdk.org/dev/20241021015246.304431-2-wathsala.vithanage@arm.co= m/ Changes since v1: * Remove the second loop in favour of a helper. =20 An open question from v1 is whether it would be preferable to use an index into the DT of the CPU nodes instead of the hardware id. This would save an arch specific swizzle - but the numbers would change if the DT were changed. This scheme isn't sensitive to the order of DT nodes. --- drivers/base/cacheinfo.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index cf0d455209d7..df593da0d5f7 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -8,6 +8,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include +#include #include #include #include @@ -183,6 +184,42 @@ static bool cache_node_is_unified(struct cacheinfo *th= is_leaf, return of_property_read_bool(np, "cache-unified"); } =20 +static bool match_cache_node(struct device_node *cpu, + const struct device_node *cache_node) +{ + for (struct device_node *cache __free(device_node) =3D of_find_next_cache= _node(cpu); + cache !=3D NULL; cache =3D of_find_next_cache_node(cache)) { + if (cache =3D=3D cache_node) + return true; + } + + return false; +} + +static void cache_of_set_id(struct cacheinfo *this_leaf, + struct device_node *cache_node) +{ + struct device_node *cpu; + u32 min_id =3D ~0; + + for_each_of_cpu_node(cpu) { + u64 id =3D of_get_cpu_hwid(cpu, 0); + + if (FIELD_GET(GENMASK_ULL(63, 32), id)) { + of_node_put(cpu); + return; + } + + if (match_cache_node(cpu, cache_node)) + min_id =3D min(min_id, id); + } + + if (min_id !=3D ~0) { + this_leaf->id =3D min_id; + this_leaf->attributes |=3D CACHE_ID; + } +} + static void cache_of_set_props(struct cacheinfo *this_leaf, struct device_node *np) { @@ -198,6 +235,7 @@ static void cache_of_set_props(struct cacheinfo *this_l= eaf, cache_get_line_size(this_leaf, np); cache_nr_sets(this_leaf, np); cache_associativity(this_leaf); + cache_of_set_id(this_leaf, np); } =20 static int cache_setup_of_node(unsigned int cpu) --=20 2.39.5 From nobody Tue Oct 7 22:38:30 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9F7762DEA99 for ; Fri, 4 Jul 2025 17:38:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751650736; cv=none; b=G+bqP2UBIQ7seSCOlJrl0tvcypFC9AA0m5KA+5GtiqShQ5/89jq0UUlqczL3cM3k/EWb6bJSCP685snR2pbPDXr3k/6RK7kupTIq5nj5Q9v77351n6xgpX4mp3eUtg/vGeWXMA5YejBc5ibR1PTfT7BH2Pf/Kcb5cXRf/mL1xkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751650736; c=relaxed/simple; bh=Y8Ao9VFKOGm4s0rrTv5ueK7YLyz/32omxIZkTsEdhcU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fkFkEdYxR431TCEuLHJJUzLF6k93QSC9pN4d4DH8XsoSKpJkaGRAwjpxqliCYteU2SDkM8+IxhJNEkt0v47fLL6GK78FawSXhMtxThTaKmJxZThGyME5CIxfaa2LAV2BbYmot6ntknluY5P+u0b8NmA0zIETzWdKBsT5zanIl50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1B0CC2A2A; Fri, 4 Jul 2025 10:38:40 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 652783F66E; Fri, 4 Jul 2025 10:38:52 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , Jonathan Cameron , Catalin Marinas , WillDeaconwill@kernel.org, James Morse Subject: [PATCH v2 2/3] cacheinfo: Add arch hook to compress CPU h/w id into 32 bits for cache-id Date: Fri, 4 Jul 2025 17:38:25 +0000 Message-Id: <20250704173826.13025-3-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250704173826.13025-1-james.morse@arm.com> References: <20250704173826.13025-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Filesystems like resctrl use the cache-id exposed via sysfs to identify groups of CPUs. The value is also used for PCIe cache steering tags. On DT platforms cache-id is not something that is described in the device-tree, but instead generated from the smallest CPU h/w id of the CPUs associated with that cache. CPU h/w ids may be larger than 32 bits. Add a hook to allow architectures to compress the value from the devicetree into 32 bits. Returning the same value is always safe as cache_of_set_id() will stop if a value larger than 32 bits is seen. For example, on arm64 the value is the MPIDR affinity register, which only has 32 bits of affinity data, but spread accross the 64 bit field. An arch-specific bit swizzle gives a 32 bit value. Signed-off-by: James Morse Reviewed-by: Jonathan Cameron Reviewed-by: Gavin Shan --- drivers/base/cacheinfo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index df593da0d5f7..25d028f7a986 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -196,6 +196,10 @@ static bool match_cache_node(struct device_node *cpu, return false; } =20 +#ifndef arch_compact_of_hwid +#define arch_compact_of_hwid(_x) (_x) +#endif + static void cache_of_set_id(struct cacheinfo *this_leaf, struct device_node *cache_node) { @@ -205,6 +209,7 @@ static void cache_of_set_id(struct cacheinfo *this_leaf, for_each_of_cpu_node(cpu) { u64 id =3D of_get_cpu_hwid(cpu, 0); =20 + id =3D arch_compact_of_hwid(id); if (FIELD_GET(GENMASK_ULL(63, 32), id)) { of_node_put(cpu); return; --=20 2.39.5 From nobody Tue Oct 7 22:38:30 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E7C172E5B19 for ; Fri, 4 Jul 2025 17:38:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751650738; cv=none; b=jSfr1+Bjy3i0GjpSIjpEZxSP+1R5TLfb3KJhBZU/CfTNhm+VNn3k1j0/JVxDiMd4Houw/wHBVfR+VQYofntVhISI9DJg1r5swd6Bq9Q38zxCRl6C/MztMRWJ07I8BTvzfS2yiMlZSv3cLPFwzL0rAP4+cjhTS3NKemCTs7gXtoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751650738; c=relaxed/simple; bh=8tt1EdIBpAVCF3uj+plmzLIQTInEBU1xCp8xD8FtxRY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EWUVNvHAuSG/V0ZsQHcjanNf6AwI0Aa7aaGXZ6TD2Kd5f5R3ZqtNA4/7w4D8bfVK7bCoV/XCHEQeBgf2JP7NAhFWpPjbgpJnNRJMkoDAGMqp47jR/S8p68wIHwdvLGRkRxRC0PRgD9CiNhqV7BTtUxd4RlT4cfy2+fbJ9xDhx8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B39D302D; Fri, 4 Jul 2025 10:38:42 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C6C873F66E; Fri, 4 Jul 2025 10:38:54 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , Jonathan Cameron , Catalin Marinas , WillDeaconwill@kernel.org, James Morse Subject: [PATCH v2 3/3] arm64: cacheinfo: Provide helper to compress MPIDR value into u32 Date: Fri, 4 Jul 2025 17:38:26 +0000 Message-Id: <20250704173826.13025-4-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250704173826.13025-1-james.morse@arm.com> References: <20250704173826.13025-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Filesystems like resctrl use the cache-id exposed via sysfs to identify groups of CPUs. The value is also used for PCIe cache steering tags. On DT platforms cache-id is not something that is described in the device-tree, but instead generated from the smallest MPIDR of the CPUs associated with that cache. The cache-id exposed to user-space has historically been 32 bits. MPIDR values may be larger than 32 bits. MPIDR only has 32 bits worth of affinity data, but the aff3 field lives above 32bits. The corresponding lower bits are masked out by MPIDR_HWID_BITMASK and contain an SMT flag and Uni-Processor flag. Swizzzle the aff3 field into the bottom 32 bits and using that. In case more affinity fields are added in the future, the upper RES0 area should be checked. Returning a value greater than 32 bits from this helper will cause the caller to give up on allocating cache-ids. Signed-off-by: James Morse Reviewed-by: Jonathan Cameron Reviewed-by: Gavin Shan --- Changes since v1: * Removal of unrelated changes. * Added a comment about how the RES0 bit safety net works. --- arch/arm64/include/asm/cache.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 99cd6546e72e..09963004ceea 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -87,6 +87,23 @@ int cache_line_size(void); =20 #define dma_get_cache_alignment cache_line_size =20 +/* Compress a u64 MPIDR value into 32 bits. */ +static inline u64 arch_compact_of_hwid(u64 id) +{ + u64 aff3 =3D MPIDR_AFFINITY_LEVEL(id, 3); + + /* + * These bits are expected to be RES0. If not, return a value with + * the upper 32 bits set to force the caller to give up on 32 bit + * cache ids. + */ + if (FIELD_GET(GENMASK_ULL(63, 40), id)) + return id; + + return (aff3 << 24) | FIELD_GET(GENMASK_ULL(23, 0), id); +} +#define arch_compact_of_hwid arch_compact_of_hwid + /* * Read the effective value of CTR_EL0. * --=20 2.39.5