From nobody Wed Oct 8 00:04:33 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D32A110942; Fri, 4 Jul 2025 15:58:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751644737; cv=none; b=Cx5cypBz7BeFBUfJMTnTNYrWIu6kTg4QBgvp1vfFg2wMYeN0UW8PHZopF2ReCtNzPouY+kgFE07za5V1F/b+1m/zr/eVotuhwgUzlaI+hQTQFrKpfdK9Ho6WaNqpRzfdVTLN49hxuAiWJ+jotESOkE2r3wdcK5e76VOE8JCmWOE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751644737; c=relaxed/simple; bh=Nbk7wLUjKq6J0X2SsBVO1EIU0vl1bFOUl6PqsjqzXFk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dHlPLUyl8Ciy3JsSt2FNg33J4EqZhtQ1uVkV5jvt0UWY8jST/aK8Kme4xPUtJkpb/timnagPnSpDsV9inZ6+dhG4q3/8VJ6+8HxFQgVCmONu0ByxJKk9oaaSXMQQGle9u7bHuPooGcW/7fJVU6XRuAdrb0GERzw+yrJmvhqnlGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id AD8F21F0003D; Fri, 4 Jul 2025 15:58:53 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 58433ACA6A1; Fri, 4 Jul 2025 15:50:36 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.64]) by laika.paulk.fr (Postfix) with ESMTP id E94BAACA657; Fri, 4 Jul 2025 15:46:35 +0000 (UTC) From: Paul Kocialkowski To: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Yong Deng , Paul Kocialkowski , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Maxime Ripard , Paul Kocialkowski Subject: [PATCH v8 5/9] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Date: Fri, 4 Jul 2025 17:46:22 +0200 Message-ID: <20250704154628.3468793-6-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250704154628.3468793-1-paulk@sys-base.io> References: <20250704154628.3468793-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul Kocialkowski MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge controller. The controller uses a separate D-PHY, which is the same that is otherwise used for MIPI DSI, but used in Rx mode. On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does not have access to any parallel interface pins. Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to support the MIPI CSI-2 interface. Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 even when no sensor is connected. This will result in a probe failure for the controller as long as no sensor is connected but this is fine since no other interface is available. The interconnects property is used to inherit the proper DMA offset. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts= /allwinner/sun8i-v3s.dtsi index 02d6c62b3874..bfe02295f45d 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -671,6 +671,77 @@ gic: interrupt-controller@1c81000 { interrupts =3D ; }; =20 + csi0: camera@1cb0000 { + compatible =3D "allwinner,sun8i-v3s-csi"; + reg =3D <0x01cb0000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names =3D "bus", "mod", "ram"; + resets =3D <&ccu RST_BUS_CSI>; + interconnects =3D <&mbus 5>; + interconnect-names =3D "dma-mem"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + csi0_in_mipi_csi2: endpoint { + remote-endpoint =3D <&mipi_csi2_out_csi0>; + }; + }; + }; + }; + + mipi_csi2: csi@1cb1000 { + compatible =3D "allwinner,sun8i-v3s-mipi-csi2", + "allwinner,sun6i-a31-mipi-csi2"; + reg =3D <0x01cb1000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_CSI>; + status =3D "disabled"; + + phys =3D <&dphy>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mipi_csi2_in: port@0 { + reg =3D <0>; + }; + + mipi_csi2_out: port@1 { + reg =3D <1>; + + mipi_csi2_out_csi0: endpoint { + remote-endpoint =3D <&csi0_in_mipi_csi2>; + }; + }; + }; + }; + + dphy: d-phy@1cb2000 { + compatible =3D "allwinner,sun6i-a31-mipi-dphy"; + reg =3D <0x01cb2000 0x1000>; + clocks =3D <&ccu CLK_BUS_CSI>, + <&ccu CLK_MIPI_CSI>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_CSI>; + allwinner,direction =3D "rx"; + status =3D "disabled"; + #phy-cells =3D <0>; + }; + csi1: camera@1cb4000 { compatible =3D "allwinner,sun8i-v3s-csi"; reg =3D <0x01cb4000 0x3000>; --=20 2.49.0