From nobody Tue Oct 7 22:24:59 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 981112DCF60; Fri, 4 Jul 2025 07:54:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751615682; cv=none; b=sqeFAoA1efgBho3e/Yzg/c6027Hj6hDSLNYG7vqtHURmn7JzJmhJfrU3hTsgFwIjHInoVcChr6Ic1vvOOq9Hqr1dzAKzNqE5B2Dbr86pZmwxfsqEpUWf+39jDsib8bH0t0YSm92h2hEjv4rkDqV89rC/ZtQ55Ma8uL5/U0QmT7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751615682; c=relaxed/simple; bh=mwU7btKAyZ9cAsrqBTZ0SjxXjFYhGz4ex9bDeH7DjAw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kzUaJ3zxs7gsolxq43pSzf8a6QvDnaKDEfZBN+oczplGvMG84R1v7pWDjLGK5mW3XwW2762BIds4LmHBt5UY2jvuzNZPNEEj1niL5r/MrmL2ndoUATYAHFOOmi6nABzzlT+d5r72Td1TLDIa/zuTc0ZpFF4skEjwZ9ABVdSNRuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hhmDBvUy; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hhmDBvUy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751615680; x=1783151680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mwU7btKAyZ9cAsrqBTZ0SjxXjFYhGz4ex9bDeH7DjAw=; b=hhmDBvUyPmVdcvZe46Akoxv65+I151vLTzXdI8XssN1w/ILV0em2OaPt J+4M/hFR0PfLSzO9pJPWqjcWmEMZHZCstaUjb/e+f+I5W/MXF6qDaA9Mx nGs4FKJQ9Sh1iShF7CtyE5GWce+eACO0B3LOOW9h6wyfHFT/wAQ4CjKs0 3hE05k2BWdmcMWzhyANHsL88+iQLLzWFzzskjXjzdNYgS/7xlgGjHL+Id nz2kF3z6Jdq7K8Unm1YdyQInEUUbBozlTcbJUnblatGEjqy/1GXL+8f1Z Dpl5hyU+nD5acaXza6G4b+zd74YazxQeRvWTAG9BP5NYpiSJhyALFMAbu w==; X-CSE-ConnectionGUID: hmHGdZ4yQYWNkO7d76rjSA== X-CSE-MsgGUID: 7JpYItX3Rxe47G2J49VzCw== X-IronPort-AV: E=McAfee;i="6800,10657,11483"; a="57621134" X-IronPort-AV: E=Sophos;i="6.16,286,1744095600"; d="scan'208";a="57621134" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2025 00:54:33 -0700 X-CSE-ConnectionGUID: zCcdiXaSQWWvpz/h0rYQqg== X-CSE-MsgGUID: m7spTVa2Qo6iAT4/Fz/Dhw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,286,1744095600"; d="scan'208";a="154663990" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2025 00:54:30 -0700 From: Qiuxu Zhuo To: Tony Luck , Borislav Petkov Cc: Qiuxu Zhuo , VikasX Chougule , James Morse , Mauro Carvalho Chehab , Robert Richter , Lili Li , Laurens SEGHERS , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] EDAC/i10nm: Add Intel Granite Rapids-D support Date: Fri, 4 Jul 2025 23:16:07 +0800 Message-ID: <20250704151609.7833-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250704151609.7833-1-qiuxu.zhuo@intel.com> References: <20250704151609.7833-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Granite Rapids-D CPU model uses memory controller registers similar to those of the Granite Rapids server CPU but with a different memory controller MMIO base. Add the Granite Rapids-D CPU model ID and use the new memory controller MMIO base for EDAC support. Tested-by: VikasX Chougule Signed-off-by: Qiuxu Zhuo --- drivers/edac/i10nm_base.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index a3fca2567752..c1e45c16f70e 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -62,6 +62,7 @@ ((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000) =20 #define I10NM_GNR_IMC_MMIO_OFFSET 0x24c000 +#define I10NM_GNR_D_IMC_MMIO_OFFSET 0x206000 #define I10NM_GNR_IMC_MMIO_SIZE 0x4000 #define I10NM_HBM_IMC_MMIO_SIZE 0x9000 #define I10NM_DDR_IMC_CH_CNT(reg) GET_BITFIELD(reg, 21, 24) @@ -687,6 +688,14 @@ static struct pci_dev *get_gnr_mdev(struct skx_dev *d,= int logical_idx, int *phy return NULL; } =20 +static u32 get_gnr_imc_mmio_offset(void) +{ + if (boot_cpu_data.x86_vfm =3D=3D INTEL_GRANITERAPIDS_D) + return I10NM_GNR_D_IMC_MMIO_OFFSET; + + return I10NM_GNR_IMC_MMIO_OFFSET; +} + /** * get_ddr_munit() - Get the resource of the i-th DDR memory controller. * @@ -715,7 +724,7 @@ static struct pci_dev *get_ddr_munit(struct skx_dev *d,= int i, u32 *offset, unsi return NULL; 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charset="utf-8" From: Lili Li Intel Wildcat Lake is a mobile derivative of Panther Lake with one memory controller. Wildcat Lake SoCs share the same IBECC registers with Meteor Lake-P SoCs. Add a compute die ID and a new configuration structure for Wildcat Lake SoCs with In-Band ECC capability for EDAC support. Signed-off-by: Lili Li Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index 5ffe9579959f..2fc59f9eed69 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -275,6 +275,9 @@ static struct work_struct ecclog_work; #define DID_PTL_H_SKU2 0xb001 #define DID_PTL_H_SKU3 0xb002 =20 +/* Compute die IDs for Wildcat Lake with IBECC */ +#define DID_WCL_SKU1 0xfd00 + static int get_mchbar(struct pci_dev *pdev, u64 *mchbar) { union { @@ -569,6 +572,17 @@ static struct res_config mtl_p_cfg =3D { .err_addr_to_imc_addr =3D adl_err_addr_to_imc_addr, }; =20 +static struct res_config wcl_cfg =3D { + .machine_check =3D true, + .num_imc =3D 1, + .imc_base =3D 0xd800, + .ibecc_base =3D 0xd400, + .ibecc_error_log_offset =3D 0x170, + .ibecc_available =3D mtl_p_ibecc_available, + .err_addr_to_sys_addr =3D adl_err_addr_to_sys_addr, + .err_addr_to_imc_addr =3D adl_err_addr_to_imc_addr, +}; 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charset="utf-8" Intel Raptor Lake-HX SoC shares the same memory controller registers as Raptor Lake-S SoC. Add a compute die ID for Raptor Lake-HX SoCs with Out-of-Band ECC capability for EDAC support. Signed-off-by: Qiuxu Zhuo Tested-by: Laurens SEGHERS --- drivers/edac/ie31200_edac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c index d9533ca25635..5c1fa1c0d12e 100644 --- a/drivers/edac/ie31200_edac.c +++ b/drivers/edac/ie31200_edac.c @@ -94,6 +94,9 @@ #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5 0xa740 /* 8P+12E, e.g. i7-1470= 0 */ #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6 0xa704 /* 6P+8E, e.g. i5-1460= 0 */ =20 +/* Raptor Lake-HX */ +#define PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1 0xa702 /* 8P+16E, e.g. i9-139= 50HX */ + /* Alder Lake-S */ #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1 0x4660 =20 @@ -756,6 +759,7 @@ static const struct pci_device_id ie31200_pci_tbl[] =3D= { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4), (kernel_ulong_= t)&rpl_s_cfg}, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5), (kernel_ulong_= t)&rpl_s_cfg}, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6), (kernel_ulong_= t)&rpl_s_cfg}, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1), (kernel_ulong= _t)&rpl_s_cfg}, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1), (kernel_ulong_= t)&rpl_s_cfg}, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_1), (kernel_ulong_= t)&rpl_s_cfg}, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_2), (kernel_ulong_= t)&rpl_s_cfg}, --=20 2.43.0