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([82.78.167.83]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-60fd3895ac7sm1084916a12.30.2025.07.04.06.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 06:43:36 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH 1/3] clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well Date: Fri, 4 Jul 2025 16:43:26 +0300 Message-ID: <20250704134328.3614317-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250704134328.3614317-1-claudiu.beznea.uj@bp.renesas.com> References: <20250704134328.3614317-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea If MSTOP is not added for both clocks in a coupled pair, and the clocks are not disabled in the reverse order of their enable sequence, the MSTOP may remain enabled when disabling the clocks. This happens because rzg2l_mod_clock_endisable() executes for coupled clocks only when a single clock from the pair is enabled. If one clock has no MSTOP defined, it can result in the MSTOP configuration being left active when the clocks are disabled out of order (i.e., not in the reverse order of enabling). Fixes: c49695952746 ("clk: renesas: r9a08g045: Drop power domain instantiat= ion") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a08g045-cpg.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 405907925bb7..ed0661997928 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -256,11 +256,13 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[= ] =3D { MSTOP(BUS_PERI_COM, BIT(4))), DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c,= 0, MSTOP(BUS_PERI_COM, BIT(2))), - DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c,= 0, 0), + DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c,= 0, + MSTOP(BUS_PERI_COM, BIT(2))), DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8= , 0), DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c,= 1, MSTOP(BUS_PERI_COM, BIT(3))), - DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c,= 1, 0), + DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c,= 1, + MSTOP(BUS_PERI_COM, BIT(3))), DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9= , 0), DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0, MSTOP(BUS_MCPU2, BIT(10))), --=20 2.43.0