From nobody Tue Oct 7 23:01:42 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A093F2F236A; Fri, 4 Jul 2025 10:10:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751623823; cv=none; b=Fm2MprP9xjvSTlCj7tRawK6f9A6pVZa1EW+McDZRPW3MFTnu977ROECnQknCtn3ByHkIGm8dOQ0/PlDBf9eKwuz2Xji0moJApFVBbSUYZKiPihId0Un4OUeqeT6mzQ5Mk/VnDDzrG3BBiwx3x+KEEE5+ifpjoskKI9jux72fcno= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751623823; c=relaxed/simple; bh=sgYT9MmYDSFN7NXja1D708xePMH0j5raSQXUK70USUc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dBD0lOoaOB/mVyS40PLTM9fTprUxsZuLn1TLUmo9f6H5sTtq48kgo9ACk06YYGjYSwKx/gMtoCJA4Em53khz5KvvqVAVkM0rA2zffh8MVgnCl31mP+cmHSgiil5MceBeL29iQLTNsIMH3TjOHTeKSBUUMSdleyXFHGz0lmS8hsY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mAH/ULnm; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mAH/ULnm" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 564AACBi267821; Fri, 4 Jul 2025 05:10:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751623812; bh=mhku16+L6UOMneh74gmOAB+C80CxnUV/UXbORcNGufQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mAH/ULnmNEKbaca8uVdM4uQuMnaezfAgA0nfn+1J/P2iXnz+iZE+vX9u5s6Kl0yyM y6c5j/Z8DCSUj2ONjbS1+el1KKMtSH/gtgp9OsFODb+lhrdmcyaVKsrWNiLLdEtRqk WpxdLHFPNrK0mP3sj232GKKWfhOS0kc4Licn53Es= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 564AACAW3289939 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 4 Jul 2025 05:10:12 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 4 Jul 2025 05:10:12 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 4 Jul 2025 05:10:12 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 564AABbQ2531794; Fri, 4 Jul 2025 05:10:12 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v6 1/4] arm64: dts: ti: Add bootph property to nodes at source for am62a Date: Fri, 4 Jul 2025 15:39:51 +0530 Message-ID: <20250704100954.2231853-2-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704100954.2231853-1-p-bhagat@ti.com> References: <20250704100954.2231853-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add bootph property directly into the original definitions of relevant nodes (e.g., power domains, USB controllers, and other peripherals) within their respective DTSI files (ex. main, mcu, and wakeup) for am62a. By defining bootph in the nodes source definitions instead of appending it later in final DTS files, this change ensures that the property is inherently present wherever the nodes are reused across derived device trees. Signed-off-by: Paresh Bhagat Reviewed-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 2 ++ 2 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index 63e097ddf988..44e7e459f176 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -51,6 +51,7 @@ phy_gmii_sel: phy@4044 { compatible =3D "ti,am654-phy-gmii-sel"; reg =3D <0x4044 0x8>; #phy-cells =3D <1>; + bootph-all; }; =20 epwm_tbclk: clock-controller@4130 { @@ -96,6 +97,7 @@ secure_proxy_main: mailbox@4d000000 { #mbox-cells =3D <1>; interrupt-names =3D "rx_012"; interrupts =3D ; + bootph-all; }; =20 inta_main_dmss: interrupt-controller@48000000 { @@ -131,6 +133,7 @@ main_bcdma: dma-controller@485c0100 { ti,sci-rm-range-bchan =3D <0x20>; /* BLOCK_COPY_CHAN */ ti,sci-rm-range-rchan =3D <0x21>; /* SPLIT_TR_RX_CHAN */ ti,sci-rm-range-tchan =3D <0x22>; /* SPLIT_TR_TX_CHAN */ + bootph-all; }; =20 main_pktdma: dma-controller@485c0000 { @@ -147,6 +150,8 @@ main_pktdma: dma-controller@485c0000 { "ring", "tchan", "rchan", "rflow"; msi-parent =3D <&inta_main_dmss>; #dma-cells =3D <2>; + bootph-all; + ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <30>; ti,sci-rm-range-tchan =3D <0x23>, /* UNMAPPED_TX_CHAN */ @@ -220,16 +225,19 @@ dmsc: system-controller@44043000 { k3_pds: power-controller { compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; + bootph-all; }; =20 k3_clks: clock-controller { compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; + bootph-all; }; =20 k3_reset: reset-controller { compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; + bootph-all; }; }; =20 @@ -254,6 +262,7 @@ secure_proxy_sa3: mailbox@43600000 { * firmware on non-MPU processors */ status =3D "disabled"; + bootph-all; }; =20 main_pmx0: pinctrl@f4000 { @@ -282,6 +291,7 @@ main_timer0: timer@2400000 { assigned-clock-parents =3D <&k3_clks 36 3>; power-domains =3D <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; ti,timer-pwm; + bootph-all; }; =20 main_timer1: timer@2410000 { @@ -651,6 +661,7 @@ usb0: usb@31000000 { interrupt-names =3D "host", "peripheral"; maximum-speed =3D "high-speed"; dr_mode =3D "otg"; + bootph-all; snps,usb2-gadget-lpm-disable; snps,usb2-lpm-disable; }; @@ -745,6 +756,7 @@ cpsw_port1: port@1 { phys =3D <&phy_gmii_sel 1>; mac-address =3D [00 00 00 00 00 00]; ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; + bootph-all; }; =20 cpsw_port2: port@2 { @@ -764,6 +776,7 @@ cpsw3g_mdio: mdio@f00 { clocks =3D <&k3_clks 13 0>; clock-names =3D "fck"; bus_freq =3D <1000000>; + bootph-all; }; =20 cpts@3d000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index 259ae6ebbfb5..9ef1c829a9df 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -17,6 +17,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; =20 opp_efuse_table: syscon@18 { @@ -67,6 +68,7 @@ wkup_uart0: serial@0 { reg =3D <0 0x100>; interrupts =3D ; status =3D "disabled"; + bootph-pre-ram; }; }; =20 --=20 2.34.1 From nobody Tue Oct 7 23:01:42 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DE6A2F272E; Fri, 4 Jul 2025 10:10:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751623830; cv=none; b=QihNvLWTudmeL1CaThodHkyKx+UrfNuKrO3lQ7TeqDulyK+9k9JzCR9u3kHZAOgnNva095lkHtqQjYUGOEqZ/iomDuwg8asbF4q3DJ3NrKj4DTB9JVnNqJLkVCrXujsoXQQmzvU1qUgTDYW08ZjL4e6idPTx6ci86pBJNseeR7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751623830; c=relaxed/simple; bh=bJoKfALriuJO9Lf49jizcJsBXpk+qdh0vI2kCtIkqhk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Fri, 4 Jul 2025 05:10:15 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v6 2/4] dt-bindings: arm: ti: Add AM62D2 SoC and Boards Date: Fri, 4 Jul 2025 15:39:52 +0530 Message-ID: <20250704100954.2231853-3-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704100954.2231853-1-p-bhagat@ti.com> References: <20250704100954.2231853-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The AM62D2 SoC, part of the K3 architecture, is built for high-performance DSP tasks in automotive audio, pro audio, radar, sonar, and medical imaging. It features up to four Cortex-A53 cores (1.4GHz), two Cortex-R5F cores, and a C7x DSP with 2 TOPS MMA. Key interfaces include multi-channel McASP audio, TSN-capable Gigabit Ethernet, and a range of peripherals (UART, SPI, I2C, CAN, USB, eMMC/SD, OSPI, CSI). It supports LPDDR4/DDR4, secure boot with hardware security, and low-power modes with CAN/GPIO/UART wakeup. This SoC is of part K3 AM62x family, which includes the AM62A and AM62P variants. A key distinction is that the AM62D does not include multimedia components such as the video encoder/decoder, MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal processing, or the display subsystem. Additionally, the AM62D has a different pin configuration compared to the AM62A, which impacts embedded software development. This adds dt bindings for TI's AM62D2 family of devices. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/sprujd4 Signed-off-by: Paresh Bhagat Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index bf6003d8fb76..e80c653fa438 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 =20 + - description: K3 AM62D2 SoC and Boards + items: + - enum: + - ti,am62d2-evm + - const: ti,am62d2 + - description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra items: - const: phytec,am62a7-phyboard-lyra-rdk --=20 2.34.1 From nobody Tue Oct 7 23:01:42 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B9152F364B; Fri, 4 Jul 2025 10:10:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751623828; cv=none; b=le+x2sNIuGHhVmlCtzJ5mMfqW8YUKNfcuRGBJTvH27GLnMZGOErSAdE5VMwsaLzv5QzAPd2qdHmRaXx+WEQqvpwzd9NRVZ3BIoNHtY9Y2O7koN/yaJJbh+bl+qJKKVlb2Ss12Sq7d+3d2dIosbA5v092bghzB1+xEEPuFf8jCmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751623828; c=relaxed/simple; bh=1A9CY0H/kYTojtxll//4SQPbJ+jWznvduyifJPT4qpI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=skx9L22povhimR7wj5QIJVyWp3GOSJQmaD7P1t8bRAE9FvE2XCLZ2XmQOYFl/O3FCqm1I9CWMPZeX7v9YmPQP531/Q5qVZdCrPSM255n65iyN75xqqGGdjzjvfhcWVKpZiewuWyh+NvbYqm7buTGAw1bbkH8U6t1E6N1DcjrsrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=BFdL9HGP; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="BFdL9HGP" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 564AAJhW267849; Fri, 4 Jul 2025 05:10:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751623819; bh=2nB2XrYs3/yr4cfRNXfAXTu6rjkWvNQLgoMjODS48vE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BFdL9HGPpN5V88UlLISf4hdHgBc3sY2vH0tAyCbM5ovRHoyWh72W3scXAMbeOJgKn hWYiXxIe++bhulf7pSdU6TxYVPVwfizoPNKJFFxjfdkWgLgfaQlFEzIQcklmPCDYUL JfH3AgsEKiMSF2lmIBzEBcmUhF9zQxEXhGbbFZBU= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 564AAJwZ1272710 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 4 Jul 2025 05:10:19 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 4 Jul 2025 05:10:19 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 4 Jul 2025 05:10:19 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 564AAIML2532107; Fri, 4 Jul 2025 05:10:19 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v6 3/4] arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs Date: Fri, 4 Jul 2025 15:39:53 +0530 Message-ID: <20250704100954.2231853-4-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704100954.2231853-1-p-bhagat@ti.com> References: <20250704100954.2231853-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Update k3-pinctrl file to include pin definitions for AM62D2 family of SoCs. Signed-off-by: Paresh Bhagat Reviewed-by: Devarsh Thakkar --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index cac7cccc1112..0cf57179c974 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -63,6 +63,9 @@ #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) +#define AM62DX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) + #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 --=20 2.34.1 From nobody Tue Oct 7 23:01:42 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D2542F3C3F; Fri, 4 Jul 2025 10:10:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751623833; cv=none; b=J10d2CM3+dBC498Yl3fa/AtOk9ltuXAjIyAmYa+B8kHrSx0aHNtmhpq07qv9JZllbeswYFGI3XqkzNDPbXvn1y01mHM1fHZUi966PVesCg+pflTUFCWvY3kc1JSmBVpgcbfZdow8yEia+a5BlsffUR8nu/HHHpFK1zWu3HPsNRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751623833; c=relaxed/simple; bh=MQY1NJIxoNVuUAisMpTYjRf1PWumRsGAxPeRjxAmI3o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LOUk92qRYazShVTOqGfU2Ow9O9APFZucHRZvpIcBmsnY571+B45l3einwiluCEd+lF7UvzUmddz4WHWpj+dnS/EF7p/8SHWDisZr8/G3twlxrcYiJ4kQpWUE1JFK9ecIAk8WTL26ULdATI2p8X+eEiSYUn4DEfD+ZjirzFdFDEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=aAl72qWe; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="aAl72qWe" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 564AAO2J3799477; Fri, 4 Jul 2025 05:10:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751623824; bh=Ar7OaN6YNvkOK7IoC96I5XaZs+xgUztN7pvwFH61qAo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aAl72qWe6ehIpnWK8JqPcTGHE7gAzVcxscU3sYecRlpSFGp7CaSKB5MwGCGGgJiPQ qGjcjUYzD13JHRhgPGZijqseUH/zQln1cDAHzfqM85wHI79SRHfosJbiiKDKMi6435 ZfpWhYf5JkZZ+JQ/ymWzUzLvLa6tT9htG8l/TkbU= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 564AAOq41272752 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 4 Jul 2025 05:10:24 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 4 Jul 2025 05:10:23 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 4 Jul 2025 05:10:23 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 564AAMKn2532304; Fri, 4 Jul 2025 05:10:23 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v6 4/4] arm64: dts: ti: Add support for AM62D2-EVM Date: Fri, 4 Jul 2025 15:39:54 +0530 Message-ID: <20250704100954.2231853-5-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704100954.2231853-1-p-bhagat@ti.com> References: <20250704100954.2231853-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" AM62D-EVM evaluation module (EVM) is a low-cost expandable platform board designed for AM62D2 SoC from TI. It supports the following interfaces: * 4 GB LPDDR4 RAM * x2 Gigabit Ethernet expansion connectors * x4 3.5mm TRS Audio Jack Line In * x4 3.5mm TRS Audio Jack Line Out * x2 Audio expansion connectors * x1 Type-A USB 2.0, x1 Type-C dual-role device (DRD) USB 2.0 * x1 UHS-1 capable micro SD card slot * 32 GB eMMC Flash * 512 Mb OSPI NOR flash * x4 UARTs via USB 2.0-B * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs Although AM62D2 and AM62A7 differ in peripheral capabilities example multimedia, VPAC, and display subsystems, the core architecture remains same. To reduce duplication, AM62D support reuses the AM62A dtsi and the necessary overrides will be handled in SOC specific dtsi file and a board specific dts. Add basic support for AM62D2-EVM. Schematics Link - https://www.ti.com/lit/zip/sprcal5 Signed-off-by: Paresh Bhagat Signed-off-by: Siddharth Vadapalli Reviewed-by: Andrew Davis Reviewed-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/Makefile | 3 + arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 617 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62d2.dtsi | 20 + 3 files changed, 640 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62d2-evm.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am62d2.dtsi diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index c6171de9fe88..3da3a1d1dc33 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -33,6 +33,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-pocketbeagle2.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-phyboard-lyra-rdk.dtb =20 +# Boards with AM62Dx SoC +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62d2-evm.dtb + # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-verdin-nonwifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts new file mode 100644 index 000000000000..715a407bddd8 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -0,0 +1,617 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * AM62D2 EVM: https://www.ti.com/lit/zip/sprcal5 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am62d2.dtsi" + +/ { + compatible =3D "ti,am62d2-evm", "ti,am62d2"; + model =3D "Texas Instruments AM62D2 EVM"; + + aliases { + serial0 =3D &wkup_uart0; + serial1 =3D &mcu_uart0; + serial2 =3D &main_uart0; + mmc0 =3D &sdhci0; + mmc1 =3D &sdhci1; + rtc0 =3D &wkup_rtc0; + ethernet0 =3D &cpsw_port1; + ethernet1 =3D &cpsw_port2; + }; + + chosen { + stdout-path =3D &main_uart0; + }; + + memory@80000000 { + device_type =3D "memory"; + /* 4G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-all; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x00 0x2000000>; + alloc-ranges =3D <0x00 0xc0000000 0x00 0x2000000>; + linux,cma-default; + }; + + secure_tfa_ddr: tfa@80000000 { + reg =3D <0x00 0x80000000 0x00 0x80000>; + alignment =3D <0x1000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0xf00000>; + no-map; + bootph-pre-ram; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment =3D <0x1000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a0000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0000000 0x00 0x01000000>; + no-map; + }; + }; + + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + }; + }; + + vout_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vout_pd"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vmain_pd: regulator-1 { + /* Output of TPS22811 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vmain_pd"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vout_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_5v0: regulator-2 { + /* Output of TPS630702RNMR */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3v3_main: regulator-3 { + /* output of LM5141-Q1 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_main"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_mmc1: regulator-4 { + /* TPS22918DBVR */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpio =3D <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3v3_sys: regulator-5 { + /* output of TPS222965DSGT */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3v3_main>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vddshv_sdio: regulator-6 { + compatible =3D "regulator-gpio"; + regulator-name =3D "vddshv_sdio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vddshv_sdio_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + gpios =3D <&main_gpio1 31 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usr_led_pins_default>; + + led-0 { + label =3D "am62d-evm:green:heartbeat"; + gpios =3D <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + default-state =3D "off"; + }; + }; +}; + +&mcu_pmx0 { + status =3D "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + AM62DX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins =3D < + AM62DX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ + AM62DX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ + AM62DX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */ + AM62DX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ + >; + bootph-all; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; + status =3D "reserved"; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x01c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ + AM62DX_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ + >; + bootph-all; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ + AM62DX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C17) I2C1_SCL */ + AM62DX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (E17) I2C1_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (M22) GPMC0_CSn2.I2C2_SCL = */ + AM62DX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (M20) GPMC0_CSn3.I2C2_SDA = */ + >; + }; + + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */ + AM62DX_IOPAD(0x0218, PIN_OUTPUT, 0) /* (AB7) MMC0_CLK */ + AM62DX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */ + AM62DX_IOPAD(0x0210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */ + AM62DX_IOPAD(0x020c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */ + AM62DX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */ + AM62DX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */ + AM62DX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */ + AM62DX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */ + AM62DX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x023c, PIN_INPUT, 0) /* (C21) MMC1_CMD */ + AM62DX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (E22) MMC1_CLK */ + AM62DX_IOPAD(0x0230, PIN_INPUT, 0) /* (B22) MMC1_DAT0 */ + AM62DX_IOPAD(0x022c, PIN_INPUT, 0) /* (D21) MMC1_DAT1 */ + AM62DX_IOPAD(0x0228, PIN_INPUT, 0) /* (C22) MMC1_DAT2 */ + AM62DX_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62DX_IOPAD(0x0240, PIN_INPUT, 0) /* (E18) MMC1_SDCD */ + >; + bootph-all; + }; + + main_mdio0_pins_default: main-mdio0-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ + AM62DX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ + >; + bootph-all; + }; + + main_rgmii1_pins_default: main-rgmii1-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ + AM62DX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ + AM62DX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */ + AM62DX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */ + AM62DX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */ + AM62DX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */ + AM62DX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */ + AM62DX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */ + AM62DX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */ + AM62DX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */ + AM62DX_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */ + AM62DX_IOPAD(0x012c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */ + >; + bootph-all; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */ + AM62DX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */ + AM62DX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */ + AM62DX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */ + AM62DX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */ + AM62DX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */ + AM62DX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */ + AM62DX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */ + AM62DX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */ + AM62DX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */ + AM62DX_IOPAD(0x0168, PIN_OUTPUT, 0) /* (AB19) RGMII2_TXC */ + AM62DX_IOPAD(0x0164, PIN_OUTPUT, 0) /* (Y19) RGMII2_TX_CTL */ + >; + bootph-all; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ + >; + }; + + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x1f4, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO1_31 */ + >; + bootph-all; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x0244, PIN_INPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ + >; + }; +}; + +&mcu_gpio0 { + status =3D "okay"; +}; + +&main_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <400000>; + bootph-all; + status =3D "okay"; + + typec_pd0: usb-power-controller@3f { + compatible =3D "ti,tps6598x"; + reg =3D <0x3f>; + + connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + self-powered; + data-role =3D "dual"; + power-role =3D "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint =3D <&usb0_hs_ep>; + }; + }; + }; + }; + + exp1: gpio@22 { + compatible =3D "ti,tca6424"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; + + gpio-line-names =3D "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "","MMC1_SD_EN", + "VPP_EN", "GPIO_DIX_RST", + "IO_EXP_OPT_EN", "DIX_INT", + "GPIO_eMMC_RSTn", "CPLD2_DONE", + "CPLD2_INTN", "CPLD1_DONE", + "CPLD1_INTN", "USB_TYPEA_OC_INDICATION", + "PCM1_INT", "PCM2_INT", + "GPIO_PCM1_RST", "TEST_GPIO2", + "GPIO_PCM2_RST", "", + "IO_MCAN0_STB", "IO_MCAN1_STB", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + }; + + exp2: gpio@20 { + compatible =3D "ti,tca6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D "PCM6240_BUF_IO_EN", "", + "CPLD1_JTAGENB", "CPLD1_PROGRAMN", + "CPLD2_JTAGENB", "CPLD2_PROGRAMN", + "", "", + "", "CPLD1_TCK", + "CPLD1_TMS", "CPLD1_TDI", + "CPLD1_TDO", "CPLD2_TCK", + "CPLD2_TMS", "CPLD2_TDI", + "CPLD2_TDO", "ADDR1_IO_EXP", + "SoC_I2C0_SCL", "SoC_I2C0_SDA"; + }; +}; + +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&main_i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c2_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&sdhci0 { + /* eMMC */ + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mmc0_pins_default>; + bootph-all; + status =3D "okay"; +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vddshv_sdio>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mmc1_pins_default>; + disable-wp; + bootph-all; + status =3D "okay"; +}; + +&main_gpio0 { + bootph-all; + status =3D "okay"; +}; + +&main_gpio1 { + bootph-all; + status =3D "okay"; +}; + +&main_gpio_intr { + status =3D "okay"; +}; + +&main_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; + bootph-all; + status =3D "okay"; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint =3D <&usb_con_hs>; + }; + }; +}; + +&cpsw3g { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_rgmii1_pins_default>, + <&main_rgmii2_pins_default>; + status =3D "okay"; + + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps =3D <2 1>; + }; +}; + +&cpsw_port1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&cpsw3g_phy0>; + status =3D "okay"; +}; + +&cpsw_port2 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&cpsw3g_phy1>; + status =3D "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mdio0_pins_default>; + status =3D "okay"; + + cpsw3g_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@3 { + reg =3D <3>; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + bootph-pre-ram; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + firmware-name =3D "am62d-mcu-r5f0_0-fw"; + status =3D "okay"; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster1 &mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + firmware-name =3D "am62d-c71_0-fw"; + status =3D "okay"; +}; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status =3D "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62d2.dtsi b/arch/arm64/boot/dts/ti= /k3-am62d2.dtsi new file mode 100644 index 000000000000..1095515d3780 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62d2.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for AM62D2 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/pdf/sprujd4 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62a7.dtsi" + +/ { + model =3D "Texas Instruments K3 AM62D SoC"; + compatible =3D "ti,am62d2"; +}; + +/delete-node/ &vpu; /* Delete video codec node */ +/delete-node/ &e5010; /* Delete jpeg encoder node */ --=20 2.34.1