From nobody Tue Oct 7 23:01:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B0EC30AAC0 for ; Fri, 4 Jul 2025 08:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616989; cv=none; b=XWNtFWmC4QqSVWTyZ7mEv04O7AZfOwV2y2T8jjEKwT6iQ4b54sOCxVKbMrYafRiCj7VICEKVI0C8vJ33f91V2tuCoLJdkmads/jD6DAvFZibQF1CIbhTmCQEh/VNDO1/DhBKfGj64EZOKxxBjNbqJ65Ht3OOukFrzjjncRtPaSg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616989; c=relaxed/simple; bh=VbnAmLxBB+9ni3Y9B/gXoAlfLtNObeur1VJCWbvyhdM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KDANUTTfuXjylSLhJObFIPhjOcpz9bGdnb4luCLk19RS6HT/JVg16SaCO4NCYbsv4NqP7TKdGVdk70AzDtPkZbrm0yK8FcLOnM8u4o3AYAJqIJRIsuMQYoe4DuvCFPSI1bL23Bx5D0X+/EblZnBgDbIq8gf7kLgP3Y40GrhDh9A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5648EvxA091877 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Jul 2025 16:14:57 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 4 Jul 2025 16:14:56 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH 1/8] riscv: add Andes SoC family Kconfig support Date: Fri, 4 Jul 2025 16:14:44 +0800 Message-ID: <20250704081451.2011407-2-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704081451.2011407-1-ben717@andestech.com> References: <20250704081451.2011407-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5648EvxA091877 Content-Type: text/plain; charset="utf-8" The first SoC in the Andes series is QiLai. It includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. For further information, refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qil= ai-chip/ Signed-off-by: Ben Zong-You Xie --- arch/riscv/Kconfig.errata | 2 +- arch/riscv/Kconfig.socs | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e318119d570d..be76883704a6 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -12,7 +12,7 @@ config ERRATA_ANDES =20 config ERRATA_ANDES_CMO bool "Apply Andes cache management errata" - depends on ERRATA_ANDES && ARCH_R9A07G043 + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES) select RISCV_DMA_NONCOHERENT default y help diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a9c3d2f6debc..1bf5637f2601 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,14 @@ menu "SoC selection" =20 +config ARCH_ANDES + bool "Andes SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_ANDES + select ERRATA_ANDES_CMO + select AX45MP_L2_CACHE + help + This enables support for Andes SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP =20 --=20 2.34.1 From nobody Tue Oct 7 23:01:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1DFD2DBB25 for ; Fri, 4 Jul 2025 08:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616971; cv=none; b=JeAcYU9rGaeu0N3J2DTtiVOeyCXJD6ots7NkZHIEDsyZLz1bU6fW+vPIP0W+X7jk4XgADZMljJzlo2u/w1RtkP0Z4sKm5w16bWr81//fd1iqc3RCuaCw9plc/vIJ9diJXZvpQJO9uSO0ABGJ4iR1b8TqNG5gqbUF6lm9K7L5zvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616971; c=relaxed/simple; bh=zylAOvDJUdBHWCYEsmH/F3qbW1VoaC4/zwHAJ5vXbps=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LapZifXQyJfqHdZsri7rN/6hcooc3mxSjJdb7je5x2GidGSdYqZFo5mkHheMzQ5QqcFQs+G13pJAHoEjoQc4ZhPeVd23r8emjy3wCk51Jbjk9f3f/3ZE70lBcMRUKRJDrt1fDKbqFKC0I0vH9G0hawxp0EK3iE28+f2Hde5PXaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5648EwqC091878 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Jul 2025 16:14:58 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 4 Jul 2025 16:14:57 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH 2/8] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Date: Fri, 4 Jul 2025 16:14:45 +0800 Message-ID: <20250704081451.2011407-3-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704081451.2011407-1-ben717@andestech.com> References: <20250704081451.2011407-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5648EwqC091878 Content-Type: text/plain; charset="utf-8" Add DT binding documentation for the Andes QiLai SoC and the Voyager development board. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ben Zong-You Xie --- .../devicetree/bindings/riscv/andes.yaml | 25 +++++++++++++++++++ MAINTAINERS | 5 ++++ 2 files changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml diff --git a/Documentation/devicetree/bindings/riscv/andes.yaml b/Documenta= tion/devicetree/bindings/riscv/andes.yaml new file mode 100644 index 000000000000..aa1edf1fdec7 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/andes.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/andes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes SoC-based boards + +maintainers: + - Ben Zong-You Xie + +description: + Andes SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - andestech,voyager + - const: andestech,qilai + +additionalProperties: true diff --git a/MAINTAINERS b/MAINTAINERS index 6135a36a54a8..f4b4261d3c44 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21285,6 +21285,11 @@ F: drivers/irqchip/irq-riscv-intc.c F: include/linux/irqchip/riscv-aplic.h F: include/linux/irqchip/riscv-imsic.h =20 +RISC-V ANDES SoC Support +M: Ben Zong-You Xie +S: Maintained +F: Documentation/devicetree/bindings/riscv/andes.yaml + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt --=20 2.34.1 From nobody Tue Oct 7 23:01:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 319A92FD886 for ; Fri, 4 Jul 2025 08:16:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616969; cv=none; b=YdZcjXL9zkzg9AGZcHTVOStAH/myvdd657T0M3uzoQQq3QZ/uW6iSlHJycGVDil/Pjb0TWbOYHZWEjAkUGuOdqw5krGJvSOwrkh40yiiw44aOUVyEnEBw98eMxUJq8HqNoBnrtxSQjk8nKklbo1XwqFIgEkb7DeAY4hmJMWFyds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616969; c=relaxed/simple; bh=ouFEm89hCdrWb+Z8dVPbIyYMQBmtMRvDvolDrEMlw8g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fWXUO1dvA75D8tHpSP+GaGa2bC3YEpbxMaTeAGUNdGgSxVUxJxf9GF9uKijxiIfrPVsrf8qMgpbzjVibA/cubU5zcAlc2kVTMpKztOyb1PcSchsdKrqofJFWuUQKYOVCAmm3yB1S5+V864RiKy8FFG/Wh1UU6jgaA4Awy8Sjvnw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5648ExEM091879 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Jul 2025 16:14:59 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 4 Jul 2025 16:14:59 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH 3/8] dt-bindings: interrupt-controller: add Andes QiLai PLIC Date: Fri, 4 Jul 2025 16:14:46 +0800 Message-ID: <20250704081451.2011407-4-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704081451.2011407-1-ben717@andestech.com> References: <20250704081451.2011407-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5648ExEM091879 Content-Type: text/plain; charset="utf-8" Add a new compatible string for Andes QiLai PLIC. Acked-by: Rob Herring (Arm) Signed-off-by: Ben Zong-You Xie Reviewed-by: Lad Prabhakar --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index ffc4768bad06..5b827bc24301 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -53,6 +53,7 @@ properties: oneOf: - items: - enum: + - andestech,qilai-plic - renesas,r9a07g043-plic - const: andestech,nceplic100 - items: --=20 2.34.1 From nobody Tue Oct 7 23:01:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 390E730AAB8 for ; Fri, 4 Jul 2025 08:16:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616991; cv=none; b=BAI625Xg5N+qqFzVGgOotMhW12EnQCfLHItNBO5n8WCQsWJqzwHpl/ia7L7d2P8r0m2VDz07cG9Nm8GQcvZRtXAOkbEhLIX896zJ7mG7YloWWQnN2b/msgFbn3HcWrq40zOk6aIKwBAt1aCZFArEIP+tz7Q4N7h+DQrQXcJIWD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616991; c=relaxed/simple; bh=aKdC/fRJ+J6WHGQoAiIwXJ0mtHGxMv8NI/q7yo9xl6c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e0qpiXdjCBU7vEf6uQ7hJMpoYkoaNigfVvG/51WQ+si7fdvBmoyngvGZ9mBRFIKchaXFcNeOQzErhXrVl7C/nRRq7a0JWGSLT2eqAP7uD4bK6kM5E9Xua80/9rG3fdZ1rbcKXPsSYByXt+sRhCXFs5cWGD6OAOMFmvY/YrXyyj4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5648F0GA092007 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Jul 2025 16:15:00 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 4 Jul 2025 16:15:00 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH 4/8] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Date: Fri, 4 Jul 2025 16:14:47 +0800 Message-ID: <20250704081451.2011407-5-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704081451.2011407-1-ben717@andestech.com> References: <20250704081451.2011407-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5648F0GA092007 Content-Type: text/plain; charset="utf-8" Add the DT binding documentation for Andes machine-level software interrupt controller. In the Andes platform such as QiLai SoC, the PLIC module is instantiated a second time with all interrupt sources tied to zero as the software interrupt controller (PLICSW). PLICSW can generate machine-level software interrupts through programming its registers. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- .../andestech,plicsw.yaml | 54 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= andestech,plicsw.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/andeste= ch,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/and= estech,plicsw.yaml new file mode 100644 index 000000000000..eb2eb611ac09 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plic= sw.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes machine-level software interrupt controller + +description: + In the Andes platform such as QiLai SoC, the PLIC module is instantiated= a + second time with all interrupt sources tied to zero as the software inte= rrupt + controller (PLIC_SW). PLIC_SW directly connects to the machine-mode + inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interru= pt + controller is the parent interrupt controller for PLIC_SW. PLIC_SW can + generate machine-mode inter-processor interrupts through programming its + registers. + +maintainers: + - Ben Zong-You Xie + +properties: + compatible: + items: + - enum: + - andestech,qilai-plicsw + - const: andestech,plicsw + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 15872 + description: + Specifies which harts are connected to the PLIC_SW. Each item must p= oints + to a riscv,cpu-intc node, which has a riscv cpu node as parent. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@400000 { + compatible =3D "andestech,qilai-plicsw", "andestech,plicsw"; + reg =3D <0x400000 0x400000>; + interrupts-extended =3D <&cpu0intc 3>, + <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f4b4261d3c44..df309a360615 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21288,6 +21288,7 @@ F: include/linux/irqchip/riscv-imsic.h RISC-V ANDES SoC Support M: Ben Zong-You Xie S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw= .yaml F: Documentation/devicetree/bindings/riscv/andes.yaml =20 RISC-V ARCHITECTURE --=20 2.34.1 From nobody Tue Oct 7 23:01:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B77B42FF47A for ; Fri, 4 Jul 2025 08:16:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616976; cv=none; b=cv0z23GePo3aw643q8jq+1AuyVzP8fK0Nrx89K/1GTEaRHReSSy/Y7vfiF64znANh8Lcelx5BGNcqCH+GkZbKY6pQeg49w5BGxoRBombgkFxANnazUwmoG35/y4S4kkefd5t0nA/LEyhvv0wajcdg0g/o7Ai5f2UXFmzhBBhy8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616976; c=relaxed/simple; bh=DPzQSTJp/MgbbfE2UjHSoFsHM/mpFKBTXQhQWE9UqM8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f2TE1kcjHskqvKC1FuqQ5gZW3Un8+qdN4PlGIbDjKShg4DTgT+/0gpr1rpfLsQgcnV/tT6CTWkrK3eENpoYNn/iSzuTO0L8TOEWt07m3byrsV/66TtjQ4ohWSjV7oYtJmb+SjBmLLs/n6yaMWI1we3ecR0dmSug1SPPsdk4WlUE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5648F1xE092102 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Jul 2025 16:15:01 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 4 Jul 2025 16:15:01 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH 5/8] dt-bindings: timer: add Andes machine timer Date: Fri, 4 Jul 2025 16:14:48 +0800 Message-ID: <20250704081451.2011407-6-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704081451.2011407-1-ben717@andestech.com> References: <20250704081451.2011407-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5648F1xE092102 Content-Type: text/plain; charset="utf-8" Add the DT binding documentation for Andes machine timer. The RISC-V architecture defines a machine timer that provides a real-time counter and generates timer interrupts. Andes machiner timer (PLMT0) is the implementation of the machine timer, and it contains memory-mapped registers (mtime and mtimecmp). This device supports up to 32 cores. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- .../bindings/timer/andestech,plmt0.yaml | 53 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0= .yaml diff --git a/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml b= /Documentation/devicetree/bindings/timer/andestech,plmt0.yaml new file mode 100644 index 000000000000..90b612096004 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes machine-level timer + +description: + The Andes machine-level timer device (PLMT0) provides machine-level timer + functionality for a set of HARTs on a RISC-V platform. It has a single + fixed-frequency monotonic time counter (MTIME) register and a time compa= re + register (MTIMECMP) for each HART connected to the PLMT0. A timer interr= upt is + generated if MTIME >=3D MTIMECMP. + +maintainers: + - Ben Zong-You Xie + +properties: + compatible: + items: + - enum: + - andestech,qilai-plmt + - const: andestech,plmt0 + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 32 + description: + Specifies which harts are connected to the PLMT0. Each item must poi= nts + to a riscv,cpu-intc node, which has a riscv cpu node as parent. The + PLMT0 supports 1 hart up to 32 harts. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@100000 { + compatible =3D "andestech,qilai-plmt", "andestech,plmt0"; + reg =3D <0x100000 0x100000>; + interrupts-extended =3D <&cpu0intc 7>, + <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index df309a360615..07a7abc9729c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21290,6 +21290,7 @@ M: Ben Zong-You Xie S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw= .yaml F: Documentation/devicetree/bindings/riscv/andes.yaml +F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml =20 RISC-V ARCHITECTURE M: Paul Walmsley --=20 2.34.1 From nobody Tue Oct 7 23:01:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AEA72FD898 for ; Fri, 4 Jul 2025 08:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616971; cv=none; b=bIftGdqaqrTJWxdCuVbd6mP5JJ0hZ7n7UU60eU6KJ3nmPYAtEXnwe5AghZCr4F2YHGKmnOwDmmy+M4kq1vGwvF9QObop9OumD5HQpQXUpjJVQl6YcIGJRNWI4C8Ob53sigNcTn22Z87FbP76mwT6Zu1KawsJpngOBXRuXOm6drg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616971; c=relaxed/simple; bh=f0cWmRh8vEcOj3FBAwwVohl3BHuBe7namHx9h1hwwqk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tTpr1HkiXOir4T1aiIEE2wlGbfkTwwHfi5wwLK4U6+oqUHHmbkGKhsvYG3KlRah9iDOtlTUs/x8T62r4AC3qR9cAXC8aJywYezcM0QzPuO9XtRIeFbexslsWmueb32rtYktLHjggZq6BGj5j+zgi2a9Ea/Y6rYMKET49njOT5SM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5648F65U092211 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Jul 2025 16:15:06 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 4 Jul 2025 16:15:06 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH 6/8] riscv: dts: andes: add QiLai SoC device tree Date: Fri, 4 Jul 2025 16:14:49 +0800 Message-ID: <20250704081451.2011407-7-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704081451.2011407-1-ben717@andestech.com> References: <20250704081451.2011407-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5648F65U092211 Content-Type: text/plain; charset="utf-8" Introduce the initial device tree support for the Andes QiLai SoC. For further information, you can refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qil= ai-chip/ Signed-off-by: Ben Zong-You Xie --- MAINTAINERS | 2 + arch/riscv/boot/dts/andes/qilai.dtsi | 186 +++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 07a7abc9729c..ede4e21127f6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21288,9 +21288,11 @@ F: include/linux/irqchip/riscv-imsic.h RISC-V ANDES SoC Support M: Ben Zong-You Xie S: Maintained +T: git: https://github.com/ben717-linux/linux F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw= .yaml F: Documentation/devicetree/bindings/riscv/andes.yaml F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml +F: arch/riscv/boot/dts/andes/ =20 RISC-V ARCHITECTURE M: Paul Walmsley diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/and= es/qilai.dtsi new file mode 100644 index 000000000000..de3de32f8c39 --- /dev/null +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Andes Technology Corporation. All rights reserved. + */ + +/dts-v1/; + +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <62500000>; + + cpu0: cpu@0 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu0_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <1>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu1_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <2>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu2_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <3>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu3_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + plmt: timer@100000 { + compatible =3D "andestech,qilai-plmt", "andestech,plmt0"; + reg =3D <0x0 0x00100000 0x0 0x100000>; + interrupts-extended =3D <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + l2_cache: cache-controller@200000 { + compatible =3D "andestech,qilai-ax45mp-cache", + "andestech,ax45mp-cache", "cache"; + reg =3D <0x0 0x00200000 0x0 0x100000>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <0x200000>; + cache-unified; + }; + + plic_sw: interrupt-controller@400000 { + compatible =3D "andestech,qilai-plicsw", + "andestech,plicsw"; + reg =3D <0x0 0x00400000 0x0 0x400000>; + interrupts-extended =3D <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>; + }; + + plic: interrupt-controller@2000000 { + compatible =3D "andestech,qilai-plic", + "andestech,nceplic100"; + reg =3D <0x0 0x02000000 0x0 0x2000000>; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + riscv,ndev =3D <71>; + }; + + uart0: serial@30300000 { + compatible =3D "andestech,uart16550", "ns16550a"; + reg =3D <0x0 0x30300000 0x0 0x100000>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency =3D <50000000>; + reg-offset =3D <32>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + no-loopback-test; + }; + }; +}; --=20 2.34.1 From nobody Tue Oct 7 23:01:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BB092FD899 for ; Fri, 4 Jul 2025 08:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 4 Jul 2025 16:15:09 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 4 Jul 2025 16:15:09 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH 7/8] riscv: dts: andes: add Voyager board device tree Date: Fri, 4 Jul 2025 16:14:50 +0800 Message-ID: <20250704081451.2011407-8-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704081451.2011407-1-ben717@andestech.com> References: <20250704081451.2011407-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5648F9Wm092254 Content-Type: text/plain; charset="utf-8" Introduce the device tree support for Voyager development board. Currently only support booting into console with only uart, other features will be added later. Signed-off-by: Ben Zong-You Xie --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/andes/Makefile | 2 ++ arch/riscv/boot/dts/andes/qilai-voyager.dts | 28 +++++++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 arch/riscv/boot/dts/andes/Makefile create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 64a898da9aee..3b99e91efa25 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y +=3D allwinner +subdir-y +=3D andes subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas diff --git a/arch/riscv/boot/dts/andes/Makefile b/arch/riscv/boot/dts/andes= /Makefile new file mode 100644 index 000000000000..c545c668ef70 --- /dev/null +++ b/arch/riscv/boot/dts/andes/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ANDES) +=3D qilai-voyager.dtb diff --git a/arch/riscv/boot/dts/andes/qilai-voyager.dts b/arch/riscv/boot/= dts/andes/qilai-voyager.dts new file mode 100644 index 000000000000..fa7d2b32a9b4 --- /dev/null +++ b/arch/riscv/boot/dts/andes/qilai-voyager.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Andes Technology Corporation. All rights reserved. + */ + +#include "qilai.dtsi" + +/ { + model =3D "Voyager"; + compatible =3D "andestech,voyager", "andestech,qilai"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@400000000 { + device_type =3D "memory"; + reg =3D <0x4 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Tue Oct 7 23:01:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CCED30113D for ; Fri, 4 Jul 2025 08:16:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616977; cv=none; b=h1qsaIV3TywoGmoD8eOqY4RFUltycpMWQDgft7O615WXdE5qX6hfiBXh5w+rmJJ4Mi5Eb2fYcnsxx0Yx2bJhS60ifWk2TpKYFGKePX1A9c8ttmDONQAWmguBOz5e1dhleGLIWkozY5xBtcNNpERjFOQxJl5KcmQiva4YjWZiTfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751616977; c=relaxed/simple; bh=GI90PMG6oLQIFp7nu69CEzicczRXgBh1hr6PYZ2QH+4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Tpga1c6+vXzUl7rhiSisHFafz4U+2PCsEWo9vUdHvQRUOJRYnT3IDoWcIzqF6nyMnXyPo8ME9g0lMddLkTJGjBSUpej8xhVDEPM81Xf4YKFtuu1g4JEJH2jHWCO73RxiF3MdI5SJSjOCEiOalQ0AWKZ6e5qwDBMbj+ig8jj5Krk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5648FFiG092355 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Jul 2025 16:15:16 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 4 Jul 2025 16:15:15 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH 8/8] riscv: defconfig: enable Andes SoC Date: Fri, 4 Jul 2025 16:14:51 +0800 Message-ID: <20250704081451.2011407-9-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704081451.2011407-1-ben717@andestech.com> References: <20250704081451.2011407-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5648FFiG092355 Content-Type: text/plain; charset="utf-8" Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fe8bd8afb418..12f5f6ec00fa 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -22,6 +22,7 @@ CONFIG_USER_NS=3Dy CONFIG_CHECKPOINT_RESTORE=3Dy CONFIG_BLK_DEV_INITRD=3Dy CONFIG_PROFILING=3Dy +CONFIG_ARCH_ANDES=3Dy CONFIG_ARCH_MICROCHIP=3Dy CONFIG_ARCH_SIFIVE=3Dy CONFIG_ARCH_SOPHGO=3Dy --=20 2.34.1