From nobody Wed Oct 8 00:56:22 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5CB3207A18; Fri, 4 Jul 2025 04:23:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751603019; cv=none; b=JDEpNHETo1cwKhG/JJ42ertyDpNYeQUvx1b/JGX3mDpV6XVCGqw7YdAsj/EfyTnR4I4i2rn3AwjV8HpJeHecK31knX/iuG6+NQf9q0Ka8Ya+vibvRHZxBBwg1xQTDV/hIzd2L9dDkIvJHU/qEQqNL+vzvOcMZ5uYjXk9mAFHQWY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751603019; c=relaxed/simple; bh=m40pIlIO2wo0gnv2KOAZQPAYTnCzR21fSzFkg8x1DME=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OJJTECcI7Ijx8U43iSd6sHN67sPTHe2bLz/0hXyM1jcC/vlAOCOxYSDczy4uz4w2sY8BVM03mZJCZeR9u2pLr1Ha0bLOweNuxRHIzENGKvE48w3TyO966H2QZgo+th+w+416hAi3ezshbpw7Ron+FuQyNZVYF4xyR6Jethaxt5w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=b2fDgciE; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="b2fDgciE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751603018; x=1783139018; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m40pIlIO2wo0gnv2KOAZQPAYTnCzR21fSzFkg8x1DME=; b=b2fDgciEr34QazgtAfgtb55eEOAQWQmTtzHZzQEha50IKyI2qEi+arsP 19poKgVibgj7QBO6M31jDMdVUzs83uIb8XjiHc8HaXGRUc+ZP+GsdEYRj 6pOiy17R08ceX339cokwhJ6slgWBmGKtkaYGUIFRmmIei1yeT7f7yNl+c GYyztP2lNv2XeAm5nrv2rczh3c7tAAnRL1ySks6HUPlXRPeAL9Hk7Uc/k IUOM5zlXkkbsLsu2CUCw4KLJ0UnF9895+aTXyQB5TkIMJtSC6TBMYUVGg YHB6SZg5Ba0tMcVh145EOBZPZHIUr0NVzMCetMKUmCbs0aPGngaRqBno+ w==; X-CSE-ConnectionGUID: kGU9Nix/T9yuRht3IMN43w== X-CSE-MsgGUID: 622sYKi3TyG5EvTVJvkRPA== X-IronPort-AV: E=McAfee;i="6800,10657,11483"; a="53909125" X-IronPort-AV: E=Sophos;i="6.16,286,1744095600"; d="scan'208";a="53909125" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 21:23:26 -0700 X-CSE-ConnectionGUID: +Lpl7NRDQSitRqHUpZZD0Q== X-CSE-MsgGUID: xCWoZqZbQGCGzDo8ZVm1RA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,286,1744095600"; d="scan'208";a="153968702" Received: from jf5300-b11a338t.jf.intel.com ([10.242.51.115]) by orviesa006.jf.intel.com with ESMTP; 03 Jul 2025 21:23:26 -0700 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosry.ahmed@linux.dev, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, 21cnbao@gmail.com, ying.huang@linux.alibaba.com, akpm@linux-foundation.org, senozhatsky@chromium.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, vinicius.gomes@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v10 14/25] crypto: iaa - Enable async mode and make it the default. Date: Thu, 3 Jul 2025 21:23:12 -0700 Message-Id: <20250704042323.10318-15-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20250704042323.10318-1-kanchana.p.sridhar@intel.com> References: <20250704042323.10318-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch enables the 'async' sync_mode in the driver. Further, it sets the default sync_mode to 'async', which makes it easier for IAA hardware acceleration in the iaa_crypto driver to be loaded by default in the most efficient/recommended 'async' mode for parallel compressions/decompressions, namely, asynchronous submission of descriptors, followed by polling for job completions. Earlier, the "sync" mode used to be the default. The iaa_crypto driver documentation has been updated with these changes. This way, anyone who wants to use IAA for zswap/zram can do so after building the kernel, and without having to go through these steps to use async mode: 1) disable all the IAA device/wq bindings that happen at boot time 2) rmmod iaa_crypto 3) modprobe iaa_crypto 4) echo async > /sys/bus/dsa/drivers/crypto/sync_mode 5) re-run initialization of the IAA devices and wqs Signed-off-by: Kanchana P Sridhar --- Documentation/driver-api/crypto/iaa/iaa-crypto.rst | 11 ++--------- drivers/crypto/intel/iaa/iaa_crypto_main.c | 4 ++-- 2 files changed, 4 insertions(+), 11 deletions(-) diff --git a/Documentation/driver-api/crypto/iaa/iaa-crypto.rst b/Documenta= tion/driver-api/crypto/iaa/iaa-crypto.rst index 949bfa1ef6245..8e0e98d509720 100644 --- a/Documentation/driver-api/crypto/iaa/iaa-crypto.rst +++ b/Documentation/driver-api/crypto/iaa/iaa-crypto.rst @@ -272,7 +272,7 @@ The available attributes are: echo async_irq > /sys/bus/dsa/drivers/crypto/sync_mode =20 Async mode without interrupts (caller must poll) can be enabled by - writing 'async' to it (please see Caveat):: + writing 'async' to it:: =20 echo async > /sys/bus/dsa/drivers/crypto/sync_mode =20 @@ -281,14 +281,7 @@ The available attributes are: =20 echo sync > /sys/bus/dsa/drivers/crypto/sync_mode =20 - The default mode is 'sync'. - - Caveat: since the only mechanism that iaa_crypto currently implements - for async polling without interrupts is via the 'sync' mode as - described earlier, writing 'async' to - '/sys/bus/dsa/drivers/crypto/sync_mode' will internally enable the - 'sync' mode. This is to ensure correct iaa_crypto behavior until true - async polling without interrupts is enabled in iaa_crypto. + The default mode is 'async'. =20 - g_comp_wqs_per_iaa =20 diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index 0ed3d6e8ad0ec..cf12257f7400d 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -152,7 +152,7 @@ static bool iaa_verify_compress =3D true; */ =20 /* Use async mode */ -static bool async_mode; +static bool async_mode =3D true; /* Use interrupts */ static bool use_irq; =20 @@ -206,7 +206,7 @@ static int set_iaa_sync_mode(const char *name) async_mode =3D false; use_irq =3D false; } else if (sysfs_streq(name, "async")) { - async_mode =3D false; + async_mode =3D true; use_irq =3D false; } else if (sysfs_streq(name, "async_irq")) { async_mode =3D true; --=20 2.27.0