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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae3f66d1ae3sm119401766b.7.2025.07.04.00.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 00:17:21 -0700 (PDT) From: Luca Weiss Date: Fri, 04 Jul 2025 09:17:02 +0200 Subject: [PATCH v2 10/11] dt-bindings: clock: qcom: document the Milos Video Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-sm7635-clocks-v2-10-9e47a7c0d47f@fairphone.com> References: <20250704-sm7635-clocks-v2-0-9e47a7c0d47f@fairphone.com> In-Reply-To: <20250704-sm7635-clocks-v2-0-9e47a7c0d47f@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1751613431; l=3534; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=+AgG3zOOY6NcwwiQON9pv2xqdDKfNXoaCvH5y/j8frQ=; b=j6yEHZm8qoUd1p2T4cYFS2hQiXkDm9rfgmvDYx5bvu6n0tdFs9nB51qM4Y2ihCYrcJ95g8k6d cdY8LlZ2ViiALnQXKai0hlFDtUXjNItbH4tlqOK4KYl8hjWSftyCxjJ X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add bindings documentation for the Milos (e.g. SM7635) Video Clock Controller. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,milos-videocc.yaml | 53 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,milos-videocc.h | 36 +++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yam= l b/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..14c31efe1308aadbea61eb7be7e= 56039a923aec5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,milos-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on Milos + +maintainers: + - Luca Weiss + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on Milos. + + See also: include/dt-bindings/clock/qcom,milos-videocc.h + +properties: + compatible: + const: qcom,milos-videocc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: Video AHB clock from GCC + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@aaf0000 { + compatible =3D "qcom,milos-videocc"; + reg =3D <0x0aaf0000 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,milos-videocc.h b/include/dt-bi= ndings/clock/qcom,milos-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..3544db81ffae6fb7c72b123063b= 9af4337742054 --- /dev/null +++ b/include/dt-bindings/clock/qcom,milos-videocc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2025, Luca Weiss + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MILOS_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MILOS_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_PLL0 0 +#define VIDEO_CC_AHB_CLK 1 +#define VIDEO_CC_AHB_CLK_SRC 2 +#define VIDEO_CC_MVS0_CLK 3 +#define VIDEO_CC_MVS0_CLK_SRC 4 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 5 +#define VIDEO_CC_MVS0_SHIFT_CLK 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS0C_SHIFT_CLK 9 +#define VIDEO_CC_SLEEP_CLK 10 +#define VIDEO_CC_SLEEP_CLK_SRC 11 +#define VIDEO_CC_XO_CLK 12 +#define VIDEO_CC_XO_CLK_SRC 13 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_MVS0C_BCR 3 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 + +#endif --=20 2.50.0