From nobody Tue Oct 7 22:39:43 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56EDE1957FC for ; Fri, 4 Jul 2025 14:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751639016; cv=none; b=ENd2XBPazUiRzCwVHwWBKKIRKeGzMrCyBn/CkgWNQrSVaGMnZ+13CJobH1Dwi18/2O3mzBvxqhLSq5DRZ8u0+67IZbz45BRnqKaM6KTobeqXicjRoH9sJKCgp6apUzg6ZcvtrJ0V8aonuEGIRmIE/Es1V7/C0Ejk2ikjq9cDSmo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751639016; c=relaxed/simple; bh=ldghlCA/gMRJSmgWfHfOpqHHla57kEBIADI+qzIkLJM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MnB3Q9bHuX8pHqVC4pG2Tr0hgjZly3mB1xrNxfLx4DgMlWh25tUdDU7Qd0lZXQ8g+HaaM0x49qb5qNTJwpVcJ8Uh9Lgb4Dvt+NLjUM71J6cC/9grTqQAVqpFxscjmeWFroJ0mG8bEfkog0IBJkQRe5TViAjFYRGB+AmCtpjHNEM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=j0OSfDCF; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="j0OSfDCF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1751639012; bh=ldghlCA/gMRJSmgWfHfOpqHHla57kEBIADI+qzIkLJM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=j0OSfDCFH8OfiJOhvUn9D6WUpQJvvU4qXHErh4TQF0dt4QlncVUY7xgM7zYF32CGe mfHoZ8eiivxE2b/t3EDAaHeJUjaLpCVjCSUCExJypkk19O5QSBfY9d91nqPjsQ8gvE jyih9f9bX3SHlnoIZkl+KLy0qTotzF4ZOI9uswffr2YhjkWxIZEpNRIpjfarVGz/lW x8EkNZeZR4fGWPJ2kAM/RuxGhh1pHKxsIJwRYKRg6ZJ/76kYx8m8chW0ChJc5UzTJa ZJjolJHfLo9uVPSYX5kfwLG51cJ85x6EioqsO6eLm63jQfz8818VaJEUGwQdXtaVI1 B6uTSDgXViuUQ== Received: from localhost (unknown [212.93.144.165]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 2C9D917E090E; Fri, 4 Jul 2025 16:23:32 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 04 Jul 2025 17:23:22 +0300 Subject: [PATCH 1/5] drm/rockchip: dw_hdmi_qp: Provide CEC IRQ in dw_hdmi_qp_plat_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-rk3588-hdmi-cec-v1-1-2bd8de8700cd@collabora.com> References: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> In-Reply-To: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 In preparation to support the CEC interface of the DesignWare HDMI QP IP block, extend the platform data to provide the required IRQ number. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 4 ++++ include/drm/bridge/dw_hdmi_qp.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 7d531b6f4c098c6c548788dad487ce4613a2f32b..126e556025961e8645f3567b4d7= a1c73cc2f2e7f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -539,6 +539,10 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, if (plat_data.main_irq < 0) return plat_data.main_irq; =20 + plat_data.cec_irq =3D platform_get_irq_byname(pdev, "cec"); + if (plat_data.cec_irq < 0) + return plat_data.cec_irq; + irq =3D platform_get_irq_byname(pdev, "hpd"); if (irq < 0) return irq; diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index e9be6d507ad9cdc55f5c7d6d3ef37eba41f1ce74..b4a9b739734ec7b67013b683fe6= 017551aa19172 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -23,6 +23,7 @@ struct dw_hdmi_qp_plat_data { const struct dw_hdmi_qp_phy_ops *phy_ops; void *phy_data; int main_irq; + int cec_irq; }; =20 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, --=20 2.50.0 From nobody Tue Oct 7 22:39:43 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1041719AD5C for ; Fri, 4 Jul 2025 14:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751639017; cv=none; b=YN/Eqwa2wnAjGii/F1IIOedSxyxrVFD8O0qwzvGURnxswNsQJTm5OwgYPILxX9m3ut+MBAK04lSxznoIa6VcKfP4FlOyk66dUCXdzzoEcADsbuIIdrtE2lapVmW7ACd7d8pvZ/3xCjkwKaSY3x6MC3pljjuyU/cJgZPKggt3CRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751639017; c=relaxed/simple; bh=pjIe5xbHyZmxavJ2HWMZlWZPWolcvoBu+7pdo4pWb8k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 4 Jul 2025 16:23:32 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 04 Jul 2025 17:23:23 +0300 Subject: [PATCH 2/5] drm/bridge: dw-hdmi-qp: Add CEC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-rk3588-hdmi-cec-v1-2-2bd8de8700cd@collabora.com> References: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> In-Reply-To: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Algea Cao , Derek Foreman X-Mailer: b4 0.14.2 Add support for the CEC interface of the Synopsys DesignWare HDMI QP TX controller. This is based on the downstream implementation, but rewritten on top of the CEC helpers added recently to the DRM HDMI connector framework. Co-developed-by: Algea Cao Signed-off-by: Algea Cao Co-developed-by: Derek Foreman Signed-off-by: Derek Foreman Signed-off-by: Cristian Ciocaltea Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/bridge/synopsys/Kconfig | 8 + drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 220 +++++++++++++++++++++++= ++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 14 ++ 3 files changed, 242 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/brid= ge/synopsys/Kconfig index f3ab2f985f8ca9dc1eeac3bda6b4a31d355cd51c..99878f051067e65fa3b97d8132b= e8cfa15980966 100644 --- a/drivers/gpu/drm/bridge/synopsys/Kconfig +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig @@ -54,6 +54,14 @@ config DRM_DW_HDMI_QP select DRM_KMS_HELPER select REGMAP_MMIO =20 +config DRM_DW_HDMI_QP_CEC + bool "Synopsis Designware QP CEC interface" + depends on DRM_DW_HDMI_QP + select DRM_DISPLAY_HDMI_CEC_HELPER + help + Support the CEC interface which is part of the Synopsys + Designware HDMI QP block. + config DRM_DW_MIPI_DSI tristate select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index 7ade80f02a94c91905c13b4a945c65da5681b183..cfe8171b2183874517f583f284f= 7728fe1613c91 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -18,6 +18,7 @@ =20 #include #include +#include #include #include #include @@ -26,6 +27,8 @@ #include #include =20 +#include + #include =20 #include "dw-hdmi-qp.h" @@ -131,12 +134,28 @@ struct dw_hdmi_qp_i2c { bool is_segment; }; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC +struct dw_hdmi_qp_cec { + struct drm_connector *connector; + int irq; + u32 addresses; + struct cec_msg rx_msg; + u8 tx_status; + bool tx_done; + bool rx_done; +}; +#endif + struct dw_hdmi_qp { struct drm_bridge bridge; =20 struct device *dev; struct dw_hdmi_qp_i2c *i2c; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC + struct dw_hdmi_qp_cec *cec; +#endif + struct { const struct dw_hdmi_qp_phy_ops *ops; void *data; @@ -965,6 +984,191 @@ static int dw_hdmi_qp_bridge_write_infoframe(struct d= rm_bridge *bridge, } } =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC +static irqreturn_t dw_hdmi_qp_cec_hardirq(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi =3D dev_id; + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + irqreturn_t ret =3D IRQ_HANDLED; + u32 stat; + + stat =3D dw_hdmi_qp_read(hdmi, CEC_INT_STATUS); + if (stat =3D=3D 0) + return IRQ_NONE; + + dw_hdmi_qp_write(hdmi, stat, CEC_INT_CLEAR); + + if (stat & CEC_STAT_LINE_ERR) { + cec->tx_status =3D CEC_TX_STATUS_ERROR; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_DONE) { + cec->tx_status =3D CEC_TX_STATUS_OK; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_NACK) { + cec->tx_status =3D CEC_TX_STATUS_NACK; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } + + if (stat & CEC_STAT_EOM) { + unsigned int len, i, val; + + val =3D dw_hdmi_qp_read(hdmi, CEC_RX_COUNT_STATUS); + len =3D (val & 0xf) + 1; + + if (len > sizeof(cec->rx_msg.msg)) + len =3D sizeof(cec->rx_msg.msg); + + for (i =3D 0; i < 4; i++) { + val =3D dw_hdmi_qp_read(hdmi, CEC_RX_DATA3_0 + i * 4); + cec->rx_msg.msg[i * 4] =3D val & 0xff; + cec->rx_msg.msg[i * 4 + 1] =3D (val >> 8) & 0xff; + cec->rx_msg.msg[i * 4 + 2] =3D (val >> 16) & 0xff; + cec->rx_msg.msg[i * 4 + 3] =3D (val >> 24) & 0xff; + } + + dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); + + cec->rx_msg.len =3D len; + cec->rx_done =3D true; + + ret =3D IRQ_WAKE_THREAD; + } + + return ret; +} + +static irqreturn_t dw_hdmi_qp_cec_thread(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi =3D dev_id; + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + + if (cec->tx_done) { + cec->tx_done =3D false; + drm_connector_hdmi_cec_transmit_attempt_done(cec->connector, + cec->tx_status); + } + + if (cec->rx_done) { + cec->rx_done =3D false; + drm_connector_hdmi_cec_received_msg(cec->connector, &cec->rx_msg); + } + + return IRQ_HANDLED; +} + +static int dw_hdmi_qp_cec_init(struct drm_connector *connector, + struct drm_bridge *bridge) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + int ret; + + if (cec->irq < 0) { + dev_err(hdmi->dev, "Invalid cec irq: %d\n", cec->irq); + return -EINVAL; + } + + cec->connector =3D connector; + + dw_hdmi_qp_write(hdmi, 0, CEC_TX_COUNT); + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); + + ret =3D devm_request_threaded_irq(hdmi->dev, cec->irq, + dw_hdmi_qp_cec_hardirq, + dw_hdmi_qp_cec_thread, IRQF_SHARED, + dev_name(hdmi->dev), hdmi); + if (ret < 0) { + dev_err(hdmi->dev, "Request cec irq thread failed: %d\n", ret); + return ret; + } + + return 0; +} + +static int dw_hdmi_qp_cec_log_addr(struct drm_bridge *bridge, u8 logical_a= ddr) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + + if (logical_addr =3D=3D CEC_LOG_ADDR_INVALID) + cec->addresses =3D 0; + else + cec->addresses |=3D BIT(logical_addr) | CEC_ADDR_BROADCAST; + + dw_hdmi_qp_write(hdmi, cec->addresses, CEC_ADDR); + + return 0; +} + +static int dw_hdmi_qp_cec_enable(struct drm_bridge *bridge, bool enable) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + unsigned int irqs; + u32 swdisable; + + if (!enable) { + dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + + swdisable =3D dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); + swdisable =3D swdisable | CEC_SWDISABLE; + dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); + } else { + swdisable =3D dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); + swdisable =3D swdisable & ~CEC_SWDISABLE; + dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); + + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); + + dw_hdmi_qp_cec_log_addr(bridge, CEC_LOG_ADDR_INVALID); + + irqs =3D CEC_STAT_LINE_ERR | CEC_STAT_NACK | CEC_STAT_EOM | + CEC_STAT_DONE; + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, irqs, CEC_INT_MASK_N); + } + + return 0; +} + +static int dw_hdmi_qp_cec_transmit(struct drm_bridge *bridge, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + unsigned int i; + u32 val; + + for (i =3D 0; i < msg->len; i++) { + if (!(i % 4)) + val =3D msg->msg[i]; + if ((i % 4) =3D=3D 1) + val |=3D msg->msg[i] << 8; + if ((i % 4) =3D=3D 2) + val |=3D msg->msg[i] << 16; + if ((i % 4) =3D=3D 3) + val |=3D msg->msg[i] << 24; + + if (i =3D=3D (msg->len - 1) || (i % 4) =3D=3D 3) + dw_hdmi_qp_write(hdmi, val, CEC_TX_DATA3_0 + (i / 4) * 4); + } + + dw_hdmi_qp_write(hdmi, msg->len - 1, CEC_TX_COUNT); + dw_hdmi_qp_write(hdmi, CEC_CTRL_START, CEC_TX_CONTROL); + + return 0; +} +#else +#define dw_hdmi_qp_cec_init NULL +#define dw_hdmi_qp_cec_enable NULL +#define dw_hdmi_qp_cec_log_addr NULL +#define dw_hdmi_qp_cec_transmit NULL +#endif /* CONFIG_DRM_DW_HDMI_QP_CEC */ + static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, @@ -979,6 +1183,10 @@ static const struct drm_bridge_funcs dw_hdmi_qp_bridg= e_funcs =3D { .hdmi_audio_startup =3D dw_hdmi_qp_audio_enable, .hdmi_audio_shutdown =3D dw_hdmi_qp_audio_disable, .hdmi_audio_prepare =3D dw_hdmi_qp_audio_prepare, + .hdmi_cec_init =3D dw_hdmi_qp_cec_init, + .hdmi_cec_enable =3D dw_hdmi_qp_cec_enable, + .hdmi_cec_log_addr =3D dw_hdmi_qp_cec_log_addr, + .hdmi_cec_transmit =3D dw_hdmi_qp_cec_transmit, }; =20 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) @@ -1093,6 +1301,18 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, hdmi->bridge.hdmi_audio_dev =3D dev; hdmi->bridge.hdmi_audio_dai_port =3D 1; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC + hdmi->bridge.ops |=3D DRM_BRIDGE_OP_HDMI_CEC_ADAPTER; + hdmi->bridge.hdmi_cec_dev =3D dev; + hdmi->bridge.hdmi_cec_adapter_name =3D dev_name(dev); + + hdmi->cec =3D devm_kzalloc(hdmi->dev, sizeof(*hdmi->cec), GFP_KERNEL); + if (!hdmi->cec) + return ERR_PTR(-ENOMEM); + + hdmi->cec->irq =3D plat_data->cec_irq; +#endif + ret =3D devm_drm_bridge_add(dev, &hdmi->bridge); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.h index 72987e6c468928f2b998099697a6f32726411557..91a15f82e32acc32eef58f11ec5= ca958337ebb9a 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h @@ -488,9 +488,23 @@ #define AUDPKT_VBIT_OVR0 0xf24 /* CEC Registers */ #define CEC_TX_CONTROL 0x1000 +#define CEC_CTRL_CLEAR BIT(0) +#define CEC_CTRL_START BIT(0) #define CEC_STATUS 0x1004 +#define CEC_STAT_DONE BIT(0) +#define CEC_STAT_NACK BIT(1) +#define CEC_STAT_ARBLOST BIT(2) +#define CEC_STAT_LINE_ERR BIT(3) +#define CEC_STAT_RETRANS_FAIL BIT(4) +#define CEC_STAT_DISCARD BIT(5) +#define CEC_STAT_TX_BUSY BIT(8) +#define CEC_STAT_RX_BUSY BIT(9) +#define CEC_STAT_DRIVE_ERR BIT(10) +#define CEC_STAT_EOM BIT(11) +#define CEC_STAT_NOTIFY_ERR BIT(12) #define CEC_CONFIG 0x1008 #define CEC_ADDR 0x100c +#define CEC_ADDR_BROADCAST BIT(15) #define CEC_TX_COUNT 0x1020 #define CEC_TX_DATA3_0 0x1024 #define CEC_TX_DATA7_4 0x1028 --=20 2.50.0 From nobody Tue Oct 7 22:39:43 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B69A81C700D for ; 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Fri, 4 Jul 2025 16:23:33 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 04 Jul 2025 17:23:24 +0300 Subject: [PATCH 3/5] drm/rockchip: dw_hdmi_qp: Provide ref clock rate in dw_hdmi_qp_plat_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-rk3588-hdmi-cec-v1-3-2bd8de8700cd@collabora.com> References: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> In-Reply-To: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 In order to support correct initialization of the timer base in the HDMI QP IP block, extend the platform data to provide the necessary reference clock rate. While at it, ensure plat_data is zero-initialized in dw_hdmi_qp_rockchip_bind(). Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 13 ++++++++++++- include/drm/bridge/dw_hdmi_qp.h | 1 + 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 126e556025961e8645f3567b4d7a1c73cc2f2e7f..8c1185490009c5f1bc658998a86= 8f8b18dc479a3 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -431,8 +431,8 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev,= struct device *master, void *data) { struct platform_device *pdev =3D to_platform_device(dev); + struct dw_hdmi_qp_plat_data plat_data =3D {}; const struct rockchip_hdmi_qp_cfg *cfg; - struct dw_hdmi_qp_plat_data plat_data; struct drm_device *drm =3D data; struct drm_connector *connector; struct drm_encoder *encoder; @@ -515,6 +515,17 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, return ret; } =20 + for (i =3D 0; i < ret; i++) { + if (!strcmp(clks[i].id, "ref")) { + plat_data.ref_clk_rate =3D clk_get_rate(clks[i].clk); + break; + } + } + if (!plat_data.ref_clk_rate) { + dev_err(hdmi->dev, "Missing ref clock\n"); + return -EINVAL; + } + hdmi->enable_gpio =3D devm_gpiod_get_optional(hdmi->dev, "enable", GPIOD_OUT_HIGH); if (IS_ERR(hdmi->enable_gpio)) { diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index b4a9b739734ec7b67013b683fe6017551aa19172..76ecf31301997718604a05f70ce= 9eab8695e26b5 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -24,6 +24,7 @@ struct dw_hdmi_qp_plat_data { void *phy_data; int main_irq; int cec_irq; + unsigned long ref_clk_rate; }; =20 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, --=20 2.50.0 From nobody Tue Oct 7 22:39:43 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B694F1C6FE5 for ; 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Fri, 4 Jul 2025 16:23:34 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 04 Jul 2025 17:23:25 +0300 Subject: [PATCH 4/5] drm/bridge: dw-hdmi-qp: Fixup timer base setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-rk3588-hdmi-cec-v1-4-2bd8de8700cd@collabora.com> References: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> In-Reply-To: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed value as initially found in vendor driver code supporting the RK3588 SoC. As a matter of fact the value matches the rate of the HDMI TX reference clock, which is roughly 428.57 MHz. However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and the incorrect register configuration breaks CEC functionality. Set the timer base according to the actual reference clock rate. While at it, also drop the unnecessary empty lines in dw_hdmi_qp_init_hw(). Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index cfe8171b2183874517f583f284f7728fe1613c91..5d252800168aa4f3c10f4586317= 95de8912e29d4 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -161,6 +161,7 @@ struct dw_hdmi_qp { void *data; } phy; =20 + unsigned long ref_clk_rate; struct regmap *regm; =20 unsigned long tmds_char_rate; @@ -1222,13 +1223,11 @@ static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *h= dmi) { dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); - dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0); + dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); =20 /* Software reset */ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); - dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); - dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); =20 /* Clear DONE and ERROR interrupts */ @@ -1254,6 +1253,11 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, return ERR_PTR(-ENODEV); } =20 + if (!plat_data->ref_clk_rate) { + dev_err(dev, "Missing ref_clk rate\n"); + return ERR_PTR(-ENODEV); + } + hdmi =3D devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge, &dw_hdmi_qp_bridge_funcs); if (IS_ERR(hdmi)) @@ -1273,6 +1277,7 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_de= vice *pdev, =20 hdmi->phy.ops =3D plat_data->phy_ops; hdmi->phy.data =3D plat_data->phy_data; + hdmi->ref_clk_rate =3D plat_data->ref_clk_rate; =20 dw_hdmi_qp_init_hw(hdmi); =20 --=20 2.50.0 From nobody Tue Oct 7 22:39:43 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D0441D86C6 for ; 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Fri, 4 Jul 2025 16:23:35 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 04 Jul 2025 17:23:26 +0300 Subject: [PATCH 5/5] arm64: defconfig: Enable DW HDMI QP CEC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-rk3588-hdmi-cec-v1-5-2bd8de8700cd@collabora.com> References: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> In-Reply-To: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Enable support for the CEC interface of the Synopsys DesignWare HDMI QP IP block. This is used by all boards based on RK3588 & RK3576 SoCs. Signed-off-by: Cristian Ciocaltea --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 739b19302865fe8edc54911213321d6f1278aae4..0363ba916e0ed7e7d9dc1169f44= 7f3726580de18 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -958,6 +958,7 @@ CONFIG_DRM_CDNS_MHDP8546=3Dm CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=3Dm CONFIG_DRM_DW_HDMI_AHB_AUDIO=3Dm CONFIG_DRM_DW_HDMI_CEC=3Dm +CONFIG_DRM_DW_HDMI_QP_CEC=3Dy CONFIG_DRM_IMX_DCSS=3Dm CONFIG_DRM_V3D=3Dm CONFIG_DRM_VC4=3Dm --=20 2.50.0