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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sc8180x.c | 961 ++++++++++++++++++--------------= ---- drivers/interconnect/qcom/sc8180x.h | 179 ------- 2 files changed, 483 insertions(+), 657 deletions(-) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qco= m/sc8180x.c index 0640ee55220d54fc977dc98f65644ecf7f50508f..e68bc35b691276375349585ac03= b279e30568c68 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -14,1333 +14,1327 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc8180x.h" + +static struct qcom_icc_node mas_qhm_a1noc_cfg; +static struct qcom_icc_node mas_xm_ufs_card; +static struct qcom_icc_node mas_xm_ufs_g4; +static struct qcom_icc_node mas_xm_ufs_mem; +static struct qcom_icc_node mas_xm_usb3_0; +static struct qcom_icc_node mas_xm_usb3_1; +static struct qcom_icc_node mas_xm_usb3_2; +static struct qcom_icc_node mas_qhm_a2noc_cfg; +static struct qcom_icc_node mas_qhm_qdss_bam; +static struct qcom_icc_node mas_qhm_qspi; +static struct qcom_icc_node mas_qhm_qspi1; +static struct qcom_icc_node mas_qhm_qup0; +static struct qcom_icc_node mas_qhm_qup1; +static struct qcom_icc_node mas_qhm_qup2; +static struct qcom_icc_node mas_qhm_sensorss_ahb; +static struct qcom_icc_node mas_qxm_crypto; +static struct qcom_icc_node mas_qxm_ipa; +static struct qcom_icc_node mas_xm_emac; +static struct qcom_icc_node mas_xm_pcie3_0; +static struct qcom_icc_node mas_xm_pcie3_1; +static struct qcom_icc_node mas_xm_pcie3_2; +static struct qcom_icc_node mas_xm_pcie3_3; +static struct qcom_icc_node mas_xm_qdss_etr; +static struct qcom_icc_node mas_xm_sdc2; +static struct qcom_icc_node mas_xm_sdc4; +static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp; +static struct qcom_icc_node mas_qnm_npu; +static struct qcom_icc_node mas_qnm_snoc; +static struct qcom_icc_node mas_qhm_cnoc_dc_noc; +static struct qcom_icc_node mas_acm_apps; +static struct qcom_icc_node mas_acm_gpu_tcu; +static struct qcom_icc_node mas_acm_sys_tcu; +static struct qcom_icc_node mas_qhm_gemnoc_cfg; +static struct qcom_icc_node mas_qnm_cmpnoc; +static struct qcom_icc_node mas_qnm_gpu; +static struct qcom_icc_node mas_qnm_mnoc_hf; +static struct qcom_icc_node mas_qnm_mnoc_sf; +static struct qcom_icc_node mas_qnm_pcie; +static struct qcom_icc_node mas_qnm_snoc_gc; +static struct qcom_icc_node mas_qnm_snoc_sf; +static struct qcom_icc_node mas_qxm_ecc; +static struct qcom_icc_node mas_llcc_mc; +static struct qcom_icc_node mas_qhm_mnoc_cfg; +static struct qcom_icc_node mas_qxm_camnoc_hf0; +static struct qcom_icc_node mas_qxm_camnoc_hf1; +static struct qcom_icc_node mas_qxm_camnoc_sf; +static struct qcom_icc_node mas_qxm_mdp0; +static struct qcom_icc_node mas_qxm_mdp1; +static struct qcom_icc_node mas_qxm_rot; +static struct qcom_icc_node mas_qxm_venus0; +static struct qcom_icc_node mas_qxm_venus1; +static struct qcom_icc_node mas_qxm_venus_arm9; +static struct qcom_icc_node mas_qhm_snoc_cfg; +static struct qcom_icc_node mas_qnm_aggre1_noc; +static struct qcom_icc_node mas_qnm_aggre2_noc; +static struct qcom_icc_node mas_qnm_gemnoc; +static struct qcom_icc_node mas_qxm_pimem; +static struct qcom_icc_node mas_xm_gic; +static struct qcom_icc_node mas_qup_core_0; +static struct qcom_icc_node mas_qup_core_1; +static struct qcom_icc_node mas_qup_core_2; +static struct qcom_icc_node slv_qns_a1noc_snoc; +static struct qcom_icc_node slv_srvc_aggre1_noc; +static struct qcom_icc_node slv_qns_a2noc_snoc; +static struct qcom_icc_node slv_qns_pcie_mem_noc; +static struct qcom_icc_node slv_srvc_aggre2_noc; +static struct qcom_icc_node slv_qns_camnoc_uncomp; +static struct qcom_icc_node slv_qns_cdsp_mem_noc; +static struct qcom_icc_node slv_qhs_a1_noc_cfg; +static struct qcom_icc_node slv_qhs_a2_noc_cfg; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west; +static struct qcom_icc_node slv_qhs_ahb2phy_south; +static struct qcom_icc_node slv_qhs_aop; +static struct qcom_icc_node slv_qhs_aoss; +static struct qcom_icc_node slv_qhs_camera_cfg; +static struct qcom_icc_node slv_qhs_clk_ctl; +static struct qcom_icc_node slv_qhs_compute_dsp; +static struct qcom_icc_node slv_qhs_cpr_cx; +static struct qcom_icc_node slv_qhs_cpr_mmcx; +static struct qcom_icc_node slv_qhs_cpr_mx; +static struct qcom_icc_node slv_qhs_crypto0_cfg; +static struct qcom_icc_node slv_qhs_ddrss_cfg; +static struct qcom_icc_node slv_qhs_display_cfg; +static struct qcom_icc_node slv_qhs_emac_cfg; +static struct qcom_icc_node slv_qhs_glm; +static struct qcom_icc_node slv_qhs_gpuss_cfg; +static struct qcom_icc_node slv_qhs_imem_cfg; +static struct qcom_icc_node slv_qhs_ipa; +static struct qcom_icc_node slv_qhs_mnoc_cfg; +static struct qcom_icc_node slv_qhs_npu_cfg; +static struct qcom_icc_node slv_qhs_pcie0_cfg; +static struct qcom_icc_node slv_qhs_pcie1_cfg; +static struct qcom_icc_node slv_qhs_pcie2_cfg; +static struct qcom_icc_node slv_qhs_pcie3_cfg; +static struct qcom_icc_node slv_qhs_pdm; +static struct qcom_icc_node slv_qhs_pimem_cfg; +static struct qcom_icc_node slv_qhs_prng; +static struct qcom_icc_node slv_qhs_qdss_cfg; +static struct qcom_icc_node slv_qhs_qspi_0; +static struct qcom_icc_node slv_qhs_qspi_1; +static struct qcom_icc_node slv_qhs_qupv3_east0; +static struct qcom_icc_node slv_qhs_qupv3_east1; +static struct qcom_icc_node slv_qhs_qupv3_west; +static struct qcom_icc_node slv_qhs_sdc2; +static struct qcom_icc_node slv_qhs_sdc4; +static struct qcom_icc_node slv_qhs_security; +static struct qcom_icc_node slv_qhs_snoc_cfg; +static struct qcom_icc_node slv_qhs_spss_cfg; +static struct qcom_icc_node slv_qhs_tcsr; +static struct qcom_icc_node slv_qhs_tlmm_east; +static struct qcom_icc_node slv_qhs_tlmm_south; +static struct qcom_icc_node slv_qhs_tlmm_west; +static struct qcom_icc_node slv_qhs_tsif; +static struct qcom_icc_node slv_qhs_ufs_card_cfg; +static struct qcom_icc_node slv_qhs_ufs_mem0_cfg; +static struct qcom_icc_node slv_qhs_ufs_mem1_cfg; +static struct qcom_icc_node slv_qhs_usb3_0; +static struct qcom_icc_node slv_qhs_usb3_1; +static struct qcom_icc_node slv_qhs_usb3_2; +static struct qcom_icc_node slv_qhs_venus_cfg; +static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg; +static struct qcom_icc_node slv_srvc_cnoc; +static struct qcom_icc_node slv_qhs_gemnoc; +static struct qcom_icc_node slv_qhs_llcc; +static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node slv_qns_ecc; +static struct qcom_icc_node slv_qns_gem_noc_snoc; +static struct qcom_icc_node slv_qns_llcc; +static struct qcom_icc_node slv_srvc_gemnoc; +static struct qcom_icc_node slv_srvc_gemnoc1; +static struct qcom_icc_node slv_ebi; +static struct qcom_icc_node slv_qns2_mem_noc; +static struct qcom_icc_node slv_qns_mem_noc_hf; +static struct qcom_icc_node slv_srvc_mnoc; +static struct qcom_icc_node slv_qhs_apss; +static struct qcom_icc_node slv_qns_cnoc; +static struct qcom_icc_node slv_qns_gemnoc_gc; +static struct qcom_icc_node slv_qns_gemnoc_sf; +static struct qcom_icc_node slv_qxs_imem; +static struct qcom_icc_node slv_qxs_pimem; +static struct qcom_icc_node slv_srvc_snoc; +static struct qcom_icc_node slv_xs_pcie_0; +static struct qcom_icc_node slv_xs_pcie_1; +static struct qcom_icc_node slv_xs_pcie_2; +static struct qcom_icc_node slv_xs_pcie_3; +static struct qcom_icc_node slv_xs_qdss_stm; +static struct qcom_icc_node slv_xs_sys_tcu_cfg; +static struct qcom_icc_node slv_qup_core_0; +static struct qcom_icc_node slv_qup_core_1; +static struct qcom_icc_node slv_qup_core_2; =20 static struct qcom_icc_node mas_qhm_a1noc_cfg =3D { .name =3D "mas_qhm_a1noc_cfg", - .id =3D SC8180X_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_SERVICE_A1NOC } + .link_nodes =3D { &slv_srvc_aggre1_noc, NULL } }; =20 static struct qcom_icc_node mas_xm_ufs_card =3D { .name =3D "mas_xm_ufs_card", - .id =3D SC8180X_MASTER_UFS_CARD, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_ufs_g4 =3D { .name =3D "mas_xm_ufs_g4", - .id =3D SC8180X_MASTER_UFS_GEN4, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_ufs_mem =3D { .name =3D "mas_xm_ufs_mem", - .id =3D SC8180X_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_usb3_0 =3D { .name =3D "mas_xm_usb3_0", - .id =3D SC8180X_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_usb3_1 =3D { .name =3D "mas_xm_usb3_1", - .id =3D SC8180X_MASTER_USB3_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_usb3_2 =3D { .name =3D "mas_xm_usb3_2", - .id =3D SC8180X_MASTER_USB3_2, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a1noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qhm_a2noc_cfg =3D { .name =3D "mas_qhm_a2noc_cfg", - .id =3D SC8180X_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_SERVICE_A2NOC } + .link_nodes =3D { &slv_srvc_aggre2_noc, NULL } }; =20 static struct qcom_icc_node mas_qhm_qdss_bam =3D { .name =3D "mas_qhm_qdss_bam", - .id =3D SC8180X_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qhm_qspi =3D { .name =3D "mas_qhm_qspi", - .id =3D SC8180X_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qhm_qspi1 =3D { .name =3D "mas_qhm_qspi1", - .id =3D SC8180X_MASTER_QSPI_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qhm_qup0 =3D { .name =3D "mas_qhm_qup0", - .id =3D SC8180X_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qhm_qup1 =3D { .name =3D "mas_qhm_qup1", - .id =3D SC8180X_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qhm_qup2 =3D { .name =3D "mas_qhm_qup2", - .id =3D SC8180X_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qhm_sensorss_ahb =3D { .name =3D "mas_qhm_sensorss_ahb", - .id =3D SC8180X_MASTER_SENSORS_AHB, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qxm_crypto =3D { .name =3D "mas_qxm_crypto", - .id =3D SC8180X_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qxm_ipa =3D { .name =3D "mas_qxm_ipa", - .id =3D SC8180X_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_emac =3D { .name =3D "mas_xm_emac", - .id =3D SC8180X_MASTER_EMAC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_pcie3_0 =3D { .name =3D "mas_xm_pcie3_0", - .id =3D SC8180X_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes =3D { &slv_qns_pcie_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_xm_pcie3_1 =3D { .name =3D "mas_xm_pcie3_1", - .id =3D SC8180X_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes =3D { &slv_qns_pcie_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_xm_pcie3_2 =3D { .name =3D "mas_xm_pcie3_2", - .id =3D SC8180X_MASTER_PCIE_2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes =3D { &slv_qns_pcie_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_xm_pcie3_3 =3D { .name =3D "mas_xm_pcie3_3", - .id =3D SC8180X_MASTER_PCIE_3, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes =3D { &slv_qns_pcie_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_xm_qdss_etr =3D { .name =3D "mas_xm_qdss_etr", - .id =3D SC8180X_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_sdc2 =3D { .name =3D "mas_xm_sdc2", - .id =3D SC8180X_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_xm_sdc4 =3D { .name =3D "mas_xm_sdc4", - .id =3D SC8180X_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_SLV } + .link_nodes =3D { &slv_qns_a2noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp =3D { .name =3D "mas_qxm_camnoc_hf0_uncomp", - .id =3D SC8180X_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes =3D { &slv_qns_camnoc_uncomp, NULL } }; =20 static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp =3D { .name =3D "mas_qxm_camnoc_hf1_uncomp", - .id =3D SC8180X_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes =3D { &slv_qns_camnoc_uncomp, NULL } }; =20 static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp =3D { .name =3D "mas_qxm_camnoc_sf_uncomp", - .id =3D SC8180X_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes =3D { &slv_qns_camnoc_uncomp, NULL } }; =20 static struct qcom_icc_node mas_qnm_npu =3D { .name =3D "mas_qnm_npu", - .id =3D SC8180X_MASTER_NPU, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_CDSP_MEM_NOC } + .link_nodes =3D { &slv_qns_cdsp_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_qnm_snoc =3D { .name =3D "mas_qnm_snoc", - .id =3D SC8180X_SNOC_CNOC_MAS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 56, - .links =3D { SC8180X_SLAVE_TLMM_SOUTH, - SC8180X_SLAVE_CDSP_CFG, - SC8180X_SLAVE_SPSS_CFG, - SC8180X_SLAVE_CAMERA_CFG, - SC8180X_SLAVE_SDCC_4, - SC8180X_SLAVE_AHB2PHY_CENTER, - SC8180X_SLAVE_SDCC_2, - SC8180X_SLAVE_PCIE_2_CFG, - SC8180X_SLAVE_CNOC_MNOC_CFG, - SC8180X_SLAVE_EMAC_CFG, - SC8180X_SLAVE_QSPI_0, - SC8180X_SLAVE_QSPI_1, - SC8180X_SLAVE_TLMM_EAST, - SC8180X_SLAVE_SNOC_CFG, - SC8180X_SLAVE_AHB2PHY_EAST, - SC8180X_SLAVE_GLM, - SC8180X_SLAVE_PDM, - SC8180X_SLAVE_PCIE_1_CFG, - SC8180X_SLAVE_A2NOC_CFG, - SC8180X_SLAVE_QDSS_CFG, - SC8180X_SLAVE_DISPLAY_CFG, - SC8180X_SLAVE_TCSR, - SC8180X_SLAVE_UFS_MEM_0_CFG, - SC8180X_SLAVE_CNOC_DDRSS, - SC8180X_SLAVE_PCIE_0_CFG, - SC8180X_SLAVE_QUP_1, - SC8180X_SLAVE_QUP_2, - SC8180X_SLAVE_NPU_CFG, - SC8180X_SLAVE_CRYPTO_0_CFG, - SC8180X_SLAVE_GRAPHICS_3D_CFG, - SC8180X_SLAVE_VENUS_CFG, - SC8180X_SLAVE_TSIF, - SC8180X_SLAVE_IPA_CFG, - SC8180X_SLAVE_CLK_CTL, - SC8180X_SLAVE_SECURITY, - SC8180X_SLAVE_AOP, - SC8180X_SLAVE_AHB2PHY_WEST, - SC8180X_SLAVE_AHB2PHY_SOUTH, - SC8180X_SLAVE_SERVICE_CNOC, - SC8180X_SLAVE_UFS_CARD_CFG, - SC8180X_SLAVE_USB3_1, - SC8180X_SLAVE_USB3_2, - SC8180X_SLAVE_PCIE_3_CFG, - SC8180X_SLAVE_RBCPR_CX_CFG, - SC8180X_SLAVE_TLMM_WEST, - SC8180X_SLAVE_A1NOC_CFG, - SC8180X_SLAVE_AOSS, - SC8180X_SLAVE_PRNG, - SC8180X_SLAVE_VSENSE_CTRL_CFG, - SC8180X_SLAVE_QUP_0, - SC8180X_SLAVE_USB3, - SC8180X_SLAVE_RBCPR_MMCX_CFG, - SC8180X_SLAVE_PIMEM_CFG, - SC8180X_SLAVE_UFS_MEM_1_CFG, - SC8180X_SLAVE_RBCPR_MX_CFG, - SC8180X_SLAVE_IMEM_CFG } + .link_nodes =3D { &slv_qhs_tlmm_south, + &slv_qhs_compute_dsp, + &slv_qhs_spss_cfg, + &slv_qhs_camera_cfg, + &slv_qhs_sdc4, + &slv_qhs_ahb2phy_refgen_center, + &slv_qhs_sdc2, + &slv_qhs_pcie2_cfg, + &slv_qhs_mnoc_cfg, + &slv_qhs_emac_cfg, + &slv_qhs_qspi_0, + &slv_qhs_qspi_1, + &slv_qhs_tlmm_east, + &slv_qhs_snoc_cfg, + &slv_qhs_ahb2phy_refgen_east, + &slv_qhs_glm, + &slv_qhs_pdm, + &slv_qhs_pcie1_cfg, + &slv_qhs_a2_noc_cfg, + &slv_qhs_qdss_cfg, + &slv_qhs_display_cfg, + &slv_qhs_tcsr, + &slv_qhs_ufs_mem0_cfg, + &slv_qhs_ddrss_cfg, + &slv_qhs_pcie0_cfg, + &slv_qhs_qupv3_east0, + &slv_qhs_qupv3_east1, + &slv_qhs_npu_cfg, + &slv_qhs_crypto0_cfg, + &slv_qhs_gpuss_cfg, + &slv_qhs_venus_cfg, + &slv_qhs_tsif, + &slv_qhs_ipa, + &slv_qhs_clk_ctl, + &slv_qhs_security, + &slv_qhs_aop, + &slv_qhs_ahb2phy_refgen_west, + &slv_qhs_ahb2phy_south, + &slv_srvc_cnoc, + &slv_qhs_ufs_card_cfg, + &slv_qhs_usb3_1, + &slv_qhs_usb3_2, + &slv_qhs_pcie3_cfg, + &slv_qhs_cpr_cx, + &slv_qhs_tlmm_west, + &slv_qhs_a1_noc_cfg, + &slv_qhs_aoss, + &slv_qhs_prng, + &slv_qhs_vsense_ctrl_cfg, + &slv_qhs_qupv3_west, + &slv_qhs_usb3_0, + &slv_qhs_cpr_mmcx, + &slv_qhs_pimem_cfg, + &slv_qhs_ufs_mem1_cfg, + &slv_qhs_cpr_mx, + &slv_qhs_imem_cfg, NULL } }; =20 static struct qcom_icc_node mas_qhm_cnoc_dc_noc =3D { .name =3D "mas_qhm_cnoc_dc_noc", - .id =3D SC8180X_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC_CFG, - SC8180X_SLAVE_GEM_NOC_CFG } + .link_nodes =3D { &slv_qhs_llcc, + &slv_qhs_gemnoc, NULL } }; =20 static struct qcom_icc_node mas_acm_apps =3D { .name =3D "mas_acm_apps", - .id =3D SC8180X_MASTER_AMPSS_M0, .channels =3D 4, .buswidth =3D 64, - .num_links =3D 3, - .links =3D { SC8180X_SLAVE_ECC, - SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_ecc, + &slv_qns_llcc, + &slv_qns_gem_noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_acm_gpu_tcu =3D { .name =3D "mas_acm_gpu_tcu", - .id =3D SC8180X_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_acm_sys_tcu =3D { .name =3D "mas_acm_sys_tcu", - .id =3D SC8180X_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qhm_gemnoc_cfg =3D { .name =3D "mas_qhm_gemnoc_cfg", - .id =3D SC8180X_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 3, - .links =3D { SC8180X_SLAVE_SERVICE_GEM_NOC_1, - SC8180X_SLAVE_SERVICE_GEM_NOC, - SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG } + .link_nodes =3D { &slv_srvc_gemnoc1, + &slv_srvc_gemnoc, + &slv_qhs_mdsp_ms_mpu_cfg, NULL } }; =20 static struct qcom_icc_node mas_qnm_cmpnoc =3D { .name =3D "mas_qnm_cmpnoc", - .id =3D SC8180X_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 3, - .links =3D { SC8180X_SLAVE_ECC, - SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_ecc, + &slv_qns_llcc, + &slv_qns_gem_noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qnm_gpu =3D { .name =3D "mas_qnm_gpu", - .id =3D SC8180X_MASTER_GRAPHICS_3D, .channels =3D 4, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qnm_mnoc_hf =3D { .name =3D "mas_qnm_mnoc_hf", - .id =3D SC8180X_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_LLCC } + .link_nodes =3D { &slv_qns_llcc, NULL } }; =20 static struct qcom_icc_node mas_qnm_mnoc_sf =3D { .name =3D "mas_qnm_mnoc_sf", - .id =3D SC8180X_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qnm_pcie =3D { .name =3D "mas_qnm_pcie", - .id =3D SC8180X_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes =3D { &slv_qns_llcc, + &slv_qns_gem_noc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qnm_snoc_gc =3D { .name =3D "mas_qnm_snoc_gc", - .id =3D SC8180X_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_LLCC } + .link_nodes =3D { &slv_qns_llcc, NULL } }; =20 static struct qcom_icc_node mas_qnm_snoc_sf =3D { .name =3D "mas_qnm_snoc_sf", - .id =3D SC8180X_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_LLCC } + .link_nodes =3D { &slv_qns_llcc, NULL } }; =20 static struct qcom_icc_node mas_qxm_ecc =3D { .name =3D "mas_qxm_ecc", - .id =3D SC8180X_MASTER_ECC, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_LLCC } + .link_nodes =3D { &slv_qns_llcc, NULL } }; =20 static struct qcom_icc_node mas_llcc_mc =3D { .name =3D "mas_llcc_mc", - .id =3D SC8180X_MASTER_LLCC, .channels =3D 8, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_EBI_CH0 } + .link_nodes =3D { &slv_ebi, NULL } }; =20 static struct qcom_icc_node mas_qhm_mnoc_cfg =3D { .name =3D "mas_qhm_mnoc_cfg", - .id =3D SC8180X_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_SERVICE_MNOC } + .link_nodes =3D { &slv_srvc_mnoc, NULL } }; =20 static struct qcom_icc_node mas_qxm_camnoc_hf0 =3D { .name =3D "mas_qxm_camnoc_hf0", - .id =3D SC8180X_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes =3D { &slv_qns_mem_noc_hf, NULL } }; =20 static struct qcom_icc_node mas_qxm_camnoc_hf1 =3D { .name =3D "mas_qxm_camnoc_hf1", - .id =3D SC8180X_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes =3D { &slv_qns_mem_noc_hf, NULL } }; =20 static struct qcom_icc_node mas_qxm_camnoc_sf =3D { .name =3D "mas_qxm_camnoc_sf", - .id =3D SC8180X_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_qxm_mdp0 =3D { .name =3D "mas_qxm_mdp0", - .id =3D SC8180X_MASTER_MDP_PORT0, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes =3D { &slv_qns_mem_noc_hf, NULL } }; =20 static struct qcom_icc_node mas_qxm_mdp1 =3D { .name =3D "mas_qxm_mdp1", - .id =3D SC8180X_MASTER_MDP_PORT1, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes =3D { &slv_qns_mem_noc_hf, NULL } }; =20 static struct qcom_icc_node mas_qxm_rot =3D { .name =3D "mas_qxm_rot", - .id =3D SC8180X_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_qxm_venus0 =3D { .name =3D "mas_qxm_venus0", - .id =3D SC8180X_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_qxm_venus1 =3D { .name =3D "mas_qxm_venus1", - .id =3D SC8180X_MASTER_VIDEO_P1, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_qxm_venus_arm9 =3D { .name =3D "mas_qxm_venus_arm9", - .id =3D SC8180X_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes =3D { &slv_qns2_mem_noc, NULL } }; =20 static struct qcom_icc_node mas_qhm_snoc_cfg =3D { .name =3D "mas_qhm_snoc_cfg", - .id =3D SC8180X_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_SERVICE_SNOC } + .link_nodes =3D { &slv_srvc_snoc, NULL } }; =20 static struct qcom_icc_node mas_qnm_aggre1_noc =3D { .name =3D "mas_qnm_aggre1_noc", - .id =3D SC8180X_A1NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 6, - .links =3D { SC8180X_SLAVE_SNOC_GEM_NOC_SF, - SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_QDSS_STM } + .link_nodes =3D { &slv_qns_gemnoc_sf, + &slv_qxs_pimem, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_qns_cnoc, + &slv_xs_qdss_stm, NULL } }; =20 static struct qcom_icc_node mas_qnm_aggre2_noc =3D { .name =3D "mas_qnm_aggre2_noc", - .id =3D SC8180X_A2NOC_SNOC_MAS, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 11, - .links =3D { SC8180X_SLAVE_SNOC_GEM_NOC_SF, - SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_PCIE_3, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SLAVE_PCIE_2, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_PCIE_0, - SC8180X_SLAVE_PCIE_1, - SC8180X_SLAVE_TCU, - SC8180X_SLAVE_QDSS_STM } + .link_nodes =3D { &slv_qns_gemnoc_sf, + &slv_qxs_pimem, + &slv_xs_pcie_3, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_xs_pcie_2, + &slv_qns_cnoc, + &slv_xs_pcie_0, + &slv_xs_pcie_1, + &slv_xs_sys_tcu_cfg, + &slv_xs_qdss_stm, NULL } }; =20 static struct qcom_icc_node mas_qnm_gemnoc =3D { .name =3D "mas_qnm_gemnoc", - .id =3D SC8180X_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 6, - .links =3D { SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_TCU, - SC8180X_SLAVE_QDSS_STM } + .link_nodes =3D { &slv_qxs_pimem, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_qns_cnoc, + &slv_xs_sys_tcu_cfg, + &slv_xs_qdss_stm, NULL } }; =20 static struct qcom_icc_node mas_qxm_pimem =3D { .name =3D "mas_qxm_pimem", - .id =3D SC8180X_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { SC8180X_SLAVE_SNOC_GEM_NOC_GC, - SC8180X_SLAVE_OCIMEM } + .link_nodes =3D { &slv_qns_gemnoc_gc, + &slv_qxs_imem, NULL } }; =20 static struct qcom_icc_node mas_xm_gic =3D { .name =3D "mas_xm_gic", - .id =3D SC8180X_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { SC8180X_SLAVE_SNOC_GEM_NOC_GC, - SC8180X_SLAVE_OCIMEM } + .link_nodes =3D { &slv_qns_gemnoc_gc, + &slv_qxs_imem, NULL } }; =20 static struct qcom_icc_node mas_qup_core_0 =3D { .name =3D "mas_qup_core_0", - .id =3D SC8180X_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_QUP_CORE_0 } + .link_nodes =3D { &slv_qup_core_0, NULL } }; =20 static struct qcom_icc_node mas_qup_core_1 =3D { .name =3D "mas_qup_core_1", - .id =3D SC8180X_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_QUP_CORE_1 } + .link_nodes =3D { &slv_qup_core_1, NULL } }; =20 static struct qcom_icc_node mas_qup_core_2 =3D { .name =3D "mas_qup_core_2", - .id =3D SC8180X_MASTER_QUP_CORE_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_SLAVE_QUP_CORE_2 } + .link_nodes =3D { &slv_qup_core_2, NULL } }; =20 static struct qcom_icc_node slv_qns_a1noc_snoc =3D { .name =3D "slv_qns_a1noc_snoc", - .id =3D SC8180X_A1NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_A1NOC_SNOC_MAS } + .link_nodes =3D { &mas_qnm_aggre1_noc, NULL } }; =20 static struct qcom_icc_node slv_srvc_aggre1_noc =3D { .name =3D "slv_srvc_aggre1_noc", - .id =3D SC8180X_SLAVE_SERVICE_A1NOC, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qns_a2noc_snoc =3D { .name =3D "slv_qns_a2noc_snoc", - .id =3D SC8180X_A2NOC_SNOC_SLV, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC8180X_A2NOC_SNOC_MAS } + .link_nodes =3D { &mas_qnm_aggre2_noc, NULL } }; =20 static struct qcom_icc_node slv_qns_pcie_mem_noc =3D { .name =3D "slv_qns_pcie_mem_noc", - .id =3D SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_GEM_NOC_PCIE_SNOC } + .link_nodes =3D { &mas_qnm_pcie, NULL } }; =20 static struct qcom_icc_node slv_srvc_aggre2_noc =3D { .name =3D "slv_srvc_aggre2_noc", - .id =3D SC8180X_SLAVE_SERVICE_A2NOC, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qns_camnoc_uncomp =3D { .name =3D "slv_qns_camnoc_uncomp", - .id =3D SC8180X_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, - .buswidth =3D 32 + .buswidth =3D 32, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qns_cdsp_mem_noc =3D { .name =3D "slv_qns_cdsp_mem_noc", - .id =3D SC8180X_SLAVE_CDSP_MEM_NOC, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_COMPUTE_NOC } + .link_nodes =3D { &mas_qnm_cmpnoc, NULL } }; =20 static struct qcom_icc_node slv_qhs_a1_noc_cfg =3D { .name =3D "slv_qhs_a1_noc_cfg", - .id =3D SC8180X_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_A1NOC_CFG } + .link_nodes =3D { &mas_qhm_a1noc_cfg, NULL } }; =20 static struct qcom_icc_node slv_qhs_a2_noc_cfg =3D { .name =3D "slv_qhs_a2_noc_cfg", - .id =3D SC8180X_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_A2NOC_CFG } + .link_nodes =3D { &mas_qhm_a2noc_cfg, NULL } }; =20 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center =3D { .name =3D "slv_qhs_ahb2phy_refgen_center", - .id =3D SC8180X_SLAVE_AHB2PHY_CENTER, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east =3D { .name =3D "slv_qhs_ahb2phy_refgen_east", - .id =3D SC8180X_SLAVE_AHB2PHY_EAST, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west =3D { .name =3D "slv_qhs_ahb2phy_refgen_west", - .id =3D SC8180X_SLAVE_AHB2PHY_WEST, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_ahb2phy_south =3D { .name =3D "slv_qhs_ahb2phy_south", - .id =3D SC8180X_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_aop =3D { .name =3D "slv_qhs_aop", - .id =3D SC8180X_SLAVE_AOP, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_aoss =3D { .name =3D "slv_qhs_aoss", - .id =3D SC8180X_SLAVE_AOSS, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_camera_cfg =3D { .name =3D "slv_qhs_camera_cfg", - .id =3D SC8180X_SLAVE_CAMERA_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_clk_ctl =3D { .name =3D "slv_qhs_clk_ctl", - .id =3D SC8180X_SLAVE_CLK_CTL, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_compute_dsp =3D { .name =3D "slv_qhs_compute_dsp", - .id =3D SC8180X_SLAVE_CDSP_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_cpr_cx =3D { .name =3D "slv_qhs_cpr_cx", - .id =3D SC8180X_SLAVE_RBCPR_CX_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_cpr_mmcx =3D { .name =3D "slv_qhs_cpr_mmcx", - .id =3D SC8180X_SLAVE_RBCPR_MMCX_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_cpr_mx =3D { .name =3D "slv_qhs_cpr_mx", - .id =3D SC8180X_SLAVE_RBCPR_MX_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_crypto0_cfg =3D { .name =3D "slv_qhs_crypto0_cfg", - .id =3D SC8180X_SLAVE_CRYPTO_0_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_ddrss_cfg =3D { .name =3D "slv_qhs_ddrss_cfg", - .id =3D SC8180X_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_CNOC_DC_NOC } + .link_nodes =3D { &mas_qhm_cnoc_dc_noc, NULL } }; =20 static struct qcom_icc_node slv_qhs_display_cfg =3D { .name =3D "slv_qhs_display_cfg", - .id =3D SC8180X_SLAVE_DISPLAY_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_emac_cfg =3D { .name =3D "slv_qhs_emac_cfg", - .id =3D SC8180X_SLAVE_EMAC_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_glm =3D { .name =3D "slv_qhs_glm", - .id =3D SC8180X_SLAVE_GLM, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_gpuss_cfg =3D { .name =3D "slv_qhs_gpuss_cfg", - .id =3D SC8180X_SLAVE_GRAPHICS_3D_CFG, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_imem_cfg =3D { .name =3D "slv_qhs_imem_cfg", - .id =3D SC8180X_SLAVE_IMEM_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_ipa =3D { .name =3D "slv_qhs_ipa", - .id =3D SC8180X_SLAVE_IPA_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_mnoc_cfg =3D { .name =3D "slv_qhs_mnoc_cfg", - .id =3D SC8180X_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_CNOC_MNOC_CFG } + .link_nodes =3D { &mas_qhm_mnoc_cfg, NULL } }; =20 static struct qcom_icc_node slv_qhs_npu_cfg =3D { .name =3D "slv_qhs_npu_cfg", - .id =3D SC8180X_SLAVE_NPU_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_pcie0_cfg =3D { .name =3D "slv_qhs_pcie0_cfg", - .id =3D SC8180X_SLAVE_PCIE_0_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_pcie1_cfg =3D { .name =3D "slv_qhs_pcie1_cfg", - .id =3D SC8180X_SLAVE_PCIE_1_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_pcie2_cfg =3D { .name =3D "slv_qhs_pcie2_cfg", - .id =3D SC8180X_SLAVE_PCIE_2_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_pcie3_cfg =3D { .name =3D "slv_qhs_pcie3_cfg", - .id =3D SC8180X_SLAVE_PCIE_3_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_pdm =3D { .name =3D "slv_qhs_pdm", - .id =3D SC8180X_SLAVE_PDM, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_pimem_cfg =3D { .name =3D "slv_qhs_pimem_cfg", - .id =3D SC8180X_SLAVE_PIMEM_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_prng =3D { .name =3D "slv_qhs_prng", - .id =3D SC8180X_SLAVE_PRNG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_qdss_cfg =3D { .name =3D "slv_qhs_qdss_cfg", - .id =3D SC8180X_SLAVE_QDSS_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_qspi_0 =3D { .name =3D "slv_qhs_qspi_0", - .id =3D SC8180X_SLAVE_QSPI_0, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_qspi_1 =3D { .name =3D "slv_qhs_qspi_1", - .id =3D SC8180X_SLAVE_QSPI_1, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_qupv3_east0 =3D { .name =3D "slv_qhs_qupv3_east0", - .id =3D SC8180X_SLAVE_QUP_1, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_qupv3_east1 =3D { .name =3D "slv_qhs_qupv3_east1", - .id =3D SC8180X_SLAVE_QUP_2, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_qupv3_west =3D { .name =3D "slv_qhs_qupv3_west", - .id =3D SC8180X_SLAVE_QUP_0, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_sdc2 =3D { .name =3D "slv_qhs_sdc2", - .id =3D SC8180X_SLAVE_SDCC_2, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_sdc4 =3D { .name =3D "slv_qhs_sdc4", - .id =3D SC8180X_SLAVE_SDCC_4, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_security =3D { .name =3D "slv_qhs_security", - .id =3D SC8180X_SLAVE_SECURITY, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_snoc_cfg =3D { .name =3D "slv_qhs_snoc_cfg", - .id =3D SC8180X_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_SNOC_CFG } + .link_nodes =3D { &mas_qhm_snoc_cfg, NULL } }; =20 static struct qcom_icc_node slv_qhs_spss_cfg =3D { .name =3D "slv_qhs_spss_cfg", - .id =3D SC8180X_SLAVE_SPSS_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_tcsr =3D { .name =3D "slv_qhs_tcsr", - .id =3D SC8180X_SLAVE_TCSR, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_tlmm_east =3D { .name =3D "slv_qhs_tlmm_east", - .id =3D SC8180X_SLAVE_TLMM_EAST, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_tlmm_south =3D { .name =3D "slv_qhs_tlmm_south", - .id =3D SC8180X_SLAVE_TLMM_SOUTH, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_tlmm_west =3D { .name =3D "slv_qhs_tlmm_west", - .id =3D SC8180X_SLAVE_TLMM_WEST, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_tsif =3D { .name =3D "slv_qhs_tsif", - .id =3D SC8180X_SLAVE_TSIF, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_ufs_card_cfg =3D { .name =3D "slv_qhs_ufs_card_cfg", - .id =3D SC8180X_SLAVE_UFS_CARD_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_ufs_mem0_cfg =3D { .name =3D "slv_qhs_ufs_mem0_cfg", - .id =3D SC8180X_SLAVE_UFS_MEM_0_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_ufs_mem1_cfg =3D { .name =3D "slv_qhs_ufs_mem1_cfg", - .id =3D SC8180X_SLAVE_UFS_MEM_1_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_usb3_0 =3D { .name =3D "slv_qhs_usb3_0", - .id =3D SC8180X_SLAVE_USB3, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_usb3_1 =3D { .name =3D "slv_qhs_usb3_1", - .id =3D SC8180X_SLAVE_USB3_1, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_usb3_2 =3D { .name =3D "slv_qhs_usb3_2", - .id =3D SC8180X_SLAVE_USB3_2, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_venus_cfg =3D { .name =3D "slv_qhs_venus_cfg", - .id =3D SC8180X_SLAVE_VENUS_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg =3D { .name =3D "slv_qhs_vsense_ctrl_cfg", - .id =3D SC8180X_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_srvc_cnoc =3D { .name =3D "slv_srvc_cnoc", - .id =3D SC8180X_SLAVE_SERVICE_CNOC, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_gemnoc =3D { .name =3D "slv_qhs_gemnoc", - .id =3D SC8180X_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_GEM_NOC_CFG } + .link_nodes =3D { &mas_qhm_gemnoc_cfg, NULL } }; =20 static struct qcom_icc_node slv_qhs_llcc =3D { .name =3D "slv_qhs_llcc", - .id =3D SC8180X_SLAVE_LLCC_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg =3D { .name =3D "slv_qhs_mdsp_ms_mpu_cfg", - .id =3D SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qns_ecc =3D { .name =3D "slv_qns_ecc", - .id =3D SC8180X_SLAVE_ECC, .channels =3D 1, - .buswidth =3D 32 + .buswidth =3D 32, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qns_gem_noc_snoc =3D { .name =3D "slv_qns_gem_noc_snoc", - .id =3D SC8180X_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_GEM_NOC_SNOC } + .link_nodes =3D { &mas_qnm_gemnoc, NULL } }; =20 static struct qcom_icc_node slv_qns_llcc =3D { .name =3D "slv_qns_llcc", - .id =3D SC8180X_SLAVE_LLCC, .channels =3D 8, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_LLCC } + .link_nodes =3D { &mas_llcc_mc, NULL } }; =20 static struct qcom_icc_node slv_srvc_gemnoc =3D { .name =3D "slv_srvc_gemnoc", - .id =3D SC8180X_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_srvc_gemnoc1 =3D { .name =3D "slv_srvc_gemnoc1", - .id =3D SC8180X_SLAVE_SERVICE_GEM_NOC_1, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_ebi =3D { .name =3D "slv_ebi", - .id =3D SC8180X_SLAVE_EBI_CH0, .channels =3D 8, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qns2_mem_noc =3D { .name =3D "slv_qns2_mem_noc", - .id =3D SC8180X_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_MNOC_SF_MEM_NOC } + .link_nodes =3D { &mas_qnm_mnoc_sf, NULL } }; =20 static struct qcom_icc_node slv_qns_mem_noc_hf =3D { .name =3D "slv_qns_mem_noc_hf", - .id =3D SC8180X_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_MNOC_HF_MEM_NOC } + .link_nodes =3D { &mas_qnm_mnoc_hf, NULL } }; =20 static struct qcom_icc_node slv_srvc_mnoc =3D { .name =3D "slv_srvc_mnoc", - .id =3D SC8180X_SLAVE_SERVICE_MNOC, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qhs_apss =3D { .name =3D "slv_qhs_apss", - .id =3D SC8180X_SLAVE_APPSS, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qns_cnoc =3D { .name =3D "slv_qns_cnoc", - .id =3D SC8180X_SNOC_CNOC_SLV, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_SNOC_CNOC_MAS } + .link_nodes =3D { &mas_qnm_snoc, NULL } }; =20 static struct qcom_icc_node slv_qns_gemnoc_gc =3D { .name =3D "slv_qns_gemnoc_gc", - .id =3D SC8180X_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_SNOC_GC_MEM_NOC } + .link_nodes =3D { &mas_qnm_snoc_gc, NULL } }; =20 static struct qcom_icc_node slv_qns_gemnoc_sf =3D { .name =3D "slv_qns_gemnoc_sf", - .id =3D SC8180X_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC8180X_MASTER_SNOC_SF_MEM_NOC } + .link_nodes =3D { &mas_qnm_snoc_sf, NULL } }; =20 static struct qcom_icc_node slv_qxs_imem =3D { .name =3D "slv_qxs_imem", - .id =3D SC8180X_SLAVE_OCIMEM, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qxs_pimem =3D { .name =3D "slv_qxs_pimem", - .id =3D SC8180X_SLAVE_PIMEM, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_srvc_snoc =3D { .name =3D "slv_srvc_snoc", - .id =3D SC8180X_SLAVE_SERVICE_SNOC, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_xs_pcie_0 =3D { .name =3D "slv_xs_pcie_0", - .id =3D SC8180X_SLAVE_PCIE_0, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_xs_pcie_1 =3D { .name =3D "slv_xs_pcie_1", - .id =3D SC8180X_SLAVE_PCIE_1, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_xs_pcie_2 =3D { .name =3D "slv_xs_pcie_2", - .id =3D SC8180X_SLAVE_PCIE_2, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_xs_pcie_3 =3D { .name =3D "slv_xs_pcie_3", - .id =3D SC8180X_SLAVE_PCIE_3, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_xs_qdss_stm =3D { .name =3D "slv_xs_qdss_stm", - .id =3D SC8180X_SLAVE_QDSS_STM, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_xs_sys_tcu_cfg =3D { .name =3D "slv_xs_sys_tcu_cfg", - .id =3D SC8180X_SLAVE_TCU, .channels =3D 1, - .buswidth =3D 8 + .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qup_core_0 =3D { .name =3D "slv_qup_core_0", - .id =3D SC8180X_SLAVE_QUP_CORE_0, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qup_core_1 =3D { .name =3D "slv_qup_core_1", - .id =3D SC8180X_SLAVE_QUP_CORE_1, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node slv_qup_core_2 =3D { .name =3D "slv_qup_core_2", - .id =3D SC8180X_SLAVE_QUP_CORE_2, .channels =3D 1, - .buswidth =3D 4 + .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1767,6 +1761,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc8180x_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1774,6 +1769,7 @@ static const struct qcom_icc_desc sc8180x_aggre1_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1781,6 +1777,7 @@ static const struct qcom_icc_desc sc8180x_aggre2_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1788,6 +1785,7 @@ static const struct qcom_icc_desc sc8180x_camnoc_virt= =3D { }; =20 static const struct qcom_icc_desc sc8180x_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1795,6 +1793,7 @@ static const struct qcom_icc_desc sc8180x_compute_noc= =3D { }; =20 static const struct qcom_icc_desc sc8180x_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1802,11 +1801,13 @@ static const struct qcom_icc_desc sc8180x_config_no= c =3D { }; =20 static const struct qcom_icc_desc sc8180x_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; =20 static const struct qcom_icc_desc sc8180x_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1814,6 +1815,7 @@ static const struct qcom_icc_desc sc8180x_gem_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1821,6 +1823,7 @@ static const struct qcom_icc_desc sc8180x_mc_virt = =3D { }; =20 static const struct qcom_icc_desc sc8180x_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1828,6 +1831,7 @@ static const struct qcom_icc_desc sc8180x_mmss_noc = =3D { }; =20 static const struct qcom_icc_desc sc8180x_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, @@ -1848,6 +1852,7 @@ static struct qcom_icc_node * const qup_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc8180x_qup_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D qup_virt_nodes, .num_nodes =3D ARRAY_SIZE(qup_virt_nodes), .bcms =3D qup_virt_bcms, diff --git a/drivers/interconnect/qcom/sc8180x.h b/drivers/interconnect/qco= m/sc8180x.h deleted file mode 100644 index f8d90598335a1d334a6b783bfe8569ab3c46b4f2..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sc8180x.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC8180X interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8180X_H -#define __DRIVERS_INTERCONNECT_QCOM_SC8180X_H - -#define SC8180X_MASTER_A1NOC_CFG 1 -#define SC8180X_MASTER_UFS_CARD 2 -#define SC8180X_MASTER_UFS_GEN4 3 -#define SC8180X_MASTER_UFS_MEM 4 -#define SC8180X_MASTER_USB3 5 -#define SC8180X_MASTER_USB3_1 6 -#define SC8180X_MASTER_USB3_2 7 -#define SC8180X_MASTER_A2NOC_CFG 8 -#define SC8180X_MASTER_QDSS_BAM 9 -#define SC8180X_MASTER_QSPI_0 10 -#define SC8180X_MASTER_QSPI_1 11 -#define SC8180X_MASTER_QUP_0 12 -#define SC8180X_MASTER_QUP_1 13 -#define SC8180X_MASTER_QUP_2 14 -#define SC8180X_MASTER_SENSORS_AHB 15 -#define SC8180X_MASTER_CRYPTO_CORE_0 16 -#define SC8180X_MASTER_IPA 17 -#define SC8180X_MASTER_EMAC 18 -#define SC8180X_MASTER_PCIE 19 -#define SC8180X_MASTER_PCIE_1 20 -#define SC8180X_MASTER_PCIE_2 21 -#define SC8180X_MASTER_PCIE_3 22 -#define SC8180X_MASTER_QDSS_ETR 23 -#define SC8180X_MASTER_SDCC_2 24 -#define SC8180X_MASTER_SDCC_4 25 -#define SC8180X_MASTER_CAMNOC_HF0_UNCOMP 26 -#define SC8180X_MASTER_CAMNOC_HF1_UNCOMP 27 -#define SC8180X_MASTER_CAMNOC_SF_UNCOMP 28 -#define SC8180X_MASTER_NPU 29 -#define SC8180X_SNOC_CNOC_MAS 30 -#define SC8180X_MASTER_CNOC_DC_NOC 31 -#define SC8180X_MASTER_AMPSS_M0 32 -#define SC8180X_MASTER_GPU_TCU 33 -#define SC8180X_MASTER_SYS_TCU 34 -#define SC8180X_MASTER_GEM_NOC_CFG 35 -#define SC8180X_MASTER_COMPUTE_NOC 36 -#define SC8180X_MASTER_GRAPHICS_3D 37 -#define SC8180X_MASTER_MNOC_HF_MEM_NOC 38 -#define SC8180X_MASTER_MNOC_SF_MEM_NOC 39 -#define SC8180X_MASTER_GEM_NOC_PCIE_SNOC 40 -#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41 -#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42 -#define SC8180X_MASTER_ECC 43 -/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SC8180X_MASTER_LLCC 45 -#define SC8180X_MASTER_CNOC_MNOC_CFG 46 -#define SC8180X_MASTER_CAMNOC_HF0 47 -#define SC8180X_MASTER_CAMNOC_HF1 48 -#define SC8180X_MASTER_CAMNOC_SF 49 -#define SC8180X_MASTER_MDP_PORT0 50 -#define SC8180X_MASTER_MDP_PORT1 51 -#define SC8180X_MASTER_ROTATOR 52 -#define SC8180X_MASTER_VIDEO_P0 53 -#define SC8180X_MASTER_VIDEO_P1 54 -#define SC8180X_MASTER_VIDEO_PROC 55 -#define SC8180X_MASTER_SNOC_CFG 56 -#define SC8180X_A1NOC_SNOC_MAS 57 -#define SC8180X_A2NOC_SNOC_MAS 58 -#define SC8180X_MASTER_GEM_NOC_SNOC 59 -#define SC8180X_MASTER_PIMEM 60 -#define SC8180X_MASTER_GIC 61 -#define SC8180X_MASTER_MNOC_HF_MEM_NOC_DISPLAY 62 -#define SC8180X_MASTER_MNOC_SF_MEM_NOC_DISPLAY 63 -#define SC8180X_MASTER_LLCC_DISPLAY 64 -#define SC8180X_MASTER_MDP_PORT0_DISPLAY 65 -#define SC8180X_MASTER_MDP_PORT1_DISPLAY 66 -#define SC8180X_MASTER_ROTATOR_DISPLAY 67 -#define SC8180X_A1NOC_SNOC_SLV 68 -#define SC8180X_SLAVE_SERVICE_A1NOC 69 -#define SC8180X_A2NOC_SNOC_SLV 70 -#define SC8180X_SLAVE_ANOC_PCIE_GEM_NOC 71 -#define SC8180X_SLAVE_SERVICE_A2NOC 72 -#define SC8180X_SLAVE_CAMNOC_UNCOMP 73 -#define SC8180X_SLAVE_CDSP_MEM_NOC 74 -#define SC8180X_SLAVE_A1NOC_CFG 75 -#define SC8180X_SLAVE_A2NOC_CFG 76 -#define SC8180X_SLAVE_AHB2PHY_CENTER 77 -#define SC8180X_SLAVE_AHB2PHY_EAST 78 -#define SC8180X_SLAVE_AHB2PHY_WEST 79 -#define SC8180X_SLAVE_AHB2PHY_SOUTH 80 -#define SC8180X_SLAVE_AOP 81 -#define SC8180X_SLAVE_AOSS 82 -#define SC8180X_SLAVE_CAMERA_CFG 83 -#define SC8180X_SLAVE_CLK_CTL 84 -#define SC8180X_SLAVE_CDSP_CFG 85 -#define SC8180X_SLAVE_RBCPR_CX_CFG 86 -#define SC8180X_SLAVE_RBCPR_MMCX_CFG 87 -#define SC8180X_SLAVE_RBCPR_MX_CFG 88 -#define SC8180X_SLAVE_CRYPTO_0_CFG 89 -#define SC8180X_SLAVE_CNOC_DDRSS 90 -#define SC8180X_SLAVE_DISPLAY_CFG 91 -#define SC8180X_SLAVE_EMAC_CFG 92 -#define SC8180X_SLAVE_GLM 93 -#define SC8180X_SLAVE_GRAPHICS_3D_CFG 94 -#define SC8180X_SLAVE_IMEM_CFG 95 -#define SC8180X_SLAVE_IPA_CFG 96 -#define SC8180X_SLAVE_CNOC_MNOC_CFG 97 -#define SC8180X_SLAVE_NPU_CFG 98 -#define SC8180X_SLAVE_PCIE_0_CFG 99 -#define SC8180X_SLAVE_PCIE_1_CFG 100 -#define SC8180X_SLAVE_PCIE_2_CFG 101 -#define SC8180X_SLAVE_PCIE_3_CFG 102 -#define SC8180X_SLAVE_PDM 103 -#define SC8180X_SLAVE_PIMEM_CFG 104 -#define SC8180X_SLAVE_PRNG 105 -#define SC8180X_SLAVE_QDSS_CFG 106 -#define SC8180X_SLAVE_QSPI_0 107 -#define SC8180X_SLAVE_QSPI_1 108 -#define SC8180X_SLAVE_QUP_1 109 -#define SC8180X_SLAVE_QUP_2 110 -#define SC8180X_SLAVE_QUP_0 111 -#define SC8180X_SLAVE_SDCC_2 112 -#define SC8180X_SLAVE_SDCC_4 113 -#define SC8180X_SLAVE_SECURITY 114 -#define SC8180X_SLAVE_SNOC_CFG 115 -#define SC8180X_SLAVE_SPSS_CFG 116 -#define SC8180X_SLAVE_TCSR 117 -#define SC8180X_SLAVE_TLMM_EAST 118 -#define SC8180X_SLAVE_TLMM_SOUTH 119 -#define SC8180X_SLAVE_TLMM_WEST 120 -#define SC8180X_SLAVE_TSIF 121 -#define SC8180X_SLAVE_UFS_CARD_CFG 122 -#define SC8180X_SLAVE_UFS_MEM_0_CFG 123 -#define SC8180X_SLAVE_UFS_MEM_1_CFG 124 -#define SC8180X_SLAVE_USB3 125 -#define SC8180X_SLAVE_USB3_1 126 -#define SC8180X_SLAVE_USB3_2 127 -#define SC8180X_SLAVE_VENUS_CFG 128 -#define SC8180X_SLAVE_VSENSE_CTRL_CFG 129 -#define SC8180X_SLAVE_SERVICE_CNOC 130 -#define SC8180X_SLAVE_GEM_NOC_CFG 131 -#define SC8180X_SLAVE_LLCC_CFG 132 -#define SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG 133 -#define SC8180X_SLAVE_ECC 134 -#define SC8180X_SLAVE_GEM_NOC_SNOC 135 -#define SC8180X_SLAVE_LLCC 136 -#define SC8180X_SLAVE_SERVICE_GEM_NOC 137 -#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138 -/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8180X_SLAVE_EBI_CH0 140 -#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141 -#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142 -#define SC8180X_SLAVE_SERVICE_MNOC 143 -#define SC8180X_SLAVE_APPSS 144 -#define SC8180X_SNOC_CNOC_SLV 145 -#define SC8180X_SLAVE_SNOC_GEM_NOC_GC 146 -#define SC8180X_SLAVE_SNOC_GEM_NOC_SF 147 -#define SC8180X_SLAVE_OCIMEM 148 -#define SC8180X_SLAVE_PIMEM 149 -#define SC8180X_SLAVE_SERVICE_SNOC 150 -#define SC8180X_SLAVE_PCIE_0 151 -#define SC8180X_SLAVE_PCIE_1 152 -#define SC8180X_SLAVE_PCIE_2 153 -#define SC8180X_SLAVE_PCIE_3 154 -#define SC8180X_SLAVE_QDSS_STM 155 -#define SC8180X_SLAVE_TCU 156 -#define SC8180X_SLAVE_LLCC_DISPLAY 157 -#define SC8180X_SLAVE_EBI_CH0_DISPLAY 158 -#define SC8180X_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 159 -#define SC8180X_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 160 - -#define SC8180X_MASTER_QUP_CORE_0 163 -#define SC8180X_MASTER_QUP_CORE_1 164 -#define SC8180X_MASTER_QUP_CORE_2 165 -#define SC8180X_SLAVE_QUP_CORE_0 166 -#define SC8180X_SLAVE_QUP_CORE_1 167 -#define SC8180X_SLAVE_QUP_CORE_2 168 - -#endif --=20 2.39.5