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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556383d33f3sm298321e87.68.2025.07.04.09.35.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 09:35:28 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 04 Jul 2025 19:35:16 +0300 Subject: [PATCH v2 04/28] interconnect: qcom: rpmh: make link_nodes a NULL_terminated array Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-rework-icc-v2-4-875fac996ef5@oss.qualcomm.com> References: <20250704-rework-icc-v2-0-875fac996ef5@oss.qualcomm.com> In-Reply-To: <20250704-rework-icc-v2-0-875fac996ef5@oss.qualcomm.com> To: Georgi Djakov , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=42183; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=pVxV8zjHcQ9NxikU+1e/gZLn5//6/fURrkFvfHGQyPA=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ0YG09GQB5MdUj2LhEOfiH/8c8snSyHLKUEnS9tbUeySc 4POEodORmMWBkYuBlkxRRafgpapMZuSwz7smFoPM4iVCWQKAxenAEykP5mDYdUmk01TZx94b1/T furfje6csP8FUQl3Le55fJXZYv9bf8nuS9UHT9or667SfPqAr+jYfU/rW6suNvnFfvK9ekW/oPJ 6xxuD1+k/1v7/6nmjXy9L9fiSC+pl06cJCgYY7vu6OmBZ8s+vpwp2l5eamjeuTw+vZtxx8uBWls vKn1O39+tt6A7PF1zlsG61jcR2sVCOE/78+1VFJ0xv+KunktS2O938cVNARr61r3Ps4mleDaUbt y2tfyOfOWliaejh81f3fJFRPH5MNqz9CtuX4tayLHuekCORL9kX8VYmZ96/c3Ka3c1PDWZxVbKi Uc4PfnZlqnklXrPKElcJV3LjTJ9zs69KVOB1Q7Ky7l8jAA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA0MDEyNiBTYWx0ZWRfX/Y38nMY/q0/r 7bjSecHfde1SjZNV6vVhtXCRTNnDFppOMuvjtIeuC5DXfR9ZdFu93YzsclEC4XFlAjMWvLuBY4j UJVVClFmSdFid30s1zoqZOnwAvOLvGdETkGCeClbqustxrQRUSYoAaoY6keT+J4pNRjAjCYP6/4 uvaLWRscbKC/dSZ4sHfpSxHns/weQiOFSc7DJQpJvnmtErNL6q7Wg/4s3679I+TpI6KymV6Uz4Z nicz+H1AlqduC04wVmrlKo9cC0c3eyGwFduLLpfGXvKUPn/yp268OaFd/Y83DhOJvVQEqlKofxz bfqM2zOYsTltMTO3/59d+PLLVhPWbO6SshwEmmMYRYSxx7wMifPG3Da2cQIlDVRAT7BaNNwLC3Z C2TTAXXyjvTN28kn+rkUgraJRT8JlbAgfO8+HYn4vRxhSRpAyvGOgfiDgsiA+Ts/2UegbGsw X-Proofpoint-GUID: gwiNZlUiB9uW-IdYKel3yIbKt-baKiD0 X-Proofpoint-ORIG-GUID: gwiNZlUiB9uW-IdYKel3yIbKt-baKiD0 X-Authority-Analysis: v=2.4 cv=TqPmhCXh c=1 sm=1 tr=0 ts=686802d3 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=awKHyal4sbTCVpb1gUYA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_06,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 mlxlogscore=928 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507040126 Having the .num_links as a separate struct field can provoke errors as it is easy to omit it or to put an incorrect value into that field. Turn .link_nodes into a NULL-terminated array, removing a need for a separate .num_links field if .link_nodes is being used. This creates a deviation between non-dynamic and dynamic ID cases, but it won't stay like that for too long. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpmh.c | 7 +- drivers/interconnect/qcom/icc-rpmh.h | 4 +- drivers/interconnect/qcom/sa8775p.c | 395 ++++++++++++++++++-------------= ---- 3 files changed, 207 insertions(+), 199 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qc= om/icc-rpmh.c index 7854e3a60d97eb3cdb0a5c1f1b77a96afc104009..941692cbaf208c66a27dda2e690= 2b2f26f605840 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -302,10 +302,11 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) node->data =3D qn; icc_node_add(node, provider); =20 - for (j =3D 0; j < qn->num_links; j++) { - if (desc->alloc_dyn_id) + if (desc->alloc_dyn_id) { + for (j =3D 0; qn->link_nodes[j]; j++) icc_link_nodes(node, &qn->link_nodes[j]->node); - else + } else { + for (j =3D 0; j < qn->num_links; j++) icc_link_create(node, qn->links[j]); } =20 diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qc= om/icc-rpmh.h index 0018aa74187edcac9a0492c737771d957a133cc0..742941a296ac0a2e3d3e7147c25= f750965a36647 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -83,7 +83,6 @@ struct qcom_icc_qosbox { * @name: the node name used in debugfs * @links: an array of nodes where we can go next while traversing * @id: a unique node identifier - * @link_nodes: links associated with this node * @node: icc_node associated with this node * @num_links: the total number of @links * @channels: num of channels at this node @@ -93,12 +92,12 @@ struct qcom_icc_qosbox { * @bcms: list of bcms associated with this logical node * @num_bcms: num of @bcms * @qosbox: QoS config data associated with node + * @link_nodes: links associated with this node */ struct qcom_icc_node { const char *name; u16 links[MAX_LINKS]; u16 id; - struct qcom_icc_node **link_nodes; struct icc_node *node; u16 num_links; u16 channels; @@ -108,6 +107,7 @@ struct qcom_icc_node { struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE]; size_t num_bcms; const struct qcom_icc_qosbox *qosbox; + struct qcom_icc_node *link_nodes[]; }; =20 /** diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qco= m/sa8775p.c index 6bbe2fe03f791dd5d3606114d71d62057ddc52d2..a7049eb22d1e064afea17812637= b720f907de90e 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -213,192 +213,168 @@ static struct qcom_icc_node qxm_qup3 =3D { .name =3D "qxm_qup3", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_emac_1 =3D { .name =3D "xm_emac_1", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_usb2_2 =3D { .name =3D "xm_usb2_2", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_crypto_0 =3D { .name =3D "qxm_crypto_0", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_crypto_1 =3D { .name =3D "qxm_crypto_1", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup0_core_slave }, + .link_nodes =3D { &qup0_core_slave, NULL }, }; =20 static struct qcom_icc_node qup1_core_master =3D { .name =3D "qup1_core_master", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup1_core_slave }, + .link_nodes =3D { &qup1_core_slave, NULL }, }; =20 static struct qcom_icc_node qup2_core_master =3D { .name =3D "qup2_core_master", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup2_core_slave }, + .link_nodes =3D { &qup2_core_slave, NULL }, }; =20 static struct qcom_icc_node qup3_core_master =3D { .name =3D "qup3_core_master", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qup3_core_slave }, + .link_nodes =3D { &qup3_core_slave, NULL }, }; =20 static struct qcom_icc_node qnm_gemnoc_cnoc =3D { .name =3D "qnm_gemnoc_cnoc", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 82, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_ahb2phy2, &qhs_ahb2phy3, &qhs_anoc_throttle_cfg, &qhs_aoss, &qhs_apss, &qhs_boot_rom, @@ -438,1166 +414,1197 @@ static struct qcom_icc_node qnm_gemnoc_cnoc =3D { &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, &qns_snoc_cfg, &qxs_boot_imem, &qxs_imem, &qxs_pimem, - &xs_qdss_stm, &xs_sys_tcu_cfg }, + &xs_qdss_stm, &xs_sys_tcu_cfg, NULL }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 }, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1, NULL }, }; =20 static struct qcom_icc_node qnm_cnoc_dc_noc =3D { .name =3D "qnm_cnoc_dc_noc", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_llcc, &qns_gemnoc }, + .link_nodes =3D { &qhs_llcc, &qns_gemnoc, NULL }, }; =20 static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node chm_apps =3D { .name =3D "chm_apps", .channels =3D 4, .buswidth =3D 32, - .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, - &qns_pcie }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, }; =20 static struct qcom_icc_node qnm_cmpnoc0 =3D { .name =3D "qnm_cmpnoc0", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_cmpnoc1 =3D { .name =3D "qnm_cmpnoc1", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_gemnoc_cfg =3D { .name =3D "qnm_gemnoc_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_even_gemnoc, &srvc_odd= _gemnoc, - &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, + .link_nodes =3D { &srvc_even_gemnoc, &srvc_odd_gemnoc, + &srvc_sys_gemnoc, &srvc_sys_gemnoc_2, NULL }, }; =20 static struct qcom_icc_node qnm_gpdsp_sail =3D { .name =3D "qnm_gpdsp_sail", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie }, + .link_nodes =3D { &qns_llcc, &qns_pcie, NULL }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, - &qns_pcie }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, }; =20 static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc }, + .link_nodes =3D { &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 3, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, - &qns_pcie }, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, }; =20 static struct qcom_icc_node qxm_dsp0 =3D { .name =3D "qxm_dsp0", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc }, + .link_nodes =3D { &qns_gp_dsp_sail_noc, NULL }, }; =20 static struct qcom_icc_node qxm_dsp1 =3D { .name =3D "qxm_dsp1", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc }, + .link_nodes =3D { &qns_gp_dsp_sail_noc, NULL }, }; =20 static struct qcom_icc_node qhm_config_noc =3D { .name =3D "qhm_config_noc", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 6, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_lpass_core, &qhs_lpass_= lpi, - &qhs_lpass_mpu, &qhs_lpass_top, - &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, + .link_nodes =3D { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL }, }; =20 static struct qcom_icc_node qxm_lpass_dsp =3D { .name =3D "qxm_lpass_dsp", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 4, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhs_lpass_top, &qns_sysnoc, - &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, + .link_nodes =3D { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc, NULL }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", .channels =3D 8, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &ebi }, + .link_nodes =3D { &ebi, NULL }, }; =20 static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_mdp0_0 =3D { .name =3D "qnm_mdp0_0", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qnm_mdp0_1 =3D { .name =3D "qnm_mdp0_1", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qnm_mdp1_0 =3D { .name =3D "qnm_mdp1_0", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qnm_mdp1_1 =3D { .name =3D "qnm_mdp1_1", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qnm_mnoc_hf_cfg =3D { .name =3D "qnm_mnoc_hf_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_mnoc_hf }, + .link_nodes =3D { &srvc_mnoc_hf, NULL }, }; =20 static struct qcom_icc_node qnm_mnoc_sf_cfg =3D { .name =3D "qnm_mnoc_sf_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_mnoc_sf }, + .link_nodes =3D { &srvc_mnoc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_video1 =3D { .name =3D "qnm_video1", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qhm_nsp_noc_config =3D { .name =3D "qhm_nsp_noc_config", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &service_nsp_noc }, + .link_nodes =3D { &service_nsp_noc, NULL }, }; =20 static struct qcom_icc_node qxm_nsp =3D { .name =3D "qxm_nsp", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_hcp, &qns_nsp_gemnoc }, + .link_nodes =3D { &qns_hcp, &qns_nsp_gemnoc, NULL }, }; =20 static struct qcom_icc_node qhm_nspb_noc_config =3D { .name =3D "qhm_nspb_noc_config", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &service_nspb_noc }, + .link_nodes =3D { &service_nspb_noc, NULL }, }; =20 static struct qcom_icc_node qxm_nspb =3D { .name =3D "qxm_nspb", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_nspb_hcp, &qns_nspb_gem= noc }, + .link_nodes =3D { &qns_nspb_hcp, &qns_nspb_gemnoc, NULL }, }; =20 static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes =3D { &qns_pcie_mem_noc, NULL }, }; =20 static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, + .link_nodes =3D { &qns_pcie_mem_noc, NULL }, }; =20 static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, + .link_nodes =3D { &qns_gemnoc_sf, NULL }, }; =20 static struct qcom_icc_node qnm_snoc_cfg =3D { .name =3D "qnm_snoc_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &srvc_snoc }, + .link_nodes =3D { &srvc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes =3D { &qns_gemnoc_gc, NULL }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, + .link_nodes =3D { &qns_gemnoc_gc, NULL }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, + .link_nodes =3D { &qnm_aggre1_noc, NULL }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, + .link_nodes =3D { &qnm_aggre2_noc, NULL }, }; =20 static struct qcom_icc_node qup0_core_slave =3D { .name =3D "qup0_core_slave", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qup1_core_slave =3D { .name =3D "qup1_core_slave", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qup2_core_slave =3D { .name =3D "qup2_core_slave", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qup3_core_slave =3D { .name =3D "qup3_core_slave", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ahb2phy1 =3D { .name =3D "qhs_ahb2phy1", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ahb2phy2 =3D { .name =3D "qhs_ahb2phy2", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ahb2phy3 =3D { .name =3D "qhs_ahb2phy3", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_anoc_throttle_cfg =3D { .name =3D "qhs_anoc_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_boot_rom =3D { .name =3D "qhs_boot_rom", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg =3D { .name =3D "qhs_camera_nrt_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { .name =3D "qhs_camera_rt_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_compute0_cfg =3D { .name =3D "qhs_compute0_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhm_nsp_noc_config }, + .link_nodes =3D { &qhm_nsp_noc_config, NULL }, }; =20 static struct qcom_icc_node qhs_compute1_cfg =3D { .name =3D "qhs_compute1_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhm_nspb_noc_config }, + .link_nodes =3D { &qhm_nspb_noc_config, NULL }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cpr_mmcx =3D { .name =3D "qhs_cpr_mmcx", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cpr_nspcx =3D { .name =3D "qhs_cpr_nspcx", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cx_rdpm =3D { .name =3D "qhs_cx_rdpm", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_display0_cfg =3D { .name =3D "qhs_display0_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_display0_rt_throttle_cfg =3D { .name =3D "qhs_display0_rt_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_display1_cfg =3D { .name =3D "qhs_display1_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_display1_rt_throttle_cfg =3D { .name =3D "qhs_display1_rt_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_emac0_cfg =3D { .name =3D "qhs_emac0_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_emac1_cfg =3D { .name =3D "qhs_emac1_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gp_dsp0_cfg =3D { .name =3D "qhs_gp_dsp0_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gp_dsp1_cfg =3D { .name =3D "qhs_gp_dsp1_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg =3D { .name =3D "qhs_gpdsp0_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gpdsp1_throttle_cfg =3D { .name =3D "qhs_gpdsp1_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg =3D { .name =3D "qhs_gpu_tcu_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_hwkm =3D { .name =3D "qhs_hwkm", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ipc_router =3D { .name =3D "qhs_ipc_router", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_lpass_cfg =3D { .name =3D "qhs_lpass_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qhm_config_noc }, + .link_nodes =3D { &qhm_config_noc, NULL }, }; =20 static struct qcom_icc_node qhs_lpass_throttle_cfg =3D { .name =3D "qhs_lpass_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_mx_rdpm =3D { .name =3D "qhs_mx_rdpm", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_mxc_rdpm =3D { .name =3D "qhs_mxc_rdpm", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pcie0_cfg =3D { .name =3D "qhs_pcie0_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pcie1_cfg =3D { .name =3D "qhs_pcie1_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pcie_rsc_cfg =3D { .name =3D "qhs_pcie_rsc_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg =3D { .name =3D "qhs_pcie_tcu_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pcie_throttle_cfg =3D { .name =3D "qhs_pcie_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pke_wrapper_cfg =3D { .name =3D "qhs_pke_wrapper_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qm_cfg =3D { .name =3D "qhs_qm_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qm_mpu_cfg =3D { .name =3D "qhs_qm_mpu_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qup2 =3D { .name =3D "qhs_qup2", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qup3 =3D { .name =3D "qhs_qup3", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_sail_throttle_cfg =3D { .name =3D "qhs_sail_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_security =3D { .name =3D "qhs_security", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_snoc_throttle_cfg =3D { .name =3D "qhs_snoc_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tsc_cfg =3D { .name =3D "qhs_tsc_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ufs_card_cfg =3D { .name =3D "qhs_ufs_card_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_usb2_0 =3D { .name =3D "qhs_usb2_0", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_usb3_0 =3D { .name =3D "qhs_usb3_0", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_usb3_1 =3D { .name =3D "qhs_usb3_1", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg =3D { .name =3D "qhs_venus_cvp_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg =3D { .name =3D "qhs_venus_v_cpu_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg =3D { .name =3D "qhs_venus_vcodec_throttle_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_ddrss_cfg =3D { .name =3D "qns_ddrss_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_cnoc_dc_noc }, + .link_nodes =3D { &qnm_cnoc_dc_noc, NULL }, }; =20 static struct qcom_icc_node qns_gpdsp_noc_cfg =3D { .name =3D "qns_gpdsp_noc_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_mnoc_hf_cfg =3D { .name =3D "qns_mnoc_hf_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_hf_cfg }, + .link_nodes =3D { &qnm_mnoc_hf_cfg, NULL }, }; =20 static struct qcom_icc_node qns_mnoc_sf_cfg =3D { .name =3D "qns_mnoc_sf_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_sf_cfg }, + .link_nodes =3D { &qnm_mnoc_sf_cfg, NULL }, }; =20 static struct qcom_icc_node qns_pcie_anoc_cfg =3D { .name =3D "qns_pcie_anoc_cfg", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_snoc_cfg =3D { .name =3D "qns_snoc_cfg", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_snoc_cfg }, + .link_nodes =3D { &qnm_snoc_cfg, NULL }, }; =20 static struct qcom_icc_node qxs_boot_imem =3D { .name =3D "qxs_boot_imem", .channels =3D 1, .buswidth =3D 16, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_pcie_0 =3D { .name =3D "xs_pcie_0", .channels =3D 1, .buswidth =3D 16, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_pcie_1 =3D { .name =3D "xs_pcie_1", .channels =3D 1, .buswidth =3D 32, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_gemnoc =3D { .name =3D "qns_gemnoc", .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gemnoc_cfg }, + .link_nodes =3D { &qnm_gemnoc_cfg, NULL }, }; =20 static struct qcom_icc_node qns_gem_noc_cnoc =3D { .name =3D "qns_gem_noc_cnoc", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc }, + .link_nodes =3D { &qnm_gemnoc_cnoc, NULL }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", .channels =3D 6, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &llcc_mc }, + .link_nodes =3D { &llcc_mc, NULL }, }; =20 static struct qcom_icc_node qns_pcie =3D { .name =3D "qns_pcie", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie }, + .link_nodes =3D { &qnm_gemnoc_pcie, NULL }, }; =20 static struct qcom_icc_node srvc_even_gemnoc =3D { .name =3D "srvc_even_gemnoc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_odd_gemnoc =3D { .name =3D "srvc_odd_gemnoc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_sys_gemnoc =3D { .name =3D "srvc_sys_gemnoc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_sys_gemnoc_2 =3D { .name =3D "srvc_sys_gemnoc_2", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_gp_dsp_sail_noc =3D { .name =3D "qns_gp_dsp_sail_noc", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_gpdsp_sail }, + .link_nodes =3D { &qnm_gpdsp_sail, NULL }, }; =20 static struct qcom_icc_node qhs_lpass_core =3D { .name =3D "qhs_lpass_core", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_lpass_lpi =3D { .name =3D "qhs_lpass_lpi", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_lpass_mpu =3D { .name =3D "qhs_lpass_mpu", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_lpass_top =3D { .name =3D "qhs_lpass_top", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_sysnoc =3D { .name =3D "qns_sysnoc", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_lpass_noc }, + .link_nodes =3D { &qnm_lpass_noc, NULL }, }; =20 static struct qcom_icc_node srvc_niu_aml_noc =3D { .name =3D "srvc_niu_aml_noc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { .name =3D "srvc_niu_lpass_agnoc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", .channels =3D 8, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, + .link_nodes =3D { &qnm_mnoc_hf, NULL }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, + .link_nodes =3D { &qnm_mnoc_sf, NULL }, }; =20 static struct qcom_icc_node srvc_mnoc_hf =3D { .name =3D "srvc_mnoc_hf", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_mnoc_sf =3D { .name =3D "srvc_mnoc_sf", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_hcp =3D { .name =3D "qns_hcp", .channels =3D 2, .buswidth =3D 32, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_nsp_gemnoc =3D { .name =3D "qns_nsp_gemnoc", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_cmpnoc0 }, + .link_nodes =3D { &qnm_cmpnoc0, NULL }, }; =20 static struct qcom_icc_node service_nsp_noc =3D { .name =3D "service_nsp_noc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_nspb_gemnoc =3D { .name =3D "qns_nspb_gemnoc", .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_cmpnoc1 }, + .link_nodes =3D { &qnm_cmpnoc1, NULL }, }; =20 static struct qcom_icc_node qns_nspb_hcp =3D { .name =3D "qns_nspb_hcp", .channels =3D 2, .buswidth =3D 32, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node service_nspb_noc =3D { .name =3D "service_nspb_noc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_pcie_mem_noc =3D { .name =3D "qns_pcie_mem_noc", .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_pcie }, + .link_nodes =3D { &qnm_pcie, NULL }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_snoc_gc }, + .link_nodes =3D { &qnm_snoc_gc, NULL }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .link_nodes =3D (struct qcom_icc_node *[]) { &qnm_snoc_sf }, + .link_nodes =3D { &qnm_snoc_sf, NULL }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { --=20 2.39.5