From nobody Wed Oct 8 00:10:00 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41CBE32718D for ; Fri, 4 Jul 2025 16:35:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751646964; cv=none; b=Aa0ygoYR3YoiAcjYbhQbYNFVp2+UyTYgKKKPMvjLayBeJyeHfj6DfeXXQt0gV1svKH5yoPLrmTwmazJKo+Is2uiFtuC/yAJaaxUsY2a3oDMgVCs8JQfDq4GMg3XeDkGgHGvdBgsNF0jvKYLhDRmnJqnTAJLXilZp+yLJiIn4e6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751646964; c=relaxed/simple; bh=bBbPgWexkDpRCqTXwnbgm6YFg8/jSw7JM3CzIo4s1w8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hR5b1r7zpC1zVOIa2l4gTpz5DlH21nwu4DokbSIB+xTNwUs8K0+BogtOPsjwICYO4fBfazC6QkHGNp0IfDrPORfj6zhK8PwnlY/6Ekyyywj3/dywZ7qCfz2S2vyj/w6vwo1/7u92Qt/BaCvHEevlBfeGSWagpBTcaoO49O3E47U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=S5UX0zl8; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="S5UX0zl8" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 564AQSoR009995 for ; Fri, 4 Jul 2025 16:35:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= va5aZWVKpIytVwsEgq7nQjCg9ua6/jvkJ8zXIIesBDQ=; b=S5UX0zl8MQdg5+4p Ecvrq8hDUhjlTVVnK93NFEL3t3312KMB/5D6uoKURTYaFfIOMgaT4E0fBLiPF8N/ bfyvCTf70BQHAyviXn23aWUQt4IcvWnwZ3QkYhInihYOOdx0SPCurQFAwCQYwVE6 rfdih1+LGEsliYlyFOgPTtOsZe2WkjHch85ePd9crdq27wE3gIXWXpbBX4i1aEMl KnIpt2KTASelFgxNj4suTKVPAFr54JFMBthGe8nR3EJVuvb/29hNY5i5Tmm4rzVM Yq+aUJKwmxVuV8UqR9GlGpSgiY6/bHHpjzKzC1dhGi567qWiDc2hhg18gbSjbhO2 QkdR6w== Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47pd6w0xkn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 04 Jul 2025 16:35:56 +0000 (GMT) Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-7d4576e83cdso285305485a.1 for ; Fri, 04 Jul 2025 09:35:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751646955; x=1752251755; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=va5aZWVKpIytVwsEgq7nQjCg9ua6/jvkJ8zXIIesBDQ=; b=taR9c6yG4wkB8bM+7HUyGFIIUL/W8g56gLPy2Gpklo1Fd6jjLsmw4NCbtPopFFbKPK xEnAn+niCPpMk8QcTG9FS8g34rxztmx0851dJGryiXkAZJn8b2IYZmR96u88jd/L3C78 4Cu3k0LAlJEzVhXng+JrMkOWaUH5IcIHMN9UQk047QyfWsc/MAryFN2i2v/KUbjxrhvh t7b6+wbp2so4ccDCIkhsiJch4lZtWafuTnZ74Jc8PkaLPwAfkrSGCiG/8PdApKtROk49 laB+ooAZe0v5zaFo9B2BnaMyxH+rItEZvqId3ET4Tqh7LVRmgjXzD8rnKD7nsn08fYxa 8Sdg== X-Forwarded-Encrypted: i=1; AJvYcCXmb5JeTRSgB52HUdWChvwXDZVbmsG7HVujMx40bgR0KBQJ5fYocsX4b93OdFVAi9GJOwLlhY8YuHVZwVQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwCUE8+Mj04sfm+L0Qs6ymd9yjqDPg+aX0uFqTxopNRGEa0YFA3 P7XNoRti4sCXDL3yeEZ6Gj+FhTkHY+g0MlqKKgrZAji3CFL/FP9ty5X2ueMSpIdYXWgLtE1gxEb mwpmmrwxSWbh5xAqLZnzpP3FnPSFYvGGMx5Bnx4AcXbQo1WK7WCCSiOP2sxr5VvLVZu2u5oUDEL 6lRw== X-Gm-Gg: ASbGncvq31LPrvAWdntC7BTkuJ3QoN/szkCsyAdfz1Xcldt02g/4U/jb0Lk1zxpkGJC DgagEYkG2pYuKJJr0O5P5MJIdDNzkMzxz6ogiwvR6VCApLsXe8GXzWm4HezRWMAsfwmllkniDwh JxKqPWQeHt00OXLWuOXTVvvv1QagdrkieOd1TIPXfpf3WYuJexOREF9Wp5PuSM4ENN34DDiUPss 64abHofK5kAaaszSQNF8oRDJNsgkI5bfj8JDWsCKP/fSyuqqT0NAWmfiXrGdLAe7IQoOQnW7LGR H6NMRpSgUrFqpdDt4/Ogi12cHxDPftlpkLyIUxTm3zqeEEDi+c4RNCaJApIsDxs0M64rsZPPnQ6 Yoz6xCcH3lV47oxlOSe/HSK0mvQeVpMrF5aU= X-Received: by 2002:a05:620a:4081:b0:7ca:efed:8644 with SMTP id af79cd13be357-7d5ddaa7c92mr437653185a.5.1751646954906; Fri, 04 Jul 2025 09:35:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHAk0+ghccXNshN8u7TNeu4h3k6+oaETuS8xhYM1wr/ZQ6arRzNkAkM/WufO8ztsBL4jDREcw== X-Received: by 2002:a05:620a:4081:b0:7ca:efed:8644 with SMTP id af79cd13be357-7d5ddaa7c92mr437649185a.5.1751646954343; Fri, 04 Jul 2025 09:35:54 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556383d33f3sm298321e87.68.2025.07.04.09.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 09:35:53 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 04 Jul 2025 19:35:29 +0300 Subject: [PATCH v2 17/28] interconnect: qcom: sdx55: convert to dynamic IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-rework-icc-v2-17-875fac996ef5@oss.qualcomm.com> References: <20250704-rework-icc-v2-0-875fac996ef5@oss.qualcomm.com> In-Reply-To: <20250704-rework-icc-v2-0-875fac996ef5@oss.qualcomm.com> To: Georgi Djakov , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=25964; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=bBbPgWexkDpRCqTXwnbgm6YFg8/jSw7JM3CzIo4s1w8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoaALH7ERgAaDSQu9VkVIkv7Rl2ufRw+cdHMgl/ q+bxBHFzZyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaGgCxwAKCRCLPIo+Aiko 1ai+B/0X2tuFHM786Y3RSMDv9VsRJPMYJSvM0sKnCeaZZOOvpoG/SdDqUHLCUhLoHxqNtCv+eHs 0ckP4bqcUlDRYThZM+yXV65iEb1x+E93CreB6Bh/SNK2L60NN0T09eJogPGrHUHbZEo0Ve+0GcO +dpDe+SZ9e5NaMBZD1Owa+loiZMIWdwX/twdOqrvooWRCnRPdK/HUEUCEy8Nv6bfF3Ui7w6auvB iXZqtVja4nnZ1pfcOQBUkXE/GdphK1sXhHpmvx4l7Aiqwkhi+tYBigbxQvcpm9OcFnfj0J3UmS4 BVbsbXvCymFdm4e5xMnd4qMdbS+t9X191O4k/pUDTwbkgiWD X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA0MDEyNiBTYWx0ZWRfX7CnfvYCDKNYw 42YmwH65x20ogqvveXKrDZeOp8d3ki0/+elDqKOWGBczA9PiWklnGobhvjv6pxgPud34ZxPolQS gpy2a6AF/hga/mhfmQjxx3IQ763W5mTrBPkFcnqDQhT1TrAPtQD085zT82b/M5YFcL3V7m5SAMu NFVMfhB3i5KKVakeGvNsulgd4GYs46JfXqIYuL49F9kzKCPy5es/0dl/98fMkxo/NuE9qNbO6cT o6aG/v5uvXW01zXm+B7IWzaGXN8P/YIqDiAr0R8nq/UGNKaGcE8IQfEMOKt/VaSbF2GeezwczuO naKQjOtTtktSvttAiQVx7oi56C8jsf45fyEScbUGOuXKJC27NKxLOU4NjgZuA09gbnbpbDrW9W3 JBTRU85qVNa7rAYa+wg87JOqmq0KyPeLxkCLhLj4E6rvCQemXqXeJvp/WtOJfPtjMcoZ7MmX X-Proofpoint-GUID: FrfXaYXQVZ0nsIs9bQd87cDEJEqw-tjI X-Authority-Analysis: v=2.4 cv=UPrdHDfy c=1 sm=1 tr=0 ts=686802ec cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=lxKA6TRo1hT2z37wmrwA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: FrfXaYXQVZ0nsIs9bQd87cDEJEqw-tjI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_06,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 malwarescore=0 mlxscore=0 phishscore=0 mlxlogscore=975 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507040126 Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdx55.c | 554 +++++++++++++++++++---------------= ---- drivers/interconnect/qcom/sdx55.h | 70 ----- 2 files changed, 275 insertions(+), 349 deletions(-) diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/= sdx55.c index af273e39eef3e90519635d1c310dc108a9f8b708..5d85c1e6ec58d3949b30c143440= bb6dd0779a605 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -17,630 +17,623 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdx55.h" + +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node xm_apps_rdwr; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_blsp1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qhm_spmi_fetcher1; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_ipa; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_memnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node xm_emac; +static struct qcom_icc_node xm_ipa2pcie_slv; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_blsp1; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_ecc_cfg; +static struct qcom_icc_node qhs_emac_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_parf; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spmi_fetcher; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_aggre_noc; +static struct qcom_icc_node qns_snoc_memnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SDX55_MASTER_LLCC, .channels =3D 4, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi, NULL }, }; =20 static struct qcom_icc_node acm_tcu =3D { .name =3D "acm_tcu", - .id =3D SDX55_MASTER_TCU_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 3, - .links =3D { SDX55_SLAVE_LLCC, - SDX55_SLAVE_MEM_NOC_SNOC, - SDX55_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie, NULL }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SDX55_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc, NULL }, }; =20 static struct qcom_icc_node xm_apps_rdwr =3D { .name =3D "xm_apps_rdwr", - .id =3D SDX55_MASTER_AMPSS_M0, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 3, - .links =3D { SDX55_SLAVE_LLCC, - SDX55_SLAVE_MEM_NOC_SNOC, - SDX55_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes =3D { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie, NULL }, }; =20 static struct qcom_icc_node qhm_audio =3D { .name =3D "qhm_audio", - .id =3D SDX55_MASTER_AUDIO, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc, NULL }, }; =20 static struct qcom_icc_node qhm_blsp1 =3D { .name =3D "qhm_blsp1", - .id =3D SDX55_MASTER_BLSP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc, NULL }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SDX55_MASTER_QDSS_BAM, - .channels =3D 1, - .buswidth =3D 4, - .num_links =3D 28, - .links =3D { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg, NULL }, }; =20 static struct qcom_icc_node qhm_qpic =3D { .name =3D "qhm_qpic", - .id =3D SDX55_MASTER_QPIC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 5, - .links =3D { SDX55_SLAVE_AOSS, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP, - SDX55_SLAVE_AUDIO - }, + .link_nodes =3D { &qhs_aoss, + &qhs_ipa, + &qns_aggre_noc, + &qhs_aop, + &qhs_audio, NULL }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SDX55_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_spmi_fetcher1 =3D { .name =3D "qhm_spmi_fetcher1", - .id =3D SDX55_MASTER_SPMI_FETCHER, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 3, - .links =3D { SDX55_SLAVE_AOSS, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP - }, + .link_nodes =3D { &qhs_aoss, + &qns_aggre_noc, + &qhs_aop, NULL }, }; =20 static struct qcom_icc_node qnm_aggre_noc =3D { .name =3D "qnm_aggre_noc", - .id =3D SDX55_MASTER_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 30, - .links =3D { SDX55_SLAVE_PCIE_0, - SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_USB3, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_APPSS, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &xs_pcie, + &qhs_snoc_cfg, + &qhs_sdc1, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_usb3, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_apss, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg, NULL }, }; =20 static struct qcom_icc_node qnm_ipa =3D { .name =3D "qnm_ipa", - .id =3D SDX55_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 27, - .links =3D { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_aoss, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_tlmm, + &qhs_prng, + &qhs_crypto0_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg, NULL }, }; =20 static struct qcom_icc_node qnm_memnoc =3D { .name =3D "qnm_memnoc", - .id =3D SDX55_MASTER_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 29, - .links =3D { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_APPSS, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_apss, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg, NULL }, }; =20 static struct qcom_icc_node qnm_memnoc_pcie =3D { .name =3D "qnm_memnoc_pcie", - .id =3D SDX55_MASTER_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie, NULL }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SDX55_MASTER_CRYPTO_CORE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 3, - .links =3D { SDX55_SLAVE_AOSS, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP - }, + .link_nodes =3D { &qhs_aoss, + &qns_aggre_noc, + &qhs_aop, NULL }, }; =20 static struct qcom_icc_node xm_emac =3D { .name =3D "xm_emac", - .id =3D SDX55_MASTER_EMAC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc, NULL }, }; =20 static struct qcom_icc_node xm_ipa2pcie_slv =3D { .name =3D "xm_ipa2pcie_slv", - .id =3D SDX55_MASTER_IPA_PCIE, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie, NULL }, }; =20 static struct qcom_icc_node xm_pcie =3D { .name =3D "xm_pcie", - .id =3D SDX55_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc, NULL }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SDX55_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 28, - .links =3D { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes =3D { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_aoss, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg, NULL }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D SDX55_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 5, - .links =3D { SDX55_SLAVE_AOSS, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP, - SDX55_SLAVE_AUDIO - }, + .link_nodes =3D { &qhs_aoss, + &qhs_ipa, + &qns_aggre_noc, + &qhs_aop, + &qhs_audio, NULL }, }; =20 static struct qcom_icc_node xm_usb3 =3D { .name =3D "xm_usb3", - .id =3D SDX55_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes =3D { &qns_aggre_noc, NULL }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SDX55_SLAVE_EBI_CH0, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SDX55_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SDX55_SLAVE_EBI_CH0 }, + .link_nodes =3D { &ebi, NULL }, }; =20 static struct qcom_icc_node qns_memnoc_snoc =3D { .name =3D "qns_memnoc_snoc", - .id =3D SDX55_SLAVE_MEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_MASTER_MEM_NOC_SNOC }, + .link_nodes =3D { &qnm_memnoc, NULL }, }; =20 static struct qcom_icc_node qns_sys_pcie =3D { .name =3D "qns_sys_pcie", - .id =3D SDX55_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_MASTER_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_memnoc_pcie, NULL }, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SDX55_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SDX55_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SDX55_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_audio =3D { .name =3D "qhs_audio", - .id =3D SDX55_SLAVE_AUDIO, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_blsp1 =3D { .name =3D "qhs_blsp1", - .id =3D SDX55_SLAVE_BLSP_1, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SDX55_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SDX55_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SDX55_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ecc_cfg =3D { .name =3D "qhs_ecc_cfg", - .id =3D SDX55_SLAVE_ECC_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_emac_cfg =3D { .name =3D "qhs_emac_cfg", - .id =3D SDX55_SLAVE_EMAC_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SDX55_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SDX55_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SDX55_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pcie_parf =3D { .name =3D "qhs_pcie_parf", - .id =3D SDX55_SLAVE_PCIE_PARF, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SDX55_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SDX55_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SDX55_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qpic =3D { .name =3D "qhs_qpic", - .id =3D SDX55_SLAVE_QPIC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D SDX55_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SDX55_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SDX55_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_spmi_fetcher =3D { .name =3D "qhs_spmi_fetcher", - .id =3D SDX55_SLAVE_SPMI_FETCHER, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_spmi_vgi_coex =3D { .name =3D "qhs_spmi_vgi_coex", - .id =3D SDX55_SLAVE_SPMI_VGI_COEX, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SDX55_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tlmm =3D { .name =3D "qhs_tlmm", - .id =3D SDX55_SLAVE_TLMM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D SDX55_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_usb3_phy =3D { .name =3D "qhs_usb3_phy", - .id =3D SDX55_SLAVE_USB3_PHY_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_aggre_noc =3D { .name =3D "qns_aggre_noc", - .id =3D SDX55_SLAVE_ANOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_MASTER_ANOC_SNOC }, + .link_nodes =3D { &qnm_aggre_noc, NULL }, }; =20 static struct qcom_icc_node qns_snoc_memnoc =3D { .name =3D "qns_snoc_memnoc", - .id =3D SDX55_SLAVE_SNOC_MEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SDX55_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc, NULL }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SDX55_SLAVE_OCIMEM, .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SDX55_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_pcie =3D { .name =3D "xs_pcie", - .id =3D SDX55_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SDX55_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SDX55_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_bcm bcm_mc0 =3D { @@ -773,6 +766,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx55_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -795,6 +789,7 @@ static struct qcom_icc_node * const mem_noc_nodes[] =3D= { }; =20 static const struct qcom_icc_desc sdx55_mem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mem_noc_nodes, .num_nodes =3D ARRAY_SIZE(mem_noc_nodes), .bcms =3D mem_noc_bcms, @@ -874,6 +869,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sdx55_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sdx55.h b/drivers/interconnect/qcom/= sdx55.h deleted file mode 100644 index 46cbabec8aa1f95be840e50618efd04bcbf89f10..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sdx55.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021, Linaro Ltd. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H - -/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SDX55_MASTER_LLCC 1 -#define SDX55_MASTER_TCU_0 2 -#define SDX55_MASTER_SNOC_GC_MEM_NOC 3 -#define SDX55_MASTER_AMPSS_M0 4 -#define SDX55_MASTER_AUDIO 5 -#define SDX55_MASTER_BLSP_1 6 -#define SDX55_MASTER_QDSS_BAM 7 -#define SDX55_MASTER_QPIC 8 -#define SDX55_MASTER_SNOC_CFG 9 -#define SDX55_MASTER_SPMI_FETCHER 10 -#define SDX55_MASTER_ANOC_SNOC 11 -#define SDX55_MASTER_IPA 12 -#define SDX55_MASTER_MEM_NOC_SNOC 13 -#define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14 -#define SDX55_MASTER_CRYPTO_CORE_0 15 -#define SDX55_MASTER_EMAC 16 -#define SDX55_MASTER_IPA_PCIE 17 -#define SDX55_MASTER_PCIE 18 -#define SDX55_MASTER_QDSS_ETR 19 -#define SDX55_MASTER_SDCC_1 20 -#define SDX55_MASTER_USB3 21 -/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SDX55_SLAVE_EBI_CH0 23 -#define SDX55_SLAVE_LLCC 24 -#define SDX55_SLAVE_MEM_NOC_SNOC 25 -#define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26 -#define SDX55_SLAVE_ANOC_SNOC 27 -#define SDX55_SLAVE_SNOC_CFG 28 -#define SDX55_SLAVE_EMAC_CFG 29 -#define SDX55_SLAVE_USB3 30 -#define SDX55_SLAVE_TLMM 31 -#define SDX55_SLAVE_SPMI_FETCHER 32 -#define SDX55_SLAVE_QDSS_CFG 33 -#define SDX55_SLAVE_PDM 34 -#define SDX55_SLAVE_SNOC_MEM_NOC_GC 35 -#define SDX55_SLAVE_TCSR 36 -#define SDX55_SLAVE_CNOC_DDRSS 37 -#define SDX55_SLAVE_SPMI_VGI_COEX 38 -#define SDX55_SLAVE_QPIC 39 -#define SDX55_SLAVE_OCIMEM 40 -#define SDX55_SLAVE_IPA_CFG 41 -#define SDX55_SLAVE_USB3_PHY_CFG 42 -#define SDX55_SLAVE_AOP 43 -#define SDX55_SLAVE_BLSP_1 44 -#define SDX55_SLAVE_SDCC_1 45 -#define SDX55_SLAVE_CNOC_MSS 46 -#define SDX55_SLAVE_PCIE_PARF 47 -#define SDX55_SLAVE_ECC_CFG 48 -#define SDX55_SLAVE_AUDIO 49 -#define SDX55_SLAVE_AOSS 51 -#define SDX55_SLAVE_PRNG 52 -#define SDX55_SLAVE_CRYPTO_0_CFG 53 -#define SDX55_SLAVE_TCU 54 -#define SDX55_SLAVE_CLK_CTL 55 -#define SDX55_SLAVE_IMEM_CFG 56 -#define SDX55_SLAVE_SERVICE_SNOC 57 -#define SDX55_SLAVE_PCIE_0 58 -#define SDX55_SLAVE_QDSS_STM 59 -#define SDX55_SLAVE_APPSS 60 - -#endif --=20 2.39.5