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This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sc7180.c | 829 +++++++++++++++++++--------------= ---- drivers/interconnect/qcom/sc7180.h | 149 ------- 2 files changed, 416 insertions(+), 562 deletions(-) diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom= /sc7180.c index 6397d693918b41e35684b180fd6b8f5cb359386e..2d9099e909bb9fbc9b82370e488= d014391324637 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -14,1226 +14,1217 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc7180.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup_0; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_1; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node qhm_usb3; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qxm_npu_dsp; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps0; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node qhm_npu_cfg; +static struct qcom_icc_node qup_core_master_1; +static struct qcom_icc_node qup_core_master_2; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_rt_throttle_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_npu_dma_throttle_cfg; +static struct qcom_icc_node qhs_npu_dsp_throttle_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_1; +static struct qcom_icc_node qhs_tlmm_2; +static struct qcom_icc_node qhs_tlmm_3; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qup_core_slave_1; +static struct qcom_icc_node qup_core_slave_2; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D SC7180_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_SERVICE_A1NOC }, + .link_nodes =3D { &srvc_aggre1_noc, NULL }, }; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D SC7180_MASTER_QSPI, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qup_0 =3D { .name =3D "qhm_qup_0", - .id =3D SC7180_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D SC7180_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_emmc =3D { .name =3D "xm_emmc", - .id =3D SC7180_MASTER_EMMC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D SC7180_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_a2noc_cfg =3D { .name =3D "qhm_a2noc_cfg", - .id =3D SC7180_MASTER_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc, NULL }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D SC7180_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qup_1 =3D { .name =3D "qhm_qup_1", - .id =3D SC7180_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D SC7180_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D SC7180_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D SC7180_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_usb3 =3D { .name =3D "qhm_usb3", - .id =3D SC7180_MASTER_USB3, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D SC7180_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D SC7180_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D SC7180_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp, NULL }, }; =20 static struct qcom_icc_node qnm_npu =3D { .name =3D "qnm_npu", - .id =3D SC7180_MASTER_NPU, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_CDSP_GEM_NOC }, + .link_nodes =3D { &qns_cdsp_gemnoc, NULL }, }; =20 static struct qcom_icc_node qxm_npu_dsp =3D { .name =3D "qxm_npu_dsp", - .id =3D SC7180_MASTER_NPU_PROC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_CDSP_GEM_NOC }, + .link_nodes =3D { &qns_cdsp_gemnoc, NULL }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D SC7180_MASTER_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 51, - .links =3D { SC7180_SLAVE_A1NOC_CFG, - SC7180_SLAVE_A2NOC_CFG, - SC7180_SLAVE_AHB2PHY_SOUTH, - SC7180_SLAVE_AHB2PHY_CENTER, - SC7180_SLAVE_AOP, - SC7180_SLAVE_AOSS, - SC7180_SLAVE_BOOT_ROM, - SC7180_SLAVE_CAMERA_CFG, - SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, - SC7180_SLAVE_CLK_CTL, - SC7180_SLAVE_RBCPR_CX_CFG, - SC7180_SLAVE_RBCPR_MX_CFG, - SC7180_SLAVE_CRYPTO_0_CFG, - SC7180_SLAVE_DCC_CFG, - SC7180_SLAVE_CNOC_DDRSS, - SC7180_SLAVE_DISPLAY_CFG, - SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SC7180_SLAVE_DISPLAY_THROTTLE_CFG, - SC7180_SLAVE_EMMC_CFG, - SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, - SC7180_SLAVE_IMEM_CFG, - SC7180_SLAVE_IPA_CFG, - SC7180_SLAVE_CNOC_MNOC_CFG, - SC7180_SLAVE_CNOC_MSS, - SC7180_SLAVE_NPU_CFG, - SC7180_SLAVE_NPU_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_PROC_BWMON_CFG, - SC7180_SLAVE_PDM, - SC7180_SLAVE_PIMEM_CFG, - SC7180_SLAVE_PRNG, - SC7180_SLAVE_QDSS_CFG, - SC7180_SLAVE_QM_CFG, - SC7180_SLAVE_QM_MPU_CFG, - SC7180_SLAVE_QSPI_0, - SC7180_SLAVE_QUP_0, - SC7180_SLAVE_QUP_1, - SC7180_SLAVE_SDCC_2, - SC7180_SLAVE_SECURITY, - SC7180_SLAVE_SNOC_CFG, - SC7180_SLAVE_TCSR, - SC7180_SLAVE_TLMM_WEST, - SC7180_SLAVE_TLMM_NORTH, - SC7180_SLAVE_TLMM_SOUTH, - SC7180_SLAVE_UFS_MEM_CFG, - SC7180_SLAVE_USB3, - SC7180_SLAVE_VENUS_CFG, - SC7180_SLAVE_VENUS_THROTTLE_CFG, - SC7180_SLAVE_VSENSE_CTRL_CFG, - SC7180_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy2, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_sdc2, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc, NULL }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D SC7180_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 51, - .links =3D { SC7180_SLAVE_A1NOC_CFG, - SC7180_SLAVE_A2NOC_CFG, - SC7180_SLAVE_AHB2PHY_SOUTH, - SC7180_SLAVE_AHB2PHY_CENTER, - SC7180_SLAVE_AOP, - SC7180_SLAVE_AOSS, - SC7180_SLAVE_BOOT_ROM, - SC7180_SLAVE_CAMERA_CFG, - SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, - SC7180_SLAVE_CLK_CTL, - SC7180_SLAVE_RBCPR_CX_CFG, - SC7180_SLAVE_RBCPR_MX_CFG, - SC7180_SLAVE_CRYPTO_0_CFG, - SC7180_SLAVE_DCC_CFG, - SC7180_SLAVE_CNOC_DDRSS, - SC7180_SLAVE_DISPLAY_CFG, - SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SC7180_SLAVE_DISPLAY_THROTTLE_CFG, - SC7180_SLAVE_EMMC_CFG, - SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, - SC7180_SLAVE_IMEM_CFG, - SC7180_SLAVE_IPA_CFG, - SC7180_SLAVE_CNOC_MNOC_CFG, - SC7180_SLAVE_CNOC_MSS, - SC7180_SLAVE_NPU_CFG, - SC7180_SLAVE_NPU_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_PROC_BWMON_CFG, - SC7180_SLAVE_PDM, - SC7180_SLAVE_PIMEM_CFG, - SC7180_SLAVE_PRNG, - SC7180_SLAVE_QDSS_CFG, - SC7180_SLAVE_QM_CFG, - SC7180_SLAVE_QM_MPU_CFG, - SC7180_SLAVE_QSPI_0, - SC7180_SLAVE_QUP_0, - SC7180_SLAVE_QUP_1, - SC7180_SLAVE_SDCC_2, - SC7180_SLAVE_SECURITY, - SC7180_SLAVE_SNOC_CFG, - SC7180_SLAVE_TCSR, - SC7180_SLAVE_TLMM_WEST, - SC7180_SLAVE_TLMM_NORTH, - SC7180_SLAVE_TLMM_SOUTH, - SC7180_SLAVE_UFS_MEM_CFG, - SC7180_SLAVE_USB3, - SC7180_SLAVE_VENUS_CFG, - SC7180_SLAVE_VENUS_THROTTLE_CFG, - SC7180_SLAVE_VSENSE_CTRL_CFG, - SC7180_SLAVE_SERVICE_CNOC - }, + .link_nodes =3D { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy2, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_sdc2, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc, NULL }, }; =20 static struct qcom_icc_node qhm_cnoc_dc_noc =3D { .name =3D "qhm_cnoc_dc_noc", - .id =3D SC7180_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_CFG, - SC7180_SLAVE_LLCC_CFG - }, + .link_nodes =3D { &qhs_gemnoc, + &qhs_llcc, NULL }, }; =20 static struct qcom_icc_node acm_apps0 =3D { .name =3D "acm_apps0", - .id =3D SC7180_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc, NULL }, }; =20 static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", - .id =3D SC7180_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D SC7180_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 2, - .links =3D { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, - SC7180_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes =3D { &qhs_mdsp_ms_mpu_cfg, + &srvc_gemnoc, NULL }, }; =20 static struct qcom_icc_node qnm_cmpnoc =3D { .name =3D "qnm_cmpnoc", - .id =3D SC7180_MASTER_COMPUTE_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D SC7180_MASTER_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D SC7180_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D SC7180_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D SC7180_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qxm_gpu =3D { .name =3D "qxm_gpu", - .id =3D SC7180_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes =3D { &qns_gem_noc_snoc, + &qns_llcc, NULL }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D SC7180_MASTER_LLCC, .channels =3D 2, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_EBI1 }, + .link_nodes =3D { &ebi, NULL }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D SC7180_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D SC7180_MASTER_CAMNOC_HF0, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D SC7180_MASTER_CAMNOC_HF1, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D SC7180_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D SC7180_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D SC7180_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D SC7180_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D SC7180_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, }; =20 static struct qcom_icc_node amm_npu_sys =3D { .name =3D "amm_npu_sys", - .id =3D SC7180_MASTER_NPU_SYS, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes =3D { &qns_npu_sys, NULL }, }; =20 static struct qcom_icc_node qhm_npu_cfg =3D { .name =3D "qhm_npu_cfg", - .id =3D SC7180_MASTER_NPU_NOC_CFG, - .channels =3D 1, - .buswidth =3D 4, - .num_links =3D 8, - .links =3D { SC7180_SLAVE_NPU_CAL_DP0, - SC7180_SLAVE_NPU_CP, - SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_DPM, - SC7180_SLAVE_ISENSE_CFG, - SC7180_SLAVE_NPU_LLM_CFG, - SC7180_SLAVE_NPU_TCM, - SC7180_SLAVE_SERVICE_NPU_NOC - }, + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qhs_cal_dp0, + &qhs_cp, + &qhs_dma_bwmon, + &qhs_dpm, + &qhs_isense, + &qhs_llm, + &qhs_tcm, + &srvc_noc, NULL }, }; =20 static struct qcom_icc_node qup_core_master_1 =3D { .name =3D "qup_core_master_1", - .id =3D SC7180_MASTER_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_QUP_CORE_0 }, + .link_nodes =3D { &qup_core_slave_1, NULL }, }; =20 static struct qcom_icc_node qup_core_master_2 =3D { .name =3D "qup_core_master_2", - .id =3D SC7180_MASTER_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_QUP_CORE_1 }, + .link_nodes =3D { &qup_core_slave_2, NULL }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D SC7180_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc, NULL }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D SC7180_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 6, - .links =3D { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_SNOC_GEM_NOC_SF, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_gemnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, NULL }, }; =20 static struct qcom_icc_node qnm_aggre2_noc =3D { .name =3D "qnm_aggre2_noc", - .id =3D SC7180_MASTER_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 7, - .links =3D { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_SNOC_GEM_NOC_SF, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM, - SC7180_SLAVE_TCU - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qns_gemnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg, NULL }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D SC7180_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 6, - .links =3D { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM, - SC7180_SLAVE_TCU - }, + .link_nodes =3D { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg, NULL }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D SC7180_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { SC7180_SLAVE_SNOC_GEM_NOC_GC, - SC7180_SLAVE_IMEM - }, + .link_nodes =3D { &qns_gemnoc_gc, + &qxs_imem, NULL }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D SC7180_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC7180_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc, NULL }, }; =20 static struct qcom_icc_node srvc_aggre1_noc =3D { .name =3D "srvc_aggre1_noc", - .id =3D SC7180_SLAVE_SERVICE_A1NOC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_a2noc_snoc =3D { .name =3D "qns_a2noc_snoc", - .id =3D SC7180_SLAVE_A2NOC_SNOC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC7180_MASTER_A2NOC_SNOC }, + .link_nodes =3D { &qnm_aggre2_noc, NULL }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D SC7180_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D SC7180_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_cdsp_gemnoc =3D { .name =3D "qns_cdsp_gemnoc", - .id =3D SC7180_SLAVE_CDSP_GEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_MASTER_COMPUTE_NOC }, + .link_nodes =3D { &qnm_cmpnoc, NULL }, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D SC7180_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_a2_noc_cfg =3D { .name =3D "qhs_a2_noc_cfg", - .id =3D SC7180_SLAVE_A2NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_MASTER_A2NOC_CFG }, + .link_nodes =3D { &qhm_a2noc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_ahb2phy0 =3D { .name =3D "qhs_ahb2phy0", - .id =3D SC7180_SLAVE_AHB2PHY_SOUTH, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ahb2phy2 =3D { .name =3D "qhs_ahb2phy2", - .id =3D SC7180_SLAVE_AHB2PHY_CENTER, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D SC7180_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D SC7180_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_boot_rom =3D { .name =3D "qhs_boot_rom", - .id =3D SC7180_SLAVE_BOOT_ROM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D SC7180_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg =3D { .name =3D "qhs_camera_nrt_throttle_cfg", - .id =3D SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { .name =3D "qhs_camera_rt_throttle_cfg", - .id =3D SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D SC7180_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D SC7180_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D SC7180_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D SC7180_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_dcc_cfg =3D { .name =3D "qhs_dcc_cfg", - .id =3D SC7180_SLAVE_DCC_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D SC7180_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc_dc_noc, NULL }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D SC7180_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_display_rt_throttle_cfg =3D { .name =3D "qhs_display_rt_throttle_cfg", - .id =3D SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_display_throttle_cfg =3D { .name =3D "qhs_display_throttle_cfg", - .id =3D SC7180_SLAVE_DISPLAY_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_emmc_cfg =3D { .name =3D "qhs_emmc_cfg", - .id =3D SC7180_SLAVE_EMMC_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D SC7180_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D SC7180_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D SC7180_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D SC7180_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D SC7180_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_mss_cfg =3D { .name =3D "qhs_mss_cfg", - .id =3D SC7180_SLAVE_CNOC_MSS, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_npu_cfg =3D { .name =3D "qhs_npu_cfg", - .id =3D SC7180_SLAVE_NPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_MASTER_NPU_NOC_CFG }, + .link_nodes =3D { &qhm_npu_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_npu_dma_throttle_cfg =3D { .name =3D "qhs_npu_dma_throttle_cfg", - .id =3D SC7180_SLAVE_NPU_DMA_BWMON_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_npu_dsp_throttle_cfg =3D { .name =3D "qhs_npu_dsp_throttle_cfg", - .id =3D SC7180_SLAVE_NPU_PROC_BWMON_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pdm =3D { .name =3D "qhs_pdm", - .id =3D SC7180_SLAVE_PDM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D SC7180_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D SC7180_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D SC7180_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qm_cfg =3D { .name =3D "qhs_qm_cfg", - .id =3D SC7180_SLAVE_QM_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qm_mpu_cfg =3D { .name =3D "qhs_qm_mpu_cfg", - .id =3D SC7180_SLAVE_QM_MPU_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D SC7180_SLAVE_QSPI_0, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D SC7180_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D SC7180_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D SC7180_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_security =3D { .name =3D "qhs_security", - .id =3D SC7180_SLAVE_SECURITY, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D SC7180_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D SC7180_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tlmm_1 =3D { .name =3D "qhs_tlmm_1", - .id =3D SC7180_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tlmm_2 =3D { .name =3D "qhs_tlmm_2", - .id =3D SC7180_SLAVE_TLMM_NORTH, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tlmm_3 =3D { .name =3D "qhs_tlmm_3", - .id =3D SC7180_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D SC7180_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D SC7180_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D SC7180_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_venus_throttle_cfg =3D { .name =3D "qhs_venus_throttle_cfg", - .id =3D SC7180_SLAVE_VENUS_THROTTLE_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D SC7180_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D SC7180_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gemnoc =3D { .name =3D "qhs_gemnoc", - .id =3D SC7180_SLAVE_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { SC7180_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D SC7180_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D SC7180_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc, NULL }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D SC7180_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC7180_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc, NULL }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D SC7180_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D SC7180_SLAVE_EBI1, .channels =3D 2, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D SC7180_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf, NULL }, }; =20 static struct qcom_icc_node qns_mem_noc_sf =3D { .name =3D "qns_mem_noc_sf", - .id =3D SC7180_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { SC7180_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf, NULL }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D SC7180_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cal_dp0 =3D { .name =3D "qhs_cal_dp0", - .id =3D SC7180_SLAVE_NPU_CAL_DP0, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cp =3D { .name =3D "qhs_cp", - .id =3D SC7180_SLAVE_NPU_CP, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_dma_bwmon =3D { .name =3D "qhs_dma_bwmon", - .id =3D SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_dpm =3D { .name =3D "qhs_dpm", - .id =3D SC7180_SLAVE_NPU_DPM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_isense =3D { .name =3D "qhs_isense", - .id =3D SC7180_SLAVE_ISENSE_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_llm =3D { .name =3D "qhs_llm", - .id =3D SC7180_SLAVE_NPU_LLM_CFG, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tcm =3D { .name =3D "qhs_tcm", - .id =3D SC7180_SLAVE_NPU_TCM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_npu_sys =3D { .name =3D "qns_npu_sys", - .id =3D SC7180_SLAVE_NPU_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_noc =3D { .name =3D "srvc_noc", - .id =3D SC7180_SLAVE_SERVICE_NPU_NOC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qup_core_slave_1 =3D { .name =3D "qup_core_slave_1", - .id =3D SC7180_SLAVE_QUP_CORE_0, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qup_core_slave_2 =3D { .name =3D "qup_core_slave_2", - .id =3D SC7180_SLAVE_QUP_CORE_1, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D SC7180_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D SC7180_SLAVE_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_MASTER_SNOC_CNOC }, + .link_nodes =3D { &qnm_snoc, NULL }, }; =20 static struct qcom_icc_node qns_gemnoc_gc =3D { .name =3D "qns_gemnoc_gc", - .id =3D SC7180_SLAVE_SNOC_GEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { SC7180_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc, NULL }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D SC7180_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { SC7180_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf, NULL }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D SC7180_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D SC7180_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D SC7180_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D SC7180_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D SC7180_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1458,6 +1449,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1481,6 +1473,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_aggre2_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1499,6 +1492,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sc7180_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1518,6 +1512,7 @@ static struct qcom_icc_node * const compute_noc_nodes= [] =3D { }; =20 static const struct qcom_icc_desc sc7180_compute_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D compute_noc_nodes, .num_nodes =3D ARRAY_SIZE(compute_noc_nodes), .bcms =3D compute_noc_bcms, @@ -1586,6 +1581,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1599,6 +1595,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1627,6 +1624,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1644,6 +1642,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1671,6 +1670,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1692,6 +1692,7 @@ static struct qcom_icc_node * const npu_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_npu_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D npu_noc_nodes, .num_nodes =3D ARRAY_SIZE(npu_noc_nodes), }; @@ -1708,6 +1709,7 @@ static struct qcom_icc_node * const qup_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sc7180_qup_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D qup_virt_nodes, .num_nodes =3D ARRAY_SIZE(qup_virt_nodes), .bcms =3D qup_virt_bcms, @@ -1743,6 +1745,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sc7180_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom= /sc7180.h deleted file mode 100644 index 2b718922c10903fbb4f127e9b1d15f99f385c5c5..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/sc7180.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC7180 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7180_H -#define __DRIVERS_INTERCONNECT_QCOM_SC7180_H - -#define SC7180_MASTER_APPSS_PROC 0 -#define SC7180_MASTER_SYS_TCU 1 -#define SC7180_MASTER_NPU_SYS 2 -/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SC7180_MASTER_LLCC 4 -#define SC7180_MASTER_A1NOC_CFG 5 -#define SC7180_MASTER_A2NOC_CFG 6 -#define SC7180_MASTER_CNOC_DC_NOC 7 -#define SC7180_MASTER_GEM_NOC_CFG 8 -#define SC7180_MASTER_CNOC_MNOC_CFG 9 -#define SC7180_MASTER_NPU_NOC_CFG 10 -#define SC7180_MASTER_QDSS_BAM 11 -#define SC7180_MASTER_QSPI 12 -#define SC7180_MASTER_QUP_0 13 -#define SC7180_MASTER_QUP_1 14 -#define SC7180_MASTER_SNOC_CFG 15 -#define SC7180_MASTER_A1NOC_SNOC 16 -#define SC7180_MASTER_A2NOC_SNOC 17 -#define SC7180_MASTER_COMPUTE_NOC 18 -#define SC7180_MASTER_GEM_NOC_SNOC 19 -#define SC7180_MASTER_MNOC_HF_MEM_NOC 20 -#define SC7180_MASTER_MNOC_SF_MEM_NOC 21 -#define SC7180_MASTER_NPU 22 -#define SC7180_MASTER_SNOC_CNOC 23 -#define SC7180_MASTER_SNOC_GC_MEM_NOC 24 -#define SC7180_MASTER_SNOC_SF_MEM_NOC 25 -#define SC7180_MASTER_QUP_CORE_0 26 -#define SC7180_MASTER_QUP_CORE_1 27 -#define SC7180_MASTER_CAMNOC_HF0 28 -#define SC7180_MASTER_CAMNOC_HF1 29 -#define SC7180_MASTER_CAMNOC_HF0_UNCOMP 30 -#define SC7180_MASTER_CAMNOC_HF1_UNCOMP 31 -#define SC7180_MASTER_CAMNOC_SF 32 -#define SC7180_MASTER_CAMNOC_SF_UNCOMP 33 -#define SC7180_MASTER_CRYPTO 34 -#define SC7180_MASTER_GFX3D 35 -#define SC7180_MASTER_IPA 36 -#define SC7180_MASTER_MDP0 37 -#define SC7180_MASTER_NPU_PROC 38 -#define SC7180_MASTER_PIMEM 39 -#define SC7180_MASTER_ROTATOR 40 -#define SC7180_MASTER_VIDEO_P0 41 -#define SC7180_MASTER_VIDEO_PROC 42 -#define SC7180_MASTER_QDSS_DAP 43 -#define SC7180_MASTER_QDSS_ETR 44 -#define SC7180_MASTER_SDCC_2 45 -#define SC7180_MASTER_UFS_MEM 46 -#define SC7180_MASTER_USB3 47 -#define SC7180_MASTER_EMMC 48 -#define SC7180_SLAVE_EBI1 49 -/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC7180_SLAVE_A1NOC_CFG 51 -#define SC7180_SLAVE_A2NOC_CFG 52 -#define SC7180_SLAVE_AHB2PHY_SOUTH 53 -#define SC7180_SLAVE_AHB2PHY_CENTER 54 -#define SC7180_SLAVE_AOP 55 -#define SC7180_SLAVE_AOSS 56 -#define SC7180_SLAVE_APPSS 57 -#define SC7180_SLAVE_BOOT_ROM 58 -#define SC7180_SLAVE_NPU_CAL_DP0 59 -#define SC7180_SLAVE_CAMERA_CFG 60 -#define SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG 61 -#define SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG 62 -#define SC7180_SLAVE_CLK_CTL 63 -#define SC7180_SLAVE_NPU_CP 64 -#define SC7180_SLAVE_RBCPR_CX_CFG 65 -#define SC7180_SLAVE_RBCPR_MX_CFG 66 -#define SC7180_SLAVE_CRYPTO_0_CFG 67 -#define SC7180_SLAVE_DCC_CFG 68 -#define SC7180_SLAVE_CNOC_DDRSS 69 -#define SC7180_SLAVE_DISPLAY_CFG 70 -#define SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG 71 -#define SC7180_SLAVE_DISPLAY_THROTTLE_CFG 72 -#define SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG 73 -#define SC7180_SLAVE_NPU_DPM 74 -#define SC7180_SLAVE_EMMC_CFG 75 -#define SC7180_SLAVE_GEM_NOC_CFG 76 -#define SC7180_SLAVE_GLM 77 -#define SC7180_SLAVE_GFX3D_CFG 78 -#define SC7180_SLAVE_IMEM_CFG 79 -#define SC7180_SLAVE_IPA_CFG 80 -#define SC7180_SLAVE_ISENSE_CFG 81 -#define SC7180_SLAVE_LLCC_CFG 82 -#define SC7180_SLAVE_NPU_LLM_CFG 83 -#define SC7180_SLAVE_MSS_PROC_MS_MPU_CFG 84 -#define SC7180_SLAVE_CNOC_MNOC_CFG 85 -#define SC7180_SLAVE_CNOC_MSS 86 -#define SC7180_SLAVE_NPU_CFG 87 -#define SC7180_SLAVE_NPU_DMA_BWMON_CFG 88 -#define SC7180_SLAVE_NPU_PROC_BWMON_CFG 89 -#define SC7180_SLAVE_PDM 90 -#define SC7180_SLAVE_PIMEM_CFG 91 -#define SC7180_SLAVE_PRNG 92 -#define SC7180_SLAVE_QDSS_CFG 93 -#define SC7180_SLAVE_QM_CFG 94 -#define SC7180_SLAVE_QM_MPU_CFG 95 -#define SC7180_SLAVE_QSPI_0 96 -#define SC7180_SLAVE_QUP_0 97 -#define SC7180_SLAVE_QUP_1 98 -#define SC7180_SLAVE_SDCC_2 99 -#define SC7180_SLAVE_SECURITY 100 -#define SC7180_SLAVE_SNOC_CFG 101 -#define SC7180_SLAVE_NPU_TCM 102 -#define SC7180_SLAVE_TCSR 103 -#define SC7180_SLAVE_TLMM_WEST 104 -#define SC7180_SLAVE_TLMM_NORTH 105 -#define SC7180_SLAVE_TLMM_SOUTH 106 -#define SC7180_SLAVE_UFS_MEM_CFG 107 -#define SC7180_SLAVE_USB3 108 -#define SC7180_SLAVE_VENUS_CFG 109 -#define SC7180_SLAVE_VENUS_THROTTLE_CFG 110 -#define SC7180_SLAVE_VSENSE_CTRL_CFG 111 -#define SC7180_SLAVE_A1NOC_SNOC 112 -#define SC7180_SLAVE_A2NOC_SNOC 113 -#define SC7180_SLAVE_CAMNOC_UNCOMP 114 -#define SC7180_SLAVE_CDSP_GEM_NOC 115 -#define SC7180_SLAVE_SNOC_CNOC 116 -#define SC7180_SLAVE_GEM_NOC_SNOC 117 -#define SC7180_SLAVE_SNOC_GEM_NOC_GC 118 -#define SC7180_SLAVE_SNOC_GEM_NOC_SF 119 -#define SC7180_SLAVE_LLCC 120 -#define SC7180_SLAVE_MNOC_HF_MEM_NOC 121 -#define SC7180_SLAVE_MNOC_SF_MEM_NOC 122 -#define SC7180_SLAVE_NPU_COMPUTE_NOC 123 -#define SC7180_SLAVE_QUP_CORE_0 124 -#define SC7180_SLAVE_QUP_CORE_1 125 -#define SC7180_SLAVE_IMEM 126 -#define SC7180_SLAVE_PIMEM 127 -#define SC7180_SLAVE_SERVICE_A1NOC 128 -#define SC7180_SLAVE_SERVICE_A2NOC 129 -#define SC7180_SLAVE_SERVICE_CNOC 130 -#define SC7180_SLAVE_SERVICE_GEM_NOC 131 -#define SC7180_SLAVE_SERVICE_MNOC 132 -#define SC7180_SLAVE_SERVICE_NPU_NOC 133 -#define SC7180_SLAVE_SERVICE_SNOC 134 -#define SC7180_SLAVE_QDSS_STM 135 -#define SC7180_SLAVE_TCU 136 - -#endif --=20 2.39.5