From nobody Wed Oct 8 00:08:37 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BC4C31552D for ; Fri, 4 Jul 2025 16:35:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751646951; cv=none; b=UGkFM/elO37A31an8ArptZn/beqxtFDYjYe0gFpb979OBgTvOZEmmcPUNAtBCPuP7KADE3ssfvHaEXi1G051ZMwpPGRJIsuP6o/6OFf0fMvuTTdOiqRaDGq29r28SC3pTi1mGAZkj1oTMoxYXB8VWCCfn+7KqgNFaTS6+fkT1KI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751646951; c=relaxed/simple; bh=3bf8TRzsZH6WoEUnaTMAiG8XwfFK5qsNPxMs1nulwQ8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ywz7SELw070nRzLx5JpXC/UGLaadSBENIrqCAiU6cxjU0bXtHs/3unXUUzJkX6OnFPGm0avLHbUXheF1PYPJqUHVIL1p5w6F5FuDXN12+Tm/Q3WthAD8mDZXScz6GiqDzWIqM/PjjYUCG3KOuShR5FrZ2RIEpm67tLwE2fuLnfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=gtOexsFN; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="gtOexsFN" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56498ox6011258 for ; Fri, 4 Jul 2025 16:35:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bx4Sdr8NiqaeaiHLFn6qxN13t+SoKih+XAmE1YMuj08=; b=gtOexsFNdBVEfo+n oBSHpXMvRDNU1EqgL0mEFXgkkmZ4Y/VKznhtQ+VvcaeCaaKwTrMxU3SqCfPvswpW JIIX1Xi3nhfcXOe21eniSvryZUXtpSWzxzhwSdBVrJL81gHWR45EI0gdalGQITBq 9NQIqPPAW4cIu4cWY9roVm9IYMR3KyaKcs1YRTwN7gPcP9TatZuPy7JSwkfa0i7S /hcOqyg6I8cYxqrMq/AGX0yahLKmm3YKvjOKAKzY+546iMG5kO+xoejvpBak5XlM AHVBgDXlPWa6G6pkDkBwUypwwy3fX9oarqVMcTklh0V24vssB4a38EPGqltXft6U iGEScg== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47j802c7m9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 04 Jul 2025 16:35:44 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-7c5e2872e57so165625185a.0 for ; Fri, 04 Jul 2025 09:35:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751646944; x=1752251744; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bx4Sdr8NiqaeaiHLFn6qxN13t+SoKih+XAmE1YMuj08=; b=eIkrTOvY4zvbNV0uqUODSpxSaQQTLQdeJREesAMQCNifdmwjClMHdKCFaOPVsMArtF ommLwEAsvioZ7JsNroDPOiQ/RYFRzut7vhChy4MwACcpconKdV/RM+5+iEdAJWfCObx+ lUPFYIGAo2+NAxsf4mcEZDzx1jeFrbNB/DsexHMRVE50JiYQvL1CMUhX3TjfsAns0kQD ic/PhiqToR7wzGWpNL03EVVsxijNyolmbtxNxlt/DcT2VQMFrIKPUypp5ErNgbjo83j+ YOv8IRZ0eD4lHn7H9Z/D76rHEZmCl/LO56A2RrEeX0KqIaowbaDG4R8EYJmqoYRrmq5V 4U/Q== X-Forwarded-Encrypted: i=1; AJvYcCU6X+rFce1DhOmB4e9kUC9XDXL9yVUp44odECa/BjmD5biw+ndmkXUEzkoWy0+RrIrHDoqBqRdEVHrH3wk=@vger.kernel.org X-Gm-Message-State: AOJu0YyJIAr4x/3Vi2cffN3EXlrhFJt3FR2mW666LL37JCZFLEdXID6q sCJLr7TvDoGspPXBefl5wZdHU9NZpCMsleLdryJY0eZff8oJci7/LLzzklYZKXJL8wex9xb2SSY Ogmc9hvc8gQR67c2AjxBvwUzr1CvDNZQUZvfjxNKLlFcLKYppY34QYwIp7KlrA0mGcNXS9vv6xW UL6Q== X-Gm-Gg: ASbGncs82gxclzdeRNwhPJjN6jPkpwn0wmDy4b9AZYvLgiJIIDeOD3Xq+nwKb9miT41 lnt/cobelvyEVvrZA1H7ii12+E2c7IJKdFa55inRMG/nRGUQXeUQkEtqNg3ArC7/FovQTGfhkaL /SeqHLABleJpFKgg7RbUPFiiB+oxndvNcAMLoBJbwLWpmwcyO65loZlZdHrcQ3WEcnYceLLQrSn wcxtQKNWIRVwDEsfLPNlhsBdj+BXyhVhS85JLiFxL5fVsH0OjSRyNHKUFGqeHSzGyEX8PuNwA+a wQiyCaLiQyknO+58ToxQMqV5l2xAq/kh9j68hrfBegEyyj4BekVUpwzJ5yXGAwY05xnR3FE2p4u VIblK+2R7w7V1G51DgumPgEtqwgrtYGgWQTM= X-Received: by 2002:a05:620a:1aa1:b0:7d0:69ff:385a with SMTP id af79cd13be357-7d5df181d6cmr319511485a.58.1751646943190; Fri, 04 Jul 2025 09:35:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEOjqPhFCFe3GMUC4PfZxRIbxNrchqXkAPbTonjT9eQApLyYNblZq+Kajnb6suK32fEfQeG1Q== X-Received: by 2002:a05:620a:1aa1:b0:7d0:69ff:385a with SMTP id af79cd13be357-7d5df181d6cmr319506185a.58.1751646942493; Fri, 04 Jul 2025 09:35:42 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556383d33f3sm298321e87.68.2025.07.04.09.35.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 09:35:41 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 04 Jul 2025 19:35:23 +0300 Subject: [PATCH v2 11/28] interconnect: qcom: qcs615: convert to dynamic IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250704-rework-icc-v2-11-875fac996ef5@oss.qualcomm.com> References: <20250704-rework-icc-v2-0-875fac996ef5@oss.qualcomm.com> In-Reply-To: <20250704-rework-icc-v2-0-875fac996ef5@oss.qualcomm.com> To: Georgi Djakov , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=44958; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=3bf8TRzsZH6WoEUnaTMAiG8XwfFK5qsNPxMs1nulwQ8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoaALGNIZKQ6CkGNaYD3z0T0PD4lCuwRAwUGFSK 6R6YWKRuJmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaGgCxgAKCRCLPIo+Aiko 1UZYB/42fed7s6h6Zw+3Jwo4bR8cA34KgAxTR5dc54XRseHfvDiSsTwQMGwAIa0TIXIKlTF9qtz Uh2BoSzBHrUTV70Gf7L30PurorNgYyb9DacMPPtkKSeMkqKxDrXwHYlSzEmodMGXVjNZ2BYmFWL sNv8ZeLjR74mgVLBFjyvqx6SrpvX92RId2byLjt7bHPXR5N4kykGYA7p4vcdc1ZQPwyTlR5KKc9 MXA+lOA1vAboXudvnxZCPKfObtXDk+oiHYNatzPn5TXbuEmCuyD9m+NupWW4oKmfuhCVRX5tnPA luFIMC++T7t1MnJ93J9M2TRXmv+VVPnLBIjCp7x78buI29Si X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: PLQdXTD_bgzkYDFgP8ckHDH-Q9AbuXA- X-Authority-Analysis: v=2.4 cv=YPWfyQGx c=1 sm=1 tr=0 ts=686802e0 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=fqGdE4ulDXNMkqeDF_EA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: PLQdXTD_bgzkYDFgP8ckHDH-Q9AbuXA- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA0MDEyNiBTYWx0ZWRfX/2izSOgcHZ2y KtDEH33PhvwKwjecrbye8FrQICFstcHhzg3RLfcYHXp5u8dYKPCFuWDZ9UpAmN9Tgi07oLfGO4U ejBPgoRdS2IOO+yJnetyAmhsfP/BnkxgijbFuzDEsun9lRXi+b0Gh/70EX1qNciY/XqsR7fUB/K qZOno92V4TmH7DYNZzGRBcqnByDSGs8WQXBH/6rSsPsIUUCbGeiQY80f6c+zTieMjRsvyY2DBSp rBfsk4e1heYP8BJFhSCCDokk9jG+W/mr73VrmIkTIYtSfqfmod95Uwp6N/4BhKgopSqCd+RSAsl Y4QJJWSNInU597TXEEcYur6qxpdVOkoC4zQ2wdLyHgzRmFDh97A5tUhsQL0Nev/NWh/RyO3ytqZ fqXUDKuBXvNTSrbJDsviwZHXT6IYKp8CYv9RQLCv2UxX5GD1GtsydgvFpAPb/gGMzvKV3wpq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_06,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507040126 Stop using fixed and IDs and covert the platform to use dynamic IDs for the interconnect. This gives more flexibility and also allows us to drop the .num_links member, saving from possible errors related to it being not set or set incorrectly. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/qcs615.c | 644 +++++++++++++++++----------------= ---- drivers/interconnect/qcom/qcs615.h | 128 -------- 2 files changed, 293 insertions(+), 479 deletions(-) diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom= /qcs615.c index acf452b5ed023b2e42b23f7455e57ab124bfa524..4fc58de384e9dec2364d78e8963= 0ef61d0338155 100644 --- a/drivers/interconnect/qcom/qcs615.c +++ b/drivers/interconnect/qcom/qcs615.c @@ -13,1058 +13,991 @@ =20 #include "bcm-voter.h" #include "icc-rpmh.h" -#include "qcs615.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_emac_avb; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_gpu_tcu; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node ipa_core_master; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_lpass_anoc; +static struct qcom_icc_node qnm_pcie_anoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_lpass_snoc; +static struct qcom_icc_node qns_pcie_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_east; +static struct qcom_icc_node qhs_ahb2phy_west; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emac_avb_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie_config; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_east; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_dc_noc_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ipa_core_slave; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; =20 static struct qcom_icc_node qhm_a1noc_cfg =3D { .name =3D "qhm_a1noc_cfg", - .id =3D QCS615_MASTER_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_SERVICE_A2NOC }, + .link_nodes =3D { &srvc_aggre2_noc, NULL }, }; =20 static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", - .id =3D QCS615_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", - .id =3D QCS615_MASTER_QSPI, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", - .id =3D QCS615_MASTER_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", - .id =3D QCS615_MASTER_BLSP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", - .id =3D QCS615_MASTER_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", - .id =3D QCS615_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", - .id =3D QCS615_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_LPASS_SNOC }, + .link_nodes =3D { &qns_lpass_snoc, NULL }, }; =20 static struct qcom_icc_node xm_emac_avb =3D { .name =3D "xm_emac_avb", - .id =3D QCS615_MASTER_EMAC_EVB, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_pcie =3D { .name =3D "xm_pcie", - .id =3D QCS615_MASTER_PCIE, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qns_pcie_snoc, NULL }, }; =20 static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", - .id =3D QCS615_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", - .id =3D QCS615_MASTER_SDCC_1, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", - .id =3D QCS615_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", - .id =3D QCS615_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_usb2 =3D { .name =3D "xm_usb2", - .id =3D QCS615_MASTER_USB2, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", - .id =3D QCS615_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_A1NOC_SNOC }, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { .name =3D "qxm_camnoc_hf0_uncomp", - .id =3D QCS615_MASTER_CAMNOC_HF0_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { .name =3D "qxm_camnoc_hf1_uncomp", - .id =3D QCS615_MASTER_CAMNOC_HF1_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { .name =3D "qxm_camnoc_sf_uncomp", - .id =3D QCS615_MASTER_CAMNOC_SF_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_CAMNOC_UNCOMP }, + .link_nodes =3D { &qns_camnoc_uncomp, NULL }, }; =20 static struct qcom_icc_node qhm_spdm =3D { .name =3D "qhm_spdm", - .id =3D QCS615_MASTER_SPDM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_CNOC_A2NOC }, + .link_nodes =3D { &qns_cnoc_a2noc, NULL }, }; =20 static struct qcom_icc_node qnm_snoc =3D { .name =3D "qnm_snoc", - .id =3D QCS615_MASTER_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 39, - .links =3D { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST, - QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP, - QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG, - QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG, - QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG, - QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG, - QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM, - QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG, - QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG, - QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG, - QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG, - QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0, - QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1, - QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG, - QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR, - QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH, - QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG, - QCS615_SLAVE_USB2, QCS615_SLAVE_USB3, - QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG, - QCS615_SLAVE_SERVICE_CNOC }, + .link_nodes =3D { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_snoc_cfg, + &qhs_spdm, &qhs_tcsr, + &qhs_tlmm_east, &qhs_tlmm_south, + &qhs_tlmm_west, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &srvc_cnoc, NULL }, }; =20 static struct qcom_icc_node xm_qdss_dap =3D { .name =3D "xm_qdss_dap", - .id =3D QCS615_MASTER_QDSS_DAP, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 40, - .links =3D { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST, - QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP, - QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG, - QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG, - QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG, - QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG, - QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM, - QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG, - QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG, - QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG, - QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG, - QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0, - QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1, - QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG, - QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR, - QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH, - QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG, - QCS615_SLAVE_USB2, QCS615_SLAVE_USB3, - QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG, - QCS615_SLAVE_CNOC_A2NOC, QCS615_SLAVE_SERVICE_CNOC }, + .link_nodes =3D { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_snoc_cfg, + &qhs_spdm, &qhs_tcsr, + &qhs_tlmm_east, &qhs_tlmm_south, + &qhs_tlmm_west, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, &srvc_cnoc, NULL }, }; =20 static struct qcom_icc_node qhm_cnoc =3D { .name =3D "qhm_cnoc", - .id =3D QCS615_MASTER_CNOC_DC_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 2, - .links =3D { QCS615_SLAVE_DC_NOC_GEMNOC, QCS615_SLAVE_LLCC_CFG }, + .link_nodes =3D { &qhs_dc_noc_gemnoc, &qhs_llcc, NULL }, }; =20 static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", - .id =3D QCS615_MASTER_APPSS_PROC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 3, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC, - QCS615_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc, + &qns_sys_pcie, NULL }, }; =20 static struct qcom_icc_node acm_gpu_tcu =3D { .name =3D "acm_gpu_tcu", - .id =3D QCS615_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", - .id =3D QCS615_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qhm_gemnoc_cfg =3D { .name =3D "qhm_gemnoc_cfg", - .id =3D QCS615_MASTER_GEM_NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 2, - .links =3D { QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, QCS615_SLAVE_SERVICE_GEM_N= OC }, + .link_nodes =3D { &qhs_mdsp_ms_mpu_cfg, &srvc_gemnoc, NULL }, }; =20 static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", - .id =3D QCS615_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", - .id =3D QCS615_MASTER_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", - .id =3D QCS615_MASTER_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 2, - .links =3D { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", - .id =3D QCS615_MASTER_SNOC_GC_MEM_NOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc, NULL }, }; =20 static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", - .id =3D QCS615_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_LLCC }, + .link_nodes =3D { &qns_llcc, NULL }, }; =20 static struct qcom_icc_node ipa_core_master =3D { .name =3D "ipa_core_master", - .id =3D QCS615_MASTER_IPA_CORE, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_IPA_CORE }, + .link_nodes =3D { &ipa_core_slave, NULL }, }; =20 static struct qcom_icc_node llcc_mc =3D { .name =3D "llcc_mc", - .id =3D QCS615_MASTER_LLCC, .channels =3D 2, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_EBI1 }, + .link_nodes =3D { &ebi, NULL }, }; =20 static struct qcom_icc_node qhm_mnoc_cfg =3D { .name =3D "qhm_mnoc_cfg", - .id =3D QCS615_MASTER_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_SERVICE_MNOC }, + .link_nodes =3D { &srvc_mnoc, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", - .id =3D QCS615_MASTER_CAMNOC_HF0, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", - .id =3D QCS615_MASTER_CAMNOC_HF1, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", - .id =3D QCS615_MASTER_CAMNOC_SF, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc, NULL }, }; =20 static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", - .id =3D QCS615_MASTER_MDP0, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, }; =20 static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", - .id =3D QCS615_MASTER_ROTATOR, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc, NULL }, }; =20 static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", - .id =3D QCS615_MASTER_VIDEO_P0, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc, NULL }, }; =20 static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", - .id =3D QCS615_MASTER_VIDEO_PROC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qns2_mem_noc, NULL }, }; =20 static struct qcom_icc_node qhm_snoc_cfg =3D { .name =3D "qhm_snoc_cfg", - .id =3D QCS615_MASTER_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_SERVICE_SNOC }, + .link_nodes =3D { &srvc_snoc, NULL }, }; =20 static struct qcom_icc_node qnm_aggre1_noc =3D { .name =3D "qnm_aggre1_noc", - .id =3D QCS615_MASTER_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 8, - .links =3D { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0, - QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU }, + .link_nodes =3D { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &qxs_pimem, &xs_pcie, + &xs_qdss_stm, &xs_sys_tcu_cfg, NULL }, }; =20 static struct qcom_icc_node qnm_gemnoc =3D { .name =3D "qnm_gemnoc", - .id =3D QCS615_MASTER_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 6, - .links =3D { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_IMEM, QCS615_SLAVE_PIMEM, - QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU }, + .link_nodes =3D { &qhs_apss, &qns_cnoc, + &qxs_imem, &qxs_pimem, + &xs_qdss_stm, &xs_sys_tcu_cfg, NULL }, }; =20 static struct qcom_icc_node qnm_gemnoc_pcie =3D { .name =3D "qnm_gemnoc_pcie", - .id =3D QCS615_MASTER_GEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_SLAVE_PCIE_0 }, + .link_nodes =3D { &xs_pcie, NULL }, }; =20 static struct qcom_icc_node qnm_lpass_anoc =3D { .name =3D "qnm_lpass_anoc", - .id =3D QCS615_MASTER_LPASS_ANOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 7, - .links =3D { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0, - QCS615_SLAVE_QDSS_STM }, + .link_nodes =3D { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &qxs_pimem, &xs_pcie, + &xs_qdss_stm, NULL }, }; =20 static struct qcom_icc_node qnm_pcie_anoc =3D { .name =3D "qnm_pcie_anoc", - .id =3D QCS615_MASTER_ANOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 5, - .links =3D { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, - QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, - QCS615_SLAVE_QDSS_STM }, + .link_nodes =3D { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &xs_qdss_stm, NULL }, }; =20 static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", - .id =3D QCS615_MASTER_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM }, + .link_nodes =3D { &qns_memnoc_gc, &qxs_imem, NULL }, }; =20 static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", - .id =3D QCS615_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 2, - .links =3D { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM }, + .link_nodes =3D { &qns_memnoc_gc, &qxs_imem, NULL }, }; =20 static struct qcom_icc_node qns_a1noc_snoc =3D { .name =3D "qns_a1noc_snoc", - .id =3D QCS615_SLAVE_A1NOC_SNOC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { QCS615_MASTER_A1NOC_SNOC }, + .link_nodes =3D { &qnm_aggre1_noc, NULL }, }; =20 static struct qcom_icc_node qns_lpass_snoc =3D { .name =3D "qns_lpass_snoc", - .id =3D QCS615_SLAVE_LPASS_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_MASTER_LPASS_ANOC }, + .link_nodes =3D { &qnm_lpass_anoc, NULL }, }; =20 static struct qcom_icc_node qns_pcie_snoc =3D { .name =3D "qns_pcie_snoc", - .id =3D QCS615_SLAVE_ANOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_MASTER_ANOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_pcie_anoc, NULL }, }; =20 static struct qcom_icc_node srvc_aggre2_noc =3D { .name =3D "srvc_aggre2_noc", - .id =3D QCS615_SLAVE_SERVICE_A2NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_camnoc_uncomp =3D { .name =3D "qns_camnoc_uncomp", - .id =3D QCS615_SLAVE_CAMNOC_UNCOMP, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_a1_noc_cfg =3D { .name =3D "qhs_a1_noc_cfg", - .id =3D QCS615_SLAVE_A1NOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_MASTER_A1NOC_CFG }, + .link_nodes =3D { &qhm_a1noc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_ahb2phy_east =3D { .name =3D "qhs_ahb2phy_east", - .id =3D QCS615_SLAVE_AHB2PHY_EAST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ahb2phy_west =3D { .name =3D "qhs_ahb2phy_west", - .id =3D QCS615_SLAVE_AHB2PHY_WEST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_aop =3D { .name =3D "qhs_aop", - .id =3D QCS615_SLAVE_AOP, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_aoss =3D { .name =3D "qhs_aoss", - .id =3D QCS615_SLAVE_AOSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_camera_cfg =3D { .name =3D "qhs_camera_cfg", - .id =3D QCS615_SLAVE_CAMERA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_clk_ctl =3D { .name =3D "qhs_clk_ctl", - .id =3D QCS615_SLAVE_CLK_CTL, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cpr_cx =3D { .name =3D "qhs_cpr_cx", - .id =3D QCS615_SLAVE_RBCPR_CX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_cpr_mx =3D { .name =3D "qhs_cpr_mx", - .id =3D QCS615_SLAVE_RBCPR_MX_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_crypto0_cfg =3D { .name =3D "qhs_crypto0_cfg", - .id =3D QCS615_SLAVE_CRYPTO_0_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ddrss_cfg =3D { .name =3D "qhs_ddrss_cfg", - .id =3D QCS615_SLAVE_CNOC_DDRSS, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_MASTER_CNOC_DC_NOC }, + .link_nodes =3D { &qhm_cnoc, NULL }, }; =20 static struct qcom_icc_node qhs_display_cfg =3D { .name =3D "qhs_display_cfg", - .id =3D QCS615_SLAVE_DISPLAY_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_emac_avb_cfg =3D { .name =3D "qhs_emac_avb_cfg", - .id =3D QCS615_SLAVE_EMAC_AVB_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_glm =3D { .name =3D "qhs_glm", - .id =3D QCS615_SLAVE_GLM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_gpuss_cfg =3D { .name =3D "qhs_gpuss_cfg", - .id =3D QCS615_SLAVE_GFX3D_CFG, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_imem_cfg =3D { .name =3D "qhs_imem_cfg", - .id =3D QCS615_SLAVE_IMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ipa =3D { .name =3D "qhs_ipa", - .id =3D QCS615_SLAVE_IPA_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_mnoc_cfg =3D { .name =3D "qhs_mnoc_cfg", - .id =3D QCS615_SLAVE_CNOC_MNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_MASTER_CNOC_MNOC_CFG }, + .link_nodes =3D { &qhm_mnoc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_pcie_config =3D { .name =3D "qhs_pcie_config", - .id =3D QCS615_SLAVE_PCIE_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_pimem_cfg =3D { .name =3D "qhs_pimem_cfg", - .id =3D QCS615_SLAVE_PIMEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_prng =3D { .name =3D "qhs_prng", - .id =3D QCS615_SLAVE_PRNG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qdss_cfg =3D { .name =3D "qhs_qdss_cfg", - .id =3D QCS615_SLAVE_QDSS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qspi =3D { .name =3D "qhs_qspi", - .id =3D QCS615_SLAVE_QSPI, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qup0 =3D { .name =3D "qhs_qup0", - .id =3D QCS615_SLAVE_QUP_0, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_qup1 =3D { .name =3D "qhs_qup1", - .id =3D QCS615_SLAVE_QUP_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_sdc1 =3D { .name =3D "qhs_sdc1", - .id =3D QCS615_SLAVE_SDCC_1, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_sdc2 =3D { .name =3D "qhs_sdc2", - .id =3D QCS615_SLAVE_SDCC_2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_snoc_cfg =3D { .name =3D "qhs_snoc_cfg", - .id =3D QCS615_SLAVE_SNOC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_MASTER_SNOC_CFG }, + .link_nodes =3D { &qhm_snoc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_spdm =3D { .name =3D "qhs_spdm", - .id =3D QCS615_SLAVE_SPDM_WRAPPER, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tcsr =3D { .name =3D "qhs_tcsr", - .id =3D QCS615_SLAVE_TCSR, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tlmm_east =3D { .name =3D "qhs_tlmm_east", - .id =3D QCS615_SLAVE_TLMM_EAST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tlmm_south =3D { .name =3D "qhs_tlmm_south", - .id =3D QCS615_SLAVE_TLMM_SOUTH, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_tlmm_west =3D { .name =3D "qhs_tlmm_west", - .id =3D QCS615_SLAVE_TLMM_WEST, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_ufs_mem_cfg =3D { .name =3D "qhs_ufs_mem_cfg", - .id =3D QCS615_SLAVE_UFS_MEM_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_usb2 =3D { .name =3D "qhs_usb2", - .id =3D QCS615_SLAVE_USB2, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_usb3 =3D { .name =3D "qhs_usb3", - .id =3D QCS615_SLAVE_USB3, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_venus_cfg =3D { .name =3D "qhs_venus_cfg", - .id =3D QCS615_SLAVE_VENUS_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { .name =3D "qhs_vsense_ctrl_cfg", - .id =3D QCS615_SLAVE_VSENSE_CTRL_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_cnoc_a2noc =3D { .name =3D "qns_cnoc_a2noc", - .id =3D QCS615_SLAVE_CNOC_A2NOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_MASTER_CNOC_A2NOC }, + .link_nodes =3D { &qnm_cnoc, NULL }, }; =20 static struct qcom_icc_node srvc_cnoc =3D { .name =3D "srvc_cnoc", - .id =3D QCS615_SLAVE_SERVICE_CNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_dc_noc_gemnoc =3D { .name =3D "qhs_dc_noc_gemnoc", - .id =3D QCS615_SLAVE_DC_NOC_GEMNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 1, - .links =3D { QCS615_MASTER_GEM_NOC_CFG }, + .link_nodes =3D { &qhm_gemnoc_cfg, NULL }, }; =20 static struct qcom_icc_node qhs_llcc =3D { .name =3D "qhs_llcc", - .id =3D QCS615_SLAVE_LLCC_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { .name =3D "qhs_mdsp_ms_mpu_cfg", - .id =3D QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_gem_noc_snoc =3D { .name =3D "qns_gem_noc_snoc", - .id =3D QCS615_SLAVE_GEM_NOC_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_MASTER_GEM_NOC_SNOC }, + .link_nodes =3D { &qnm_gemnoc, NULL }, }; =20 static struct qcom_icc_node qns_llcc =3D { .name =3D "qns_llcc", - .id =3D QCS615_SLAVE_LLCC, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { QCS615_MASTER_LLCC }, + .link_nodes =3D { &llcc_mc, NULL }, }; =20 static struct qcom_icc_node qns_sys_pcie =3D { .name =3D "qns_sys_pcie", - .id =3D QCS615_SLAVE_MEM_NOC_PCIE_SNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes =3D { &qnm_gemnoc_pcie, NULL }, }; =20 static struct qcom_icc_node srvc_gemnoc =3D { .name =3D "srvc_gemnoc", - .id =3D QCS615_SLAVE_SERVICE_GEM_NOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node ipa_core_slave =3D { .name =3D "ipa_core_slave", - .id =3D QCS615_SLAVE_IPA_CORE, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node ebi =3D { .name =3D "ebi", - .id =3D QCS615_SLAVE_EBI1, .channels =3D 2, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns2_mem_noc =3D { .name =3D "qns2_mem_noc", - .id =3D QCS615_SLAVE_MNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_sf, NULL }, }; =20 static struct qcom_icc_node qns_mem_noc_hf =3D { .name =3D "qns_mem_noc_hf", - .id =3D QCS615_SLAVE_MNOC_HF_MEM_NOC, .channels =3D 1, .buswidth =3D 32, - .num_links =3D 1, - .links =3D { QCS615_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes =3D { &qnm_mnoc_hf, NULL }, }; =20 static struct qcom_icc_node srvc_mnoc =3D { .name =3D "srvc_mnoc", - .id =3D QCS615_SLAVE_SERVICE_MNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qhs_apss =3D { .name =3D "qhs_apss", - .id =3D QCS615_SLAVE_APPSS, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qns_cnoc =3D { .name =3D "qns_cnoc", - .id =3D QCS615_SLAVE_SNOC_CNOC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_MASTER_SNOC_CNOC }, + .link_nodes =3D { &qnm_snoc, NULL }, }; =20 static struct qcom_icc_node qns_gemnoc_sf =3D { .name =3D "qns_gemnoc_sf", - .id =3D QCS615_SLAVE_SNOC_GEM_NOC_SF, .channels =3D 1, .buswidth =3D 16, - .num_links =3D 1, - .links =3D { QCS615_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_sf, NULL }, }; =20 static struct qcom_icc_node qns_memnoc_gc =3D { .name =3D "qns_memnoc_gc", - .id =3D QCS615_SLAVE_SNOC_MEM_NOC_GC, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 1, - .links =3D { QCS615_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes =3D { &qnm_snoc_gc, NULL }, }; =20 static struct qcom_icc_node qxs_imem =3D { .name =3D "qxs_imem", - .id =3D QCS615_SLAVE_IMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node qxs_pimem =3D { .name =3D "qxs_pimem", - .id =3D QCS615_SLAVE_PIMEM, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node srvc_snoc =3D { .name =3D "srvc_snoc", - .id =3D QCS615_SLAVE_SERVICE_SNOC, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_pcie =3D { .name =3D "xs_pcie", - .id =3D QCS615_SLAVE_PCIE_0, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_qdss_stm =3D { .name =3D "xs_qdss_stm", - .id =3D QCS615_SLAVE_QDSS_STM, .channels =3D 1, .buswidth =3D 4, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_node xs_sys_tcu_cfg =3D { .name =3D "xs_sys_tcu_cfg", - .id =3D QCS615_SLAVE_TCU, .channels =3D 1, .buswidth =3D 8, - .num_links =3D 0, + .link_nodes =3D { NULL }, }; =20 static struct qcom_icc_bcm bcm_acv =3D { @@ -1261,6 +1194,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_aggre1_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, @@ -1279,6 +1213,7 @@ static struct qcom_icc_node * const camnoc_virt_nodes= [] =3D { }; =20 static const struct qcom_icc_desc qcs615_camnoc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D camnoc_virt_nodes, .num_nodes =3D ARRAY_SIZE(camnoc_virt_nodes), .bcms =3D camnoc_virt_bcms, @@ -1337,6 +1272,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_config_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1350,6 +1286,7 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_dc_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1379,6 +1316,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_gem_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1395,6 +1333,7 @@ static struct qcom_icc_node * const ipa_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_ipa_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D ipa_virt_nodes, .num_nodes =3D ARRAY_SIZE(ipa_virt_nodes), .bcms =3D ipa_virt_bcms, @@ -1412,6 +1351,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_mc_virt =3D { + .alloc_dyn_id =3D true, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1440,6 +1380,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc qcs615_mmss_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1482,6 +1423,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc qcs615_system_noc =3D { + .alloc_dyn_id =3D true, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, diff --git a/drivers/interconnect/qcom/qcs615.h b/drivers/interconnect/qcom= /qcs615.h deleted file mode 100644 index 66e66c7e23d4ecaf92c2697e695980c3f8663664..000000000000000000000000000= 0000000000000 --- a/drivers/interconnect/qcom/qcs615.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS615_H -#define __DRIVERS_INTERCONNECT_QCOM_QCS615_H - -#define QCS615_MASTER_A1NOC_CFG 1 -#define QCS615_MASTER_A1NOC_SNOC 2 -#define QCS615_MASTER_ANOC_PCIE_SNOC 3 -#define QCS615_MASTER_APPSS_PROC 4 -#define QCS615_MASTER_BLSP_1 5 -#define QCS615_MASTER_CAMNOC_HF0 6 -#define QCS615_MASTER_CAMNOC_HF0_UNCOMP 7 -#define QCS615_MASTER_CAMNOC_HF1 8 -#define QCS615_MASTER_CAMNOC_HF1_UNCOMP 9 -#define QCS615_MASTER_CAMNOC_SF 10 -#define QCS615_MASTER_CAMNOC_SF_UNCOMP 11 -#define QCS615_MASTER_CNOC_A2NOC 12 -#define QCS615_MASTER_CNOC_DC_NOC 13 -#define QCS615_MASTER_CNOC_MNOC_CFG 14 -#define QCS615_MASTER_CRYPTO 15 -#define QCS615_MASTER_EMAC_EVB 16 -#define QCS615_MASTER_GEM_NOC_CFG 17 -#define QCS615_MASTER_GEM_NOC_PCIE_SNOC 18 -#define QCS615_MASTER_GEM_NOC_SNOC 19 -#define QCS615_MASTER_GFX3D 20 -#define QCS615_MASTER_GIC 21 -#define QCS615_MASTER_GPU_TCU 22 -#define QCS615_MASTER_IPA 23 -#define QCS615_MASTER_IPA_CORE 24 -#define QCS615_MASTER_LLCC 25 -#define QCS615_MASTER_LPASS_ANOC 26 -#define QCS615_MASTER_MDP0 27 -#define QCS615_MASTER_MNOC_HF_MEM_NOC 28 -#define QCS615_MASTER_MNOC_SF_MEM_NOC 29 -#define QCS615_MASTER_PCIE 30 -#define QCS615_MASTER_PIMEM 31 -#define QCS615_MASTER_QDSS_BAM 32 -#define QCS615_MASTER_QDSS_DAP 33 -#define QCS615_MASTER_QDSS_ETR 34 -#define QCS615_MASTER_QSPI 35 -#define QCS615_MASTER_QUP_0 36 -#define QCS615_MASTER_ROTATOR 37 -#define QCS615_MASTER_SDCC_1 38 -#define QCS615_MASTER_SDCC_2 39 -#define QCS615_MASTER_SNOC_CFG 40 -#define QCS615_MASTER_SNOC_CNOC 41 -#define QCS615_MASTER_SNOC_GC_MEM_NOC 42 -#define QCS615_MASTER_SNOC_SF_MEM_NOC 43 -#define QCS615_MASTER_SPDM 44 -#define QCS615_MASTER_SYS_TCU 45 -#define QCS615_MASTER_UFS_MEM 46 -#define QCS615_MASTER_USB2 47 -#define QCS615_MASTER_USB3_0 48 -#define QCS615_MASTER_VIDEO_P0 49 -#define QCS615_MASTER_VIDEO_PROC 50 -#define QCS615_SLAVE_A1NOC_CFG 51 -#define QCS615_SLAVE_A1NOC_SNOC 52 -#define QCS615_SLAVE_AHB2PHY_EAST 53 -#define QCS615_SLAVE_AHB2PHY_WEST 54 -#define QCS615_SLAVE_ANOC_PCIE_SNOC 55 -#define QCS615_SLAVE_AOP 56 -#define QCS615_SLAVE_AOSS 57 -#define QCS615_SLAVE_APPSS 58 -#define QCS615_SLAVE_CAMERA_CFG 59 -#define QCS615_SLAVE_CAMNOC_UNCOMP 60 -#define QCS615_SLAVE_CLK_CTL 61 -#define QCS615_SLAVE_CNOC_A2NOC 62 -#define QCS615_SLAVE_CNOC_DDRSS 63 -#define QCS615_SLAVE_CNOC_MNOC_CFG 64 -#define QCS615_SLAVE_CRYPTO_0_CFG 65 -#define QCS615_SLAVE_DC_NOC_GEMNOC 66 -#define QCS615_SLAVE_DISPLAY_CFG 67 -#define QCS615_SLAVE_EBI1 68 -#define QCS615_SLAVE_EMAC_AVB_CFG 69 -#define QCS615_SLAVE_GEM_NOC_SNOC 70 -#define QCS615_SLAVE_GFX3D_CFG 71 -#define QCS615_SLAVE_GLM 72 -#define QCS615_SLAVE_IMEM 73 -#define QCS615_SLAVE_IMEM_CFG 74 -#define QCS615_SLAVE_IPA_CFG 75 -#define QCS615_SLAVE_IPA_CORE 76 -#define QCS615_SLAVE_LLCC 77 -#define QCS615_SLAVE_LLCC_CFG 78 -#define QCS615_SLAVE_LPASS_SNOC 79 -#define QCS615_SLAVE_MEM_NOC_PCIE_SNOC 80 -#define QCS615_SLAVE_MNOC_HF_MEM_NOC 81 -#define QCS615_SLAVE_MNOC_SF_MEM_NOC 82 -#define QCS615_SLAVE_MSS_PROC_MS_MPU_CFG 83 -#define QCS615_SLAVE_PCIE_0 84 -#define QCS615_SLAVE_PCIE_CFG 85 -#define QCS615_SLAVE_PIMEM 86 -#define QCS615_SLAVE_PIMEM_CFG 87 -#define QCS615_SLAVE_PRNG 88 -#define QCS615_SLAVE_QDSS_CFG 89 -#define QCS615_SLAVE_QDSS_STM 90 -#define QCS615_SLAVE_QSPI 91 -#define QCS615_SLAVE_QUP_0 92 -#define QCS615_SLAVE_QUP_1 93 -#define QCS615_SLAVE_RBCPR_CX_CFG 94 -#define QCS615_SLAVE_RBCPR_MX_CFG 95 -#define QCS615_SLAVE_SDCC_1 96 -#define QCS615_SLAVE_SDCC_2 97 -#define QCS615_SLAVE_SERVICE_A2NOC 98 -#define QCS615_SLAVE_SERVICE_CNOC 99 -#define QCS615_SLAVE_SERVICE_GEM_NOC 100 -#define QCS615_SLAVE_SERVICE_MNOC 101 -#define QCS615_SLAVE_SERVICE_SNOC 102 -#define QCS615_SLAVE_SNOC_CFG 103 -#define QCS615_SLAVE_SNOC_CNOC 104 -#define QCS615_SLAVE_SNOC_GEM_NOC_SF 105 -#define QCS615_SLAVE_SNOC_MEM_NOC_GC 106 -#define QCS615_SLAVE_SPDM_WRAPPER 107 -#define QCS615_SLAVE_TCSR 108 -#define QCS615_SLAVE_TCU 109 -#define QCS615_SLAVE_TLMM_EAST 110 -#define QCS615_SLAVE_TLMM_SOUTH 111 -#define QCS615_SLAVE_TLMM_WEST 112 -#define QCS615_SLAVE_UFS_MEM_CFG 113 -#define QCS615_SLAVE_USB2 114 -#define QCS615_SLAVE_USB3 115 -#define QCS615_SLAVE_VENUS_CFG 116 -#define QCS615_SLAVE_VSENSE_CTRL_CFG 117 - -#endif - --=20 2.39.5