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Change the wording so that it will remain valid even if additional macros are added to the file. Fix a couple of spelling errors and grammatical errors, and break up a run-on sentence, for clarity. Cc: Alexandre Courbot Cc: Danilo Krummrich Signed-off-by: John Hubbard Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index cdf668073480ed703c89ffa8628f5c9de6494687..864d1e83bed2979f5661e038f4c= 9fd87d33f69a7 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -1,17 +1,17 @@ // SPDX-License-Identifier: GPL-2.0 =20 -//! Macro to define register layout and accessors. +//! `register!` macro to define register layout and accessors. //! //! A single register typically includes several fields, which are accesse= d through a combination //! of bit-shift and mask operations that introduce a class of potential m= istakes, notably because //! not all possible field values are necessarily valid. //! -//! The macro in this module allow to define, using an intruitive and read= able syntax, a dedicated -//! type for each register with its own field accessors that can return an= error is a field's value -//! is invalid. +//! The `register!` macro in this module provides an intuitive and readabl= e syntax for defining a +//! dedicated type for each register. Each such type comes with its own fi= eld accessors that can +//! return an error if a field's value is invalid. =20 -/// Defines a dedicated type for a register with an absolute offset, along= side with getter and -/// setter methods for its fields and methods to read and write it from an= `Io` region. +/// Defines a dedicated type for a register with an absolute offset, inclu= ding getter and setter +/// methods for its fields and methods to read and write it from an `Io` r= egion. /// /// Example: /// @@ -24,7 +24,7 @@ /// ``` /// /// This defines a `BOOT_0` type which can be read or written from offset = `0x100` of an `Io` -/// region. It is composed of 3 fields, for instance `minor_revision` is m= ade of the 4 less +/// region. It is composed of 3 fields, for instance `minor_revision` is m= ade of the 4 least /// significant bits of the register. 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 864d1e83bed2979f5661e038f4c9fd87d33f69a7..93e9055d5ebd5f78ea534aafd44= d884da0fce345 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -116,7 +116,7 @@ macro_rules! register { ) =3D> { register!(@common $name @ $offset $(, $comment)?); register!(@field_accessors $name { $($fields)* }); - register!(@io$name @ + $offset); + register!(@io $name @ + $offset); }; =20 // Creates a alias register of relative offset register `alias` with i= ts own fields. --=20 2.50.0 From nobody Sun Feb 8 18:18:56 2026 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2053.outbound.protection.outlook.com [40.107.94.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C539280CD5; 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Also simplify the example itself and reword the explanation a bit. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 93e9055d5ebd5f78ea534aafd44d884da0fce345..8a2001c07654cd6516b09be330e= 7a595695b365b 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -76,15 +76,17 @@ /// for cases where a register's interpretation depends on the context: /// /// ```no_run -/// register!(SCRATCH_0 @ 0x0000100, "Scratch register 0" { +/// register!(SCRATCH @ 0x0000200, "Scratch register" { /// 31:0 value as u32, "Raw value"; +/// }); /// -/// register!(SCRATCH_0_BOOT_STATUS =3D> SCRATCH_0, "Boot status of the fi= rmware" { +/// register!(SCRATCH_BOOT_STATUS =3D> SCRATCH, "Boot status of the firmwa= re" { /// 0:0 completed as bool, "Whether the firmware has completed boo= ting"; +/// }); /// ``` /// /// In this example, `SCRATCH_0_BOOT_STATUS` uses the same I/O address as = `SCRATCH_0`, while also -/// providing its own `completed` method. +/// providing its own `completed` field. macro_rules! register { // Creates a register at a fixed offset of the MMIO space. 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 8a2001c07654cd6516b09be330e7a595695b365b..7d5cd45d3e787301acab0b4d8ce= 1002c2dd2cab2 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -230,7 +230,7 @@ impl $name { $(, $comment:literal)?; ) =3D> { register!( - @leaf_accessor $name $hi:$lo $field as bool + @leaf_accessor $name $hi:$lo $field { |f| <$into_type>::from(if f !=3D 0 { true } else { false }) } $into_type =3D> $into_type $(, $comment)?; ); @@ -248,7 +248,7 @@ impl $name { @field_accessor $name:ident $hi:tt:$lo:tt $field:ident as $type:tt= ?=3D> $try_into_type:ty $(, $comment:literal)?; ) =3D> { - register!(@leaf_accessor $name $hi:$lo $field as $type + register!(@leaf_accessor $name $hi:$lo $field { |f| <$try_into_type>::try_from(f as $type) } $try_into_type = =3D> ::core::result::Result< $try_into_type, @@ -262,7 +262,7 @@ impl $name { @field_accessor $name:ident $hi:tt:$lo:tt $field:ident as $type:tt= =3D> $into_type:ty $(, $comment:literal)?; ) =3D> { - register!(@leaf_accessor $name $hi:$lo $field as $type + register!(@leaf_accessor $name $hi:$lo $field { |f| <$into_type>::from(f as $type) } $into_type =3D> $into_t= ype $(, $comment)?;); }; =20 @@ -276,7 +276,7 @@ impl $name { =20 // Generates the accessor methods for a single field. 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Thus remove the `try_` accessors that have no purpose. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 38 +-------------------------------= ---- 1 file changed, 1 insertion(+), 37 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 7d5cd45d3e787301acab0b4d8ce1002c2dd2cab2..087f92f78788a013702cbc0a6e1= 56e40f7695347 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -57,9 +57,7 @@ /// definition, or the field getter and setter methods they are attached t= o. /// /// Putting a `+` before the address of the register makes it relative to = a base: the `read` and -/// `write` methods take a `base` argument that is added to the specified = address before access, -/// and `try_read` and `try_write` methods are also created, allowing acce= ss with offsets unknown -/// at compile-time: +/// `write` methods take a `base` argument that is added to the specified = address before access: /// /// ```no_run /// register!(CPU_CTL @ +0x0000010, "CPU core control" { @@ -386,40 +384,6 @@ pub(crate) fn alter( let reg =3D f(Self::read(io, base)); reg.write(io, base); } - - #[inline] - pub(crate) fn try_read( - io: &T, - base: usize, - ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, - { - io.try_read32(base + $offset).map(Self) - } - - #[inline] - pub(crate) fn try_write( - self, - io: &T, - base: usize, - ) -> ::kernel::error::Result<()> where - T: ::core::ops::Deref>, - { - io.try_write32(self.0, base + $offset) - } - - #[inline] - pub(crate) fn try_alter( - io: &T, - base: usize, - f: F, - ) -> ::kernel::error::Result<()> where - T: ::core::ops::Deref>, - F: ::core::ops::FnOnce(Self) -> Self, - { - let reg =3D f(Self::try_read(io, base)?); - reg.try_write(io, base) - } } }; } --=20 2.50.0 From nobody Sun Feb 8 18:18:56 2026 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2080.outbound.protection.outlook.com [40.107.94.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C07A285068; 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Thus, move OFFSET to the I/O impl block so it is not needed by the @common rule anymore. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 087f92f78788a013702cbc0a6e156e40f7695347..b096a3689483fa79dc22f16f4ba= ac2f9a9495c28 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -92,7 +92,7 @@ macro_rules! register { $($fields:tt)* } ) =3D> { - register!(@common $name @ $offset $(, $comment)?); + register!(@common $name $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ $offset); }; @@ -103,7 +103,7 @@ macro_rules! register { $($fields:tt)* } ) =3D> { - register!(@common $name @ $alias::OFFSET $(, $comment)?); + register!(@common $name $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ $alias::OFFSET); }; @@ -114,7 +114,7 @@ macro_rules! register { $($fields:tt)* } ) =3D> { - register!(@common $name @ $offset $(, $comment)?); + register!(@common $name $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ + $offset); }; @@ -125,7 +125,7 @@ macro_rules! register { $($fields:tt)* } ) =3D> { - register!(@common $name @ $alias::OFFSET $(, $comment)?); + register!(@common $name $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ + $alias::OFFSET); }; @@ -134,7 +134,7 @@ macro_rules! register { =20 // Defines the wrapper `$name` type, as well as its relevant implement= ations (`Debug`, `BitOr`, // and conversion to regular `u32`). - (@common $name:ident @ $offset:expr $(, $comment:literal)?) =3D> { + (@common $name:ident $(, $comment:literal)?) =3D> { $( #[doc=3D$comment] )? @@ -142,11 +142,6 @@ macro_rules! register { #[derive(Clone, Copy, Default)] pub(crate) struct $name(u32); =20 - #[allow(dead_code)] - impl $name { - pub(crate) const OFFSET: usize =3D $offset; - } - // TODO[REGA]: display the raw hex value, then the value of all th= e fields. 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 34 +++++++++-----------------------= -- 1 file changed, 9 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index b096a3689483fa79dc22f16f4baac2f9a9495c28..73ee72a6c7baa7e9d1032ec0da1= 19940b8f1a3f7 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -87,44 +87,28 @@ /// providing its own `completed` field. macro_rules! register { // Creates a register at a fixed offset of the MMIO space. - ( - $name:ident @ $offset:literal $(, $comment:literal)? { - $($fields:tt)* - } - ) =3D> { + ($name:ident @ $offset:literal $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { register!(@common $name $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ $offset); }; =20 - // Creates a alias register of fixed offset register `alias` with its = own fields. - ( - $name:ident =3D> $alias:ident $(, $comment:literal)? { - $($fields:tt)* - } - ) =3D> { + // Creates an alias register of fixed offset register `alias` with its= own fields. + ($name:ident =3D> $alias:ident $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { register!(@common $name $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ $alias::OFFSET); }; =20 // Creates a register at a relative offset from a base address. - ( - $name:ident @ + $offset:literal $(, $comment:literal)? { - $($fields:tt)* - } - ) =3D> { + ($name:ident @ + $offset:literal $(, $comment:literal)? { $($fields:tt= )* } ) =3D> { register!(@common $name $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ + $offset); }; =20 - // Creates a alias register of relative offset register `alias` with i= ts own fields. - ( - $name:ident =3D> + $alias:ident $(, $comment:literal)? { - $($fields:tt)* - } - ) =3D> { + // Creates an alias register of relative offset register `alias` with = its own fields. + ($name:ident =3D> + $alias:ident $(, $comment:literal)? { $($fields:tt= )* } ) =3D> { register!(@common $name $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ + $alias::OFFSET); @@ -259,7 +243,7 @@ impl $name { { |f| <$into_type>::from(f as $type) } $into_type =3D> $into_t= ype $(, $comment)?;); }; =20 - // Shortcut for fields defined as non-`bool` without the `=3D>` or `?= =3D>` syntax. + // Shortcut for non-boolean fields defined without the `=3D>` or `?=3D= >` syntax. ( @field_accessor $name:ident $hi:tt:$lo:tt $field:ident as $type:tt $(, $comment:literal)?; @@ -310,7 +294,7 @@ pub(crate) fn [](mut self, value: $to_type= ) -> Self { ); }; =20 - // Creates the IO accessors for a fixed offset register. + // Generates the IO accessors for a fixed offset register. (@io $name:ident @ $offset:expr) =3D> { #[allow(dead_code)] impl $name { @@ -344,7 +328,7 @@ pub(crate) fn alter( } }; =20 - // Create the IO accessors for a relative offset register. + // Generates the IO accessors for a relative offset register. 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 73ee72a6c7baa7e9d1032ec0da119940b8f1a3f7..60e5e6a2250a9db453a7a648108= af6acaa047342 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -300,6 +300,7 @@ pub(crate) fn [](mut self, value: $to_type= ) -> Self { impl $name { pub(crate) const OFFSET: usize =3D $offset; =20 + /// Read the register from its address in `io`. #[inline] pub(crate) fn read(io: &T) -> Self where T: ::core::ops::Deref>, @@ -307,6 +308,7 @@ pub(crate) fn read(io: &T) -> Sel= f where Self(io.read32($offset)) } =20 + /// Write the value contained in `self` to the register addres= s in `io`. #[inline] pub(crate) fn write(self, io: &T) where T: ::core::ops::Deref>, @@ -314,6 +316,8 @@ pub(crate) fn write(self, io: &T)= where io.write32(self.0, $offset) } =20 + /// Read the register from its address in `io` and run `f` on = its value to obtain a new + /// value to write back. #[inline] pub(crate) fn alter( io: &T, --=20 2.50.0 From nobody Sun Feb 8 18:18:56 2026 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2051.outbound.protection.outlook.com [40.107.94.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3372285C86; 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However, there are other places (like the `Debug` and `Default` implementations) where we would benefit from having access to at least some of the field information, but refrained from doing so because it would have meant matching the whole fields in a rule more complex than we need. Introduce a new `@fields_dispatcher` internal rule that captures all the field information and passes it to `@field_accessors`. It does not provide any functional change in itself, but allows us to reuse the captured field information partially to provide better `Debug` and `Default` implementations in following patches. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 42 +++++++++++++++++++++++++++-----= ---- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 60e5e6a2250a9db453a7a648108af6acaa047342..1d473ceb7b97e18e36246569abf= 0bb04e7b02060 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -88,37 +88,33 @@ macro_rules! register { // Creates a register at a fixed offset of the MMIO space. ($name:ident @ $offset:literal $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { - register!(@common $name $(, $comment)?); - register!(@field_accessors $name { $($fields)* }); + register!(@core $name $(, $comment)? { $($fields)* } ); register!(@io $name @ $offset); }; =20 // Creates an alias register of fixed offset register `alias` with its= own fields. ($name:ident =3D> $alias:ident $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { - register!(@common $name $(, $comment)?); - register!(@field_accessors $name { $($fields)* }); + register!(@core $name $(, $comment)? { $($fields)* } ); register!(@io $name @ $alias::OFFSET); }; =20 // Creates a register at a relative offset from a base address. ($name:ident @ + $offset:literal $(, $comment:literal)? { $($fields:tt= )* } ) =3D> { - register!(@common $name $(, $comment)?); - register!(@field_accessors $name { $($fields)* }); + register!(@core $name $(, $comment)? { $($fields)* } ); register!(@io $name @ + $offset); }; =20 // Creates an alias register of relative offset register `alias` with = its own fields. ($name:ident =3D> + $alias:ident $(, $comment:literal)? { $($fields:tt= )* } ) =3D> { - register!(@common $name $(, $comment)?); - register!(@field_accessors $name { $($fields)* }); + register!(@core $name $(, $comment)? { $($fields)* } ); register!(@io $name @ + $alias::OFFSET); }; =20 // All rules below are helpers. =20 // Defines the wrapper `$name` type, as well as its relevant implement= ations (`Debug`, `BitOr`, - // and conversion to regular `u32`). - (@common $name:ident $(, $comment:literal)?) =3D> { + // and conversion to the value type) and field accessor methods. + (@core $name:ident $(, $comment:literal)? { $($fields:tt)* }) =3D> { $( #[doc=3D$comment] )? @@ -149,6 +145,32 @@ fn from(reg: $name) -> u32 { reg.0 } } + + register!(@fields_dispatcher $name { $($fields)* }); + }; + + // Captures the fields and passes them to all the implementers that re= quire field information. + // + // Used to simplify the matching rules for implementers, so they don't= need to match the entire + // complex fields rule even though they only make use of part of it. + (@fields_dispatcher $name:ident { + $($hi:tt:$lo:tt $field:ident as $type:tt + $(?=3D> $try_into_type:ty)? + $(=3D> $into_type:ty)? + $(, $comment:literal)? + ; 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 1d473ceb7b97e18e36246569abf0bb04e7b02060..75b7b742b117240543ad292fc69= e5e1341728174 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -122,16 +122,6 @@ macro_rules! register { #[derive(Clone, Copy, Default)] pub(crate) struct $name(u32); =20 - // TODO[REGA]: display the raw hex value, then the value of all th= e fields. This requires - // matching the fields, which will complexify the syntax considera= bly... - impl ::core::fmt::Debug for $name { - fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::f= mt::Result { - f.debug_tuple(stringify!($name)) - .field(&format_args!("0x{0:x}", &self.0)) - .finish() - } - } - impl ::core::ops::BitOr for $name { type Output =3D Self; =20 @@ -171,6 +161,7 @@ fn from(reg: $name) -> u32 { ; )* }); + register!(@debug $name { $($field;)* }); }; =20 // Defines all the field getter/methods methods for `$name`. @@ -316,6 +307,20 @@ pub(crate) fn [](mut self, value: $to_typ= e) -> Self { ); }; =20 + // Generates the `Debug` implementation for `$name`. + (@debug $name:ident { $($field:ident;)* }) =3D> { + impl ::core::fmt::Debug for $name { + fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::f= mt::Result { + f.debug_struct(stringify!($name)) + .field("", &format_args!("{:#x}", &self.0)) + $( + .field(stringify!($field), &self.$field()) + )* + .finish() + } + } + }; + // Generates the IO accessors for a fixed offset register. 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 75b7b742b117240543ad292fc69e5e1341728174..97895800ff7031d287b3bbd03a0= 0b1ca71014aa8 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -112,14 +112,14 @@ macro_rules! register { =20 // All rules below are helpers. =20 - // Defines the wrapper `$name` type, as well as its relevant implement= ations (`Debug`, `BitOr`, - // and conversion to the value type) and field accessor methods. + // Defines the wrapper `$name` type, as well as its relevant implement= ations (`Debug`, + // `Default`, `BitOr`, and conversion to the value type) and field acc= essor methods. (@core $name:ident $(, $comment:literal)? { $($fields:tt)* }) =3D> { $( #[doc=3D$comment] )? #[repr(transparent)] - #[derive(Clone, Copy, Default)] + #[derive(Clone, Copy)] pub(crate) struct $name(u32); =20 impl ::core::ops::BitOr for $name { @@ -162,6 +162,7 @@ fn from(reg: $name) -> u32 { )* }); register!(@debug $name { $($field;)* }); + register!(@default $name { $($field;)* }); }; =20 // Defines all the field getter/methods methods for `$name`. @@ -321,6 +322,25 @@ fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> := :core::fmt::Result { } }; =20 + // Generates the `Default` implementation for `$name`. + (@default $name:ident { $($field:ident;)* }) =3D> { + /// Returns a value for the register where all fields are set to t= heir default value. + impl ::core::default::Default for $name { + fn default() -> Self { + #[allow(unused_mut)] + let mut value =3D Self(Default::default()); + + ::kernel::macros::paste!( + $( + value.[](Default::default()); + )* + ); + + value + } + } + }; + // Generates the IO accessors for a fixed offset register. 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This can be confusing as the matching rules are very similar. Since all call sites know which version they want to call, split @io into @io_fixed and @io_relative to remove any ambiguity. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 97895800ff7031d287b3bbd03a00b1ca71014aa8..1b2074e38381f9918c48691301e= 5a6f62861501f 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -89,25 +89,25 @@ macro_rules! register { // Creates a register at a fixed offset of the MMIO space. ($name:ident @ $offset:literal $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { register!(@core $name $(, $comment)? { $($fields)* } ); - register!(@io $name @ $offset); + register!(@io_fixed $name @ $offset); }; =20 // Creates an alias register of fixed offset register `alias` with its= own fields. ($name:ident =3D> $alias:ident $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { register!(@core $name $(, $comment)? { $($fields)* } ); - register!(@io $name @ $alias::OFFSET); + register!(@io_fixed $name @ $alias::OFFSET); }; =20 // Creates a register at a relative offset from a base address. ($name:ident @ + $offset:literal $(, $comment:literal)? { $($fields:tt= )* } ) =3D> { register!(@core $name $(, $comment)? { $($fields)* } ); - register!(@io $name @ + $offset); + register!(@io_relative $name @ + $offset); }; =20 // Creates an alias register of relative offset register `alias` with = its own fields. ($name:ident =3D> + $alias:ident $(, $comment:literal)? { $($fields:tt= )* } ) =3D> { register!(@core $name $(, $comment)? { $($fields)* } ); - register!(@io $name @ + $alias::OFFSET); + register!(@io_relative $name @ + $alias::OFFSET); }; =20 // All rules below are helpers. @@ -342,7 +342,7 @@ fn default() -> Self { }; =20 // Generates the IO accessors for a fixed offset register. - (@io $name:ident @ $offset:expr) =3D> { + (@io_fixed $name:ident @ $offset:expr) =3D> { #[allow(dead_code)] impl $name { pub(crate) const OFFSET: usize =3D $offset; @@ -380,7 +380,7 @@ pub(crate) fn alter( }; =20 // Generates the IO accessors for a relative offset register. - (@io $name:ident @ + $offset:literal) =3D> { + (@io_relative $name:ident @ + $offset:literal) =3D> { #[allow(dead_code)] impl $name { pub(crate) const OFFSET: usize =3D $offset; --=20 2.50.0 From nobody Sun Feb 8 18:18:56 2026 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2079.outbound.protection.outlook.com [40.107.94.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 822E2286883; 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 1b2074e38381f9918c48691301e5a6f62861501f..316b67ee1cea7c7fa2894c1778e= 7d43f853bdb19 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -280,7 +280,7 @@ impl $name { #[doc=3D"Returns the value of this field:"] #[doc=3D$comment] )? - #[inline] + #[inline(always)] pub(crate) fn $field(self) -> $res_type { ::kernel::macros::paste!( const MASK: u32 =3D $name::[<$field:upper _MASK>]; @@ -296,7 +296,7 @@ pub(crate) fn $field(self) -> $res_type { #[doc=3D"Sets the value of this field:"] #[doc=3D$comment] )? - #[inline] + #[inline(always)] pub(crate) fn [](mut self, value: $to_type) -> Self { const MASK: u32 =3D $name::[<$field:upper _MASK>]; const SHIFT: u32 =3D $name::[<$field:upper _SHIFT>]; @@ -348,7 +348,7 @@ impl $name { pub(crate) const OFFSET: usize =3D $offset; =20 /// Read the register from its address in `io`. - #[inline] + #[inline(always)] pub(crate) fn read(io: &T) -> Self where T: ::core::ops::Deref>, { @@ -356,7 +356,7 @@ pub(crate) fn read(io: &T) -> Sel= f where } =20 /// Write the value contained in `self` to the register addres= s in `io`. - #[inline] + #[inline(always)] pub(crate) fn write(self, io: &T) where T: ::core::ops::Deref>, { @@ -365,7 +365,7 @@ pub(crate) fn write(self, io: &T)= where =20 /// Read the register from its address in `io` and run `f` on = its value to obtain a new /// value to write back. - #[inline] + #[inline(always)] pub(crate) fn alter( io: &T, f: F, @@ -385,7 +385,7 @@ pub(crate) fn alter( impl $name { pub(crate) const OFFSET: usize =3D $offset; =20 - #[inline] + #[inline(always)] pub(crate) fn read( io: &T, base: usize, @@ -395,7 +395,7 @@ pub(crate) fn read( Self(io.read32(base + $offset)) } =20 - #[inline] + #[inline(always)] pub(crate) fn write( self, io: &T, @@ -406,7 +406,7 @@ pub(crate) fn write( io.write32(self.0, base + $offset) } =20 - #[inline] + #[inline(always)] pub(crate) fn alter( io: &T, base: usize, --=20 2.50.0 From nobody Sun Feb 8 18:18:56 2026 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2066.outbound.protection.outlook.com [40.107.94.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C992E27E7D9; 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Ideally, valid base addresses for a family of registers should be explicitly defined in the code, and could only be used with the relevant registers This patch changes the relative register declaration into this: register!(REGISTER_NAME @ BaseTrait[offset] ... Where `BaseTrait` is the name of a ZST used as a parameter of the `RegisterBase<>` trait to define a trait unique to a class of register. This specialized trait is then implemented for every type that provides a valid base address, enabling said types to be passed as the base address provider for the register's I/O accessor methods. This design thus makes it impossible to pass an unexpected base address to a relative register, and, since the valid bases are all known at compile-time, also guarantees that all I/O accesses are done within the valid bounds of the I/O range. Signed-off-by: Alexandre Courbot --- Documentation/gpu/nova/core/todo.rst | 1 - drivers/gpu/nova-core/falcon.rs | 67 +++++++++------- drivers/gpu/nova-core/falcon/gsp.rs | 12 ++- drivers/gpu/nova-core/falcon/hal/ga102.rs | 14 ++-- drivers/gpu/nova-core/falcon/sec2.rs | 9 ++- drivers/gpu/nova-core/regs.rs | 50 ++++++------ drivers/gpu/nova-core/regs/macros.rs | 126 +++++++++++++++++++++++---= ---- 7 files changed, 182 insertions(+), 97 deletions(-) diff --git a/Documentation/gpu/nova/core/todo.rst b/Documentation/gpu/nova/= core/todo.rst index 894a1e9c3741a43ad4eb76d24a9486862999874e..a1d12c1b289d89251d914fc271b= 7243ced11d487 100644 --- a/Documentation/gpu/nova/core/todo.rst +++ b/Documentation/gpu/nova/core/todo.rst @@ -131,7 +131,6 @@ crate so it can be used by other components as well. =20 Features desired before this happens: =20 -* Relative register with build-time base address validation, * Arrays of registers with build-time index validation, * Make I/O optional I/O (for field values that are not registers), * Support other sizes than `u32`, diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index c2c6f9eb380ab390befe5af1b3c5df260ccd7595..66400d07d186938735f705c116d= 7c7df5fb77fca 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -14,6 +14,7 @@ use crate::driver::Bar0; use crate::gpu::Chipset; use crate::regs; +use crate::regs::macros::RegisterBase; use crate::util; =20 pub(crate) mod gsp; @@ -259,10 +260,16 @@ fn from(value: bool) -> Self { } } =20 -/// Trait defining the parameters of a given Falcon instance. -pub(crate) trait FalconEngine: Sync { - /// Base I/O address for the falcon, relative from which its registers= are accessed. - const BASE: usize; +/// Type used to represent the `PFALCON` registers address base for a give= n falcon engine. +pub(crate) struct PFalconBase(()); + +/// Trait defining the parameters of a given Falcon engine. +/// +/// Each engine provides one base for `PFALCON` and `PFALCON2` registers. = The `ID` constant is used +/// to identify a given Falcon instance with register I/O methods. +pub(crate) trait FalconEngine: Sync + RegisterBase + Sized { + /// Singleton of the engine, used to identify it with register I/O met= hods. + const ID: Self; } =20 /// Represents a portion of the firmware to be loaded into a particular me= mory (e.g. IMEM or DMEM). @@ -328,13 +335,13 @@ pub(crate) fn new( bar: &Bar0, need_riscv: bool, ) -> Result { - let hwcfg1 =3D regs::NV_PFALCON_FALCON_HWCFG1::read(bar, E::BASE); + let hwcfg1 =3D regs::NV_PFALCON_FALCON_HWCFG1::read(bar, &E::ID); // Check that the revision and security model contain valid values. let _ =3D hwcfg1.core_rev()?; let _ =3D hwcfg1.security_model()?; =20 if need_riscv { - let hwcfg2 =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BA= SE); + let hwcfg2 =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, &E::I= D); if !hwcfg2.riscv() { dev_err!( dev, @@ -354,7 +361,7 @@ pub(crate) fn new( fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result { // TIMEOUT: memory scrubbing should complete in less than 20ms. util::wait_on(Delta::from_millis(20), || { - if regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE).mem_scru= bbing_done() { + if regs::NV_PFALCON_FALCON_HWCFG2::read(bar, &E::ID).mem_scrub= bing_done() { Some(()) } else { None @@ -364,12 +371,12 @@ fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Res= ult { =20 /// Reset the falcon engine. fn reset_eng(&self, bar: &Bar0) -> Result { - let _ =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); + let _ =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, &E::ID); =20 // According to OpenRM's `kflcnPreResetWait_GA102` documentation, = HW sometimes does not set // RESET_READY so a non-failing timeout is used. let _ =3D util::wait_on(Delta::from_micros(150), || { - let r =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); + let r =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, &E::ID); if r.reset_ready() { Some(()) } else { @@ -377,13 +384,13 @@ fn reset_eng(&self, bar: &Bar0) -> Result { } }); =20 - regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_rese= t(true)); + regs::NV_PFALCON_FALCON_ENGINE::alter(bar, &E::ID, |v| v.set_reset= (true)); =20 // TODO[DLAY]: replace with udelay() or equivalent once available. // TIMEOUT: falcon engine should not take more than 10us to reset. let _: Result =3D util::wait_on(Delta::from_micros(10), || None); =20 - regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_rese= t(false)); + regs::NV_PFALCON_FALCON_ENGINE::alter(bar, &E::ID, |v| v.set_reset= (false)); =20 self.reset_wait_mem_scrubbing(bar)?; =20 @@ -398,7 +405,7 @@ pub(crate) fn reset(&self, bar: &Bar0) -> Result { =20 regs::NV_PFALCON_FALCON_RM::default() .set_value(regs::NV_PMC_BOOT_0::read(bar).into()) - .write(bar, E::BASE); + .write(bar, &E::ID); =20 Ok(()) } @@ -449,10 +456,10 @@ fn dma_wr>( =20 regs::NV_PFALCON_FALCON_DMATRFBASE::default() .set_base((dma_start >> 8) as u32) - .write(bar, E::BASE); + .write(bar, &E::ID); regs::NV_PFALCON_FALCON_DMATRFBASE1::default() .set_base((dma_start >> 40) as u16) - .write(bar, E::BASE); + .write(bar, &E::ID); =20 let cmd =3D regs::NV_PFALCON_FALCON_DMATRFCMD::default() .set_size(DmaTrfCmdSize::Size256B) @@ -463,17 +470,17 @@ fn dma_wr>( // Perform a transfer of size `DMA_LEN`. regs::NV_PFALCON_FALCON_DMATRFMOFFS::default() .set_offs(load_offsets.dst_start + pos) - .write(bar, E::BASE); + .write(bar, &E::ID); regs::NV_PFALCON_FALCON_DMATRFFBOFFS::default() .set_offs(src_start + pos) - .write(bar, E::BASE); - cmd.write(bar, E::BASE); + .write(bar, &E::ID); + cmd.write(bar, &E::ID); =20 // Wait for the transfer to complete. // TIMEOUT: arbitrarily large value, no DMA transfer to the fa= lcon's small memories // should ever take that long. util::wait_on(Delta::from_secs(2), || { - let r =3D regs::NV_PFALCON_FALCON_DMATRFCMD::read(bar, E::= BASE); + let r =3D regs::NV_PFALCON_FALCON_DMATRFCMD::read(bar, &E:= :ID); if r.idle() { Some(()) } else { @@ -487,9 +494,9 @@ fn dma_wr>( =20 /// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the= falcon to run it. pub(crate) fn dma_load>(&self, bar: &B= ar0, fw: &F) -> Result { - regs::NV_PFALCON_FBIF_CTL::alter(bar, E::BASE, |v| v.set_allow_phy= s_no_ctx(true)); - regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, E::BASE); - regs::NV_PFALCON_FBIF_TRANSCFG::alter(bar, E::BASE, |v| { + regs::NV_PFALCON_FBIF_CTL::alter(bar, &E::ID, |v| v.set_allow_phys= _no_ctx(true)); + regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, &E::ID); + regs::NV_PFALCON_FBIF_TRANSCFG::alter(bar, &E::ID, |v| { v.set_target(FalconFbifTarget::CoherentSysmem) .set_mem_type(FalconFbifMemType::Physical) }); @@ -502,7 +509,7 @@ pub(crate) fn dma_load>= (&self, bar: &Bar0, fw: &F) // Set `BootVec` to start of non-secure code. regs::NV_PFALCON_FALCON_BOOTVEC::default() .set_value(fw.boot_addr()) - .write(bar, E::BASE); + .write(bar, &E::ID); =20 Ok(()) } @@ -523,27 +530,27 @@ pub(crate) fn boot( if let Some(mbox0) =3D mbox0 { regs::NV_PFALCON_FALCON_MAILBOX0::default() .set_value(mbox0) - .write(bar, E::BASE); + .write(bar, &E::ID); } =20 if let Some(mbox1) =3D mbox1 { regs::NV_PFALCON_FALCON_MAILBOX1::default() .set_value(mbox1) - .write(bar, E::BASE); + .write(bar, &E::ID); } =20 - match regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE).alias_en(= ) { + match regs::NV_PFALCON_FALCON_CPUCTL::read(bar, &E::ID).alias_en()= { true =3D> regs::NV_PFALCON_FALCON_CPUCTL_ALIAS::default() .set_startcpu(true) - .write(bar, E::BASE), + .write(bar, &E::ID), false =3D> regs::NV_PFALCON_FALCON_CPUCTL::default() .set_startcpu(true) - .write(bar, E::BASE), + .write(bar, &E::ID), } =20 // TIMEOUT: arbitrarily large value, firmwares should complete in = less than 2 seconds. util::wait_on(Delta::from_secs(2), || { - let r =3D regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE); + let r =3D regs::NV_PFALCON_FALCON_CPUCTL::read(bar, &E::ID); if r.halted() { Some(()) } else { @@ -552,8 +559,8 @@ pub(crate) fn boot( })?; =20 let (mbox0, mbox1) =3D ( - regs::NV_PFALCON_FALCON_MAILBOX0::read(bar, E::BASE).value(), - regs::NV_PFALCON_FALCON_MAILBOX1::read(bar, E::BASE).value(), + regs::NV_PFALCON_FALCON_MAILBOX0::read(bar, &E::ID).value(), + regs::NV_PFALCON_FALCON_MAILBOX1::read(bar, &E::ID).value(), ); =20 Ok((mbox0, mbox1)) diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/fa= lcon/gsp.rs index d622e9a64470932af0b48032be5a1d4b518bf4a7..0db9f94036a6a7ced5a461aec2c= ff2ce246a5e0e 100644 --- a/drivers/gpu/nova-core/falcon/gsp.rs +++ b/drivers/gpu/nova-core/falcon/gsp.rs @@ -2,23 +2,27 @@ =20 use crate::{ driver::Bar0, - falcon::{Falcon, FalconEngine}, - regs, + falcon::{Falcon, FalconEngine, PFalconBase}, + regs::{self, macros::RegisterBase}, }; =20 /// Type specifying the `Gsp` falcon engine. Cannot be instantiated. pub(crate) struct Gsp(()); =20 -impl FalconEngine for Gsp { +impl RegisterBase for Gsp { const BASE: usize =3D 0x00110000; } =20 +impl FalconEngine for Gsp { + const ID: Self =3D Gsp(()); +} + impl Falcon { /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to /// allow GSP to signal CPU for processing new messages in message que= ue. pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { regs::NV_PFALCON_FALCON_IRQSCLR::default() .set_swgen0(true) - .write(bar, Gsp::BASE); + .write(bar, &Gsp::ID); } } diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-c= ore/falcon/hal/ga102.rs index 52c33d3f22a8e920742b45940c346c47fdc70e93..3fdacd19322dd122eb00e245de4= be8d1edd61a5f 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -16,15 +16,15 @@ use super::FalconHal; =20 fn select_core_ga102(bar: &Bar0) -> Result { - let bcr_ctrl =3D regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE); + let bcr_ctrl =3D regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, &E::ID); if bcr_ctrl.core_select() !=3D PeregrineCoreSelect::Falcon { regs::NV_PRISCV_RISCV_BCR_CTRL::default() .set_core_select(PeregrineCoreSelect::Falcon) - .write(bar, E::BASE); + .write(bar, &E::ID); =20 // TIMEOUT: falcon core should take less than 10ms to report being= enabled. util::wait_on(Delta::from_millis(10), || { - let r =3D regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE); + let r =3D regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, &E::ID); if r.valid() { Some(()) } else { @@ -76,16 +76,16 @@ fn signature_reg_fuse_version_ga102( fn program_brom_ga102(bar: &Bar0, params: &FalconBromPara= ms) -> Result { regs::NV_PFALCON2_FALCON_BROM_PARAADDR::default() .set_value(params.pkc_data_offset) - .write(bar, E::BASE); + .write(bar, &E::ID); regs::NV_PFALCON2_FALCON_BROM_ENGIDMASK::default() .set_value(u32::from(params.engine_id_mask)) - .write(bar, E::BASE); + .write(bar, &E::ID); regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::default() .set_ucode_id(params.ucode_id) - .write(bar, E::BASE); + .write(bar, &E::ID); regs::NV_PFALCON2_FALCON_MOD_SEL::default() .set_algo(FalconModSelAlgo::Rsa3k) - .write(bar, E::BASE); + .write(bar, &E::ID); =20 Ok(()) } diff --git a/drivers/gpu/nova-core/falcon/sec2.rs b/drivers/gpu/nova-core/f= alcon/sec2.rs index 5147d9e2a7fe859210727504688d84cca4de991b..dbc486a712ffce30efa3a4264b0= 757974962302e 100644 --- a/drivers/gpu/nova-core/falcon/sec2.rs +++ b/drivers/gpu/nova-core/falcon/sec2.rs @@ -1,10 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use crate::falcon::FalconEngine; +use crate::falcon::{FalconEngine, PFalconBase}; +use crate::regs::macros::RegisterBase; =20 /// Type specifying the `Sec2` falcon engine. Cannot be instantiated. pub(crate) struct Sec2(()); =20 -impl FalconEngine for Sec2 { +impl RegisterBase for Sec2 { const BASE: usize =3D 0x00840000; } + +impl FalconEngine for Sec2 { + const ID: Self =3D Sec2(()); +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index e8b8aabce3f36abe6a7fba3e11f677e36baa3897..4e047fc4947b6dc09dbd34e26ee= da1ff14dff4ad 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -5,11 +5,11 @@ #![allow(non_camel_case_types)] =20 #[macro_use] -mod macros; +pub(crate) mod macros; =20 use crate::falcon::{ DmaTrfCmdSize, FalconCoreRev, FalconCoreRevSubversion, FalconFbifMemTy= pe, FalconFbifTarget, - FalconModSelAlgo, FalconSecurityModel, PeregrineCoreSelect, + FalconModSelAlgo, FalconSecurityModel, PFalconBase, PeregrineCoreSelec= t, }; use crate::gpu::{Architecture, Chipset}; use kernel::prelude::*; @@ -181,24 +181,24 @@ pub(crate) fn vga_workspace_addr(self) -> Option= { =20 /* PFALCON */ =20 -register!(NV_PFALCON_FALCON_IRQSCLR @ +0x00000004 { +register!(NV_PFALCON_FALCON_IRQSCLR @ PFalconBase[0x00000004] { 4:4 halt as bool; 6:6 swgen0 as bool; }); =20 -register!(NV_PFALCON_FALCON_MAILBOX0 @ +0x00000040 { +register!(NV_PFALCON_FALCON_MAILBOX0 @ PFalconBase[0x00000040] { 31:0 value as u32; }); =20 -register!(NV_PFALCON_FALCON_MAILBOX1 @ +0x00000044 { +register!(NV_PFALCON_FALCON_MAILBOX1 @ PFalconBase[0x00000044] { 31:0 value as u32; }); =20 -register!(NV_PFALCON_FALCON_RM @ +0x00000084 { +register!(NV_PFALCON_FALCON_RM @ PFalconBase[0x00000084] { 31:0 value as u32; }); =20 -register!(NV_PFALCON_FALCON_HWCFG2 @ +0x000000f4 { +register!(NV_PFALCON_FALCON_HWCFG2 @ PFalconBase[0x000000f4] { 10:10 riscv as bool; 12:12 mem_scrubbing as bool, "Set to 0 after memory scrubbing is com= pleted"; 31:31 reset_ready as bool, "Signal indicating that reset is complete= d (GA102+)"; @@ -211,17 +211,17 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } =20 -register!(NV_PFALCON_FALCON_CPUCTL @ +0x00000100 { +register!(NV_PFALCON_FALCON_CPUCTL @ PFalconBase[0x00000100] { 1:1 startcpu as bool; 4:4 halted as bool; 6:6 alias_en as bool; }); =20 -register!(NV_PFALCON_FALCON_BOOTVEC @ +0x00000104 { +register!(NV_PFALCON_FALCON_BOOTVEC @ PFalconBase[0x00000104] { 31:0 value as u32; }); =20 -register!(NV_PFALCON_FALCON_DMACTL @ +0x0000010c { +register!(NV_PFALCON_FALCON_DMACTL @ PFalconBase[0x0000010c] { 0:0 require_ctx as bool; 1:1 dmem_scrubbing as bool; 2:2 imem_scrubbing as bool; @@ -229,15 +229,15 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 7:7 secure_stat as bool; }); =20 -register!(NV_PFALCON_FALCON_DMATRFBASE @ +0x00000110 { +register!(NV_PFALCON_FALCON_DMATRFBASE @ PFalconBase[0x00000110] { 31:0 base as u32; }); =20 -register!(NV_PFALCON_FALCON_DMATRFMOFFS @ +0x00000114 { +register!(NV_PFALCON_FALCON_DMATRFMOFFS @ PFalconBase[0x00000114] { 23:0 offs as u32; }); =20 -register!(NV_PFALCON_FALCON_DMATRFCMD @ +0x00000118 { +register!(NV_PFALCON_FALCON_DMATRFCMD @ PFalconBase[0x00000118] { 0:0 full as bool; 1:1 idle as bool; 3:2 sec as u8; @@ -248,60 +248,60 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 16:16 set_dmtag as u8; }); =20 -register!(NV_PFALCON_FALCON_DMATRFFBOFFS @ +0x0000011c { +register!(NV_PFALCON_FALCON_DMATRFFBOFFS @ PFalconBase[0x0000011c] { 31:0 offs as u32; }); =20 -register!(NV_PFALCON_FALCON_DMATRFBASE1 @ +0x00000128 { +register!(NV_PFALCON_FALCON_DMATRFBASE1 @ PFalconBase[0x00000128] { 8:0 base as u16; }); =20 -register!(NV_PFALCON_FALCON_HWCFG1 @ +0x0000012c { +register!(NV_PFALCON_FALCON_HWCFG1 @ PFalconBase[0x0000012c] { 3:0 core_rev as u8 ?=3D> FalconCoreRev, "Core revision"; 5:4 security_model as u8 ?=3D> FalconSecurityModel, "Security mode= l"; 7:6 core_rev_subversion as u8 ?=3D> FalconCoreRevSubversion, "Core= revision subversion"; }); =20 -register!(NV_PFALCON_FALCON_CPUCTL_ALIAS @ +0x00000130 { +register!(NV_PFALCON_FALCON_CPUCTL_ALIAS @ PFalconBase[0x00000130] { 1:1 startcpu as bool; }); =20 // Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` d= epending on the falcon // instance. -register!(NV_PFALCON_FALCON_ENGINE @ +0x000003c0 { +register!(NV_PFALCON_FALCON_ENGINE @ PFalconBase[0x000003c0] { 0:0 reset as bool; }); =20 // TODO[REGA]: this is an array of registers. -register!(NV_PFALCON_FBIF_TRANSCFG @ +0x00000600 { +register!(NV_PFALCON_FBIF_TRANSCFG @ PFalconBase[0x00000600] { 1:0 target as u8 ?=3D> FalconFbifTarget; 2:2 mem_type as bool =3D> FalconFbifMemType; }); =20 -register!(NV_PFALCON_FBIF_CTL @ +0x00000624 { +register!(NV_PFALCON_FBIF_CTL @ PFalconBase[0x00000624] { 7:7 allow_phys_no_ctx as bool; }); =20 -register!(NV_PFALCON2_FALCON_MOD_SEL @ +0x00001180 { +register!(NV_PFALCON2_FALCON_MOD_SEL @ PFalconBase[0x00001180] { 7:0 algo as u8 ?=3D> FalconModSelAlgo; }); =20 -register!(NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID @ +0x00001198 { +register!(NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID @ PFalconBase[0x00001198] { 7:0 ucode_id as u8; }); =20 -register!(NV_PFALCON2_FALCON_BROM_ENGIDMASK @ +0x0000119c { +register!(NV_PFALCON2_FALCON_BROM_ENGIDMASK @ PFalconBase[0x0000119c] { 31:0 value as u32; }); =20 // TODO[REGA]: this is an array of registers. -register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ +0x00001210 { +register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ PFalconBase[0x00001210] { 31:0 value as u32; }); =20 /* PRISCV */ =20 -register!(NV_PRISCV_RISCV_BCR_CTRL @ +0x00001668 { +register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] { 0:0 valid as bool; 4:4 core_select as bool =3D> PeregrineCoreSelect; 8:8 br_fetch as bool; diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 316b67ee1cea7c7fa2894c1778e7d43f853bdb19..1f0375d20b5f4328d496a14120e= ea8a54123f8cc 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -10,6 +10,16 @@ //! dedicated type for each register. Each such type comes with its own fi= eld accessors that can //! return an error if a field's value is invalid. =20 +/// Trait providing a base address to be added to the offset of a relative= register to obtain +/// its actual offset. +/// +/// The `T` generic argument is used to distinguish which base to use, in = case a type provides +/// several bases. It is given to the `register!` macro to restrict the us= e of the register to +/// implementors of this particular variant. +pub(crate) trait RegisterBase { + const BASE: usize; +} + /// Defines a dedicated type for a register with an absolute offset, inclu= ding getter and setter /// methods for its fields and methods to read and write it from an `Io` r= egion. /// @@ -56,20 +66,6 @@ /// The documentation strings are optional. If present, they will be added= to the type's /// definition, or the field getter and setter methods they are attached t= o. /// -/// Putting a `+` before the address of the register makes it relative to = a base: the `read` and -/// `write` methods take a `base` argument that is added to the specified = address before access: -/// -/// ```no_run -/// register!(CPU_CTL @ +0x0000010, "CPU core control" { -/// 0:0 start as bool, "Start the CPU core"; -/// }); -/// -/// // Flip the `start` switch for the CPU core which base address is at `= CPU_BASE`. -/// let cpuctl =3D CPU_CTL::read(&bar, CPU_BASE); -/// pr_info!("CPU CTL: {:#x}", cpuctl); -/// cpuctl.set_start(true).write(&bar, CPU_BASE); -/// ``` -/// /// It is also possible to create a alias register by using the `=3D> ALIA= S` syntax. This is useful /// for cases where a register's interpretation depends on the context: /// @@ -85,6 +81,57 @@ /// /// In this example, `SCRATCH_0_BOOT_STATUS` uses the same I/O address as = `SCRATCH_0`, while also /// providing its own `completed` field. +/// +/// ## Relative registers +/// +/// A register can be defined as being accessible from a fixed offset of a= provided base. For this, +/// use the `Base[Offset]` syntax when specifying the register's address. +/// +/// `Base` is an arbitrary type (typically a ZST) to be used as a generic = parameter of the +/// `RegisterBase` to provide the base as a constant, i.e. each type provi= ding a base for this +/// register needs to implement `RegisterBase`. +/// +/// The`read`, `write` and `alter` methods of relative registers take an e= xtra `base` argument that +/// is used to resolve the final address of the register. +/// +/// ```no_run +/// // Type used as parameter of `RegisterBase` to specify the base. +/// pub(crate) struct CpuCtlBase; +/// +/// // ZST describing `CPU0`. +/// struct Cpu0; +/// impl RegisterBase for Cpu0 { +/// const BASE: usize =3D 0xf00; +/// } +/// // Singleton of `CPU0` used to identify it. +/// const CPU0: Cpu0 =3D Cpu0; +/// +/// // ZST describing `CPU1`. +/// struct Cpu1; +/// impl RegisterBase for Cpu1 { +/// const BASE: usize =3D 0x1f00; +/// } +/// // Singleton of `CPU1` used to identify it. +/// const CPU1: Cpu1 =3D Cpu1; +/// +/// register!(CPU_CTL @ CpuCtlBase[0x10], "CPU core control" { +/// 0:0 start as bool, "Start the CPU core"; +/// }); +/// +/// // Start `CPU0`. +/// CPU_CTL::alter(bar, &CPU0, |r| r.set_start(true)); +/// +/// // Start `CPU1`. +/// CPU_CTL::alter(bar, &CPU1, |r| r.set_start(true)); +/// +/// // Alias of a relative register. +/// register!(CPU_CTL_ALIAS =3D> CpuCtlBase[CPU_CTL], "Alias to CPU core c= ontrol" { +/// 1:1 alias_start as bool, "Start the aliased CPU core"; +/// }); +/// +/// // Start the aliased `CPU0`. +/// CPU_CTL_ALIAS::alter(bar, &CPU0, |r| r.set_alias_start(true)); +/// ``` macro_rules! register { // Creates a register at a fixed offset of the MMIO space. ($name:ident @ $offset:literal $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { @@ -98,16 +145,16 @@ macro_rules! register { register!(@io_fixed $name @ $alias::OFFSET); }; =20 - // Creates a register at a relative offset from a base address. - ($name:ident @ + $offset:literal $(, $comment:literal)? { $($fields:tt= )* } ) =3D> { + // Creates a register at a relative offset from a base address provide= r. + ($name:ident @ $base:ty [ $offset:literal ] $(, $comment:literal)? { $= ($fields:tt)* } ) =3D> { register!(@core $name $(, $comment)? { $($fields)* } ); - register!(@io_relative $name @ + $offset); + register!(@io_relative $name @ $base [ $offset ]); }; =20 // Creates an alias register of relative offset register `alias` with = its own fields. - ($name:ident =3D> + $alias:ident $(, $comment:literal)? { $($fields:tt= )* } ) =3D> { + ($name:ident =3D> $base:ty [ $alias:ident ] $(, $comment:literal)? { $= ($fields:tt)* }) =3D> { register!(@core $name $(, $comment)? { $($fields)* } ); - register!(@io_relative $name @ + $alias::OFFSET); + register!(@io_relative $name @ $base [ $alias::OFFSET ]); }; =20 // All rules below are helpers. @@ -380,39 +427,62 @@ pub(crate) fn alter( }; =20 // Generates the IO accessors for a relative offset register. - (@io_relative $name:ident @ + $offset:literal) =3D> { + (@io_relative $name:ident @ $base:ty [ $offset:expr ]) =3D> { #[allow(dead_code)] impl $name { pub(crate) const OFFSET: usize =3D $offset; =20 + /// Read the register from `io`, using the base address provid= ed by `base` and adding + /// the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, - base: usize, + #[allow(unused_variables)] + base: &B, ) -> Self where T: ::core::ops::Deref>, + B: crate::regs::macros::RegisterBase<$base>, { - Self(io.read32(base + $offset)) + const OFFSET: usize =3D $name::OFFSET; + + let value =3D io.read32( + >::BASE = + OFFSET + ); + + Self(value) } =20 + /// Write the value contained in `self` to `io`, using the bas= e address provided by + /// `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, - base: usize, + #[allow(unused_variables)] + base: &B, ) where T: ::core::ops::Deref>, + B: crate::regs::macros::RegisterBase<$base>, { - io.write32(self.0, base + $offset) + const OFFSET: usize =3D $name::OFFSET; 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So far we assumed that `PFALCON2` was located at `PFALCON + 0x1000` because that is the case of most engines, but there are exceptions (NVDEC uses `0x1c00`). Fix this shortcoming by leveraging the redesigned relative registers definitions to assign a distinct `PFalcon2Base` base address to each falcon engine. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 7 ++++++- drivers/gpu/nova-core/falcon/gsp.rs | 6 +++++- drivers/gpu/nova-core/falcon/sec2.rs | 6 +++++- drivers/gpu/nova-core/regs.rs | 12 +++++++----- 4 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 66400d07d186938735f705c116d7c7df5fb77fca..23a4ff591c8db8d4600ec43dfaa= 42233cbf65c0e 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -263,11 +263,16 @@ fn from(value: bool) -> Self { /// Type used to represent the `PFALCON` registers address base for a give= n falcon engine. pub(crate) struct PFalconBase(()); =20 +/// Type used to represent the `PFALCON2` registers address base for a giv= en falcon engine. +pub(crate) struct PFalcon2Base(()); + /// Trait defining the parameters of a given Falcon engine. /// /// Each engine provides one base for `PFALCON` and `PFALCON2` registers. = The `ID` constant is used /// to identify a given Falcon instance with register I/O methods. -pub(crate) trait FalconEngine: Sync + RegisterBase + Sized { +pub(crate) trait FalconEngine: + Sync + RegisterBase + RegisterBase + Sized +{ /// Singleton of the engine, used to identify it with register I/O met= hods. const ID: Self; } diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/fa= lcon/gsp.rs index 0db9f94036a6a7ced5a461aec2cff2ce246a5e0e..f17599cb49fa1e5077a554dc14b= 3715aa62a4ebd 100644 --- a/drivers/gpu/nova-core/falcon/gsp.rs +++ b/drivers/gpu/nova-core/falcon/gsp.rs @@ -2,7 +2,7 @@ =20 use crate::{ driver::Bar0, - falcon::{Falcon, FalconEngine, PFalconBase}, + falcon::{Falcon, FalconEngine, PFalcon2Base, PFalconBase}, regs::{self, macros::RegisterBase}, }; =20 @@ -13,6 +13,10 @@ impl RegisterBase for Gsp { const BASE: usize =3D 0x00110000; } =20 +impl RegisterBase for Gsp { + const BASE: usize =3D 0x00111000; +} + impl FalconEngine for Gsp { const ID: Self =3D Gsp(()); } diff --git a/drivers/gpu/nova-core/falcon/sec2.rs b/drivers/gpu/nova-core/f= alcon/sec2.rs index dbc486a712ffce30efa3a4264b0757974962302e..815786c8480db6cb74541d7ab57= 4112baeb816fe 100644 --- a/drivers/gpu/nova-core/falcon/sec2.rs +++ b/drivers/gpu/nova-core/falcon/sec2.rs @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use crate::falcon::{FalconEngine, PFalconBase}; +use crate::falcon::{FalconEngine, PFalcon2Base, PFalconBase}; use crate::regs::macros::RegisterBase; =20 /// Type specifying the `Sec2` falcon engine. Cannot be instantiated. @@ -10,6 +10,10 @@ impl RegisterBase for Sec2 { const BASE: usize =3D 0x00840000; } =20 +impl RegisterBase for Sec2 { + const BASE: usize =3D 0x00841000; +} + impl FalconEngine for Sec2 { const ID: Self =3D Sec2(()); } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 4e047fc4947b6dc09dbd34e26eeda1ff14dff4ad..e6382c116adf699ab24de097c15= ddca08017b36d 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -9,7 +9,7 @@ =20 use crate::falcon::{ DmaTrfCmdSize, FalconCoreRev, FalconCoreRevSubversion, FalconFbifMemTy= pe, FalconFbifTarget, - FalconModSelAlgo, FalconSecurityModel, PFalconBase, PeregrineCoreSelec= t, + FalconModSelAlgo, FalconSecurityModel, PFalcon2Base, PFalconBase, Pere= grineCoreSelect, }; use crate::gpu::{Architecture, Chipset}; use kernel::prelude::*; @@ -282,20 +282,22 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 7:7 allow_phys_no_ctx as bool; }); =20 -register!(NV_PFALCON2_FALCON_MOD_SEL @ PFalconBase[0x00001180] { +/* PFALCON2 */ + +register!(NV_PFALCON2_FALCON_MOD_SEL @ PFalcon2Base[0x00000180] { 7:0 algo as u8 ?=3D> FalconModSelAlgo; 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Thus, add a way to simply and safely declare such a layout using the register!() macro. Build-time bound-checking is effective for array accesses performed with a constant. For cases where the index cannot be known at compile time, `try_` variants of the accessors are also made available that return `EINVAL` if the access is out-of-bounds. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gpu.rs | 2 +- drivers/gpu/nova-core/regs.rs | 15 +-- drivers/gpu/nova-core/regs/macros.rs | 191 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 200 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 8e32af16b669ca773e63e184d34c3e0427bc9b76..d4a0dc2e9a6a3cef368e2f57727= 1f659f0f2c71b 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -221,7 +221,7 @@ fn run_fwsec_frts( fwsec_frts.run(dev, falcon, bar)?; =20 // SCRATCH_E contains the error code for FWSEC-FRTS. - let frts_status =3D regs::NV_PBUS_SW_SCRATCH_0E::read(bar).frts_er= r_code(); + let frts_status =3D regs::NV_PBUS_SW_SCRATCH_0E_FRTS_ERR::read(bar= ).frts_err_code(); if frts_status !=3D 0 { dev_err!( dev, diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index e6382c116adf699ab24de097c15ddca08017b36d..95b2c0d6b88f3b04af96f07c055= c539870649937 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -44,8 +44,10 @@ pub(crate) fn chipset(self) -> Result { =20 /* PBUS */ =20 -// TODO[REGA]: this is an array of registers. -register!(NV_PBUS_SW_SCRATCH_0E@0x00001438 { +register!(NV_PBUS_SW_SCRATCH @ 0x00001400[64] {}); + +register!(NV_PBUS_SW_SCRATCH_0E_FRTS_ERR =3D> NV_PBUS_SW_SCRATCH[0xe], + "scratch register 0xe used as FRTS firmware error code" { 31:16 frts_err_code as u16; }); =20 @@ -110,13 +112,12 @@ pub(crate) fn higher_bound(self) -> u64 { 0:0 read_protection_level0 as bool, "Set after FWSEC lowers its pr= otection level"; }); =20 -// TODO[REGA]: This is an array of registers. -register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05 @ 0x00118234 { - 31:0 value as u32; -}); +// OpenRM defines this as a register array, but doesn't specify its size a= nd only uses its first +// element. Be conservative until we know the actual size or need to use m= ore registers. +register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05 @ 0x00118234[1] {}); =20 register!( - NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT =3D> NV_PGC6_AON_SECURE= _SCRATCH_GROUP_05, + NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT =3D> NV_PGC6_AON_SECURE= _SCRATCH_GROUP_05[0], "Scratch group 05 register 0 used as GFW boot progress indicator" { 7:0 progress as u8, "Progress of GFW boot (0xff means completed= )"; } diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 1f0375d20b5f4328d496a14120eea8a54123f8cc..af432f0535d2944fa4609f4a44c= 98a0b1394a2c0 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -132,6 +132,53 @@ pub(crate) trait RegisterBase { /// // Start the aliased `CPU0`. /// CPU_CTL_ALIAS::alter(bar, &CPU0, |r| r.set_alias_start(true)); /// ``` +/// +/// ## Arrays of registers +/// +/// Some I/O areas contain consecutive values that can be interpreted in t= he same way. These areas +/// can be defined as an array of identical registers, allowing them to be= accessed by index with +/// compile-time or runtime bound checking. Simply define their address as= `Address[Size]`, and add +/// an `idx` parameter to their `read`, `write` and `alter` methods: +/// +/// ```no_run +/// # fn no_run() -> Result<(), Error> { +/// # fn get_scratch_idx() -> usize { +/// # 0x15 +/// # } +/// register!(SCRATCH @ 0x00000c00[64], "Scratch registers" { +/// 31:0 value as u32; +/// }); +/// +/// let scratch_0 =3D SCRATCH::read(bar, 0).value(); +/// let scratch_15 =3D SCRATCH::read(bar, 15).value(); +/// // This won't build. +/// // let scratch_128 =3D SCRATCH::read(bar, 128).value(); +/// +/// // Runtime-obtained array index. +/// let scratch_idx =3D get_scratch_idx(); +/// // Access on a runtime index returns an error if it is out-of-bounds. +/// let some_scratch =3D SCRATCH::try_read(bar, scratch_idx)?.value(); +/// +/// // Alias to a particular register in an array. +/// // `SCRATCH[8]` is used to convey the firmware exit code. +/// register!(FIRMWARE_STATUS =3D> SCRATCH[8], "Firmware exit status code"= { +/// 7:0 status as u8; +/// }); +/// +/// let status =3D FIRMWARE_STATUS::read(bar).status(); +/// +/// // Non-contiguous register arrays can be defined by adding a stride pa= rameter. +/// // Here, each of the 16 registers of the array are separated by 8 byte= s, meaning that the +/// // registers of the two declarations below are interleaved. +/// register!(SCRATCH_INTERLEAVED_0 @ 0x00000d00[16 ; 8], "Scratch registe= rs bank 0" { +/// 31:0 value as u32; +/// }); +/// register!(SCRATCH_INTERLEAVED_1 @ 0x00000d04[16 ; 8], "Scratch registe= rs bank 1" { +/// 31:0 value as u32; +/// }); +/// # Ok(()) +/// # } +/// ``` macro_rules! register { // Creates a register at a fixed offset of the MMIO space. ($name:ident @ $offset:literal $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { @@ -157,6 +204,35 @@ macro_rules! register { register!(@io_relative $name @ $base [ $alias::OFFSET ]); }; =20 + // Creates an array of registers at a fixed offset of the MMIO space. + ( + $name:ident @ $offset:literal [ $size:expr ; $stride:expr ] $(, $c= omment:literal)? { + $($fields:tt)* + } + ) =3D> { + static_assert!(::core::mem::size_of::() <=3D $stride); + register!(@core $name $(, $comment)? { $($fields)* } ); + register!(@io_array $name @ $offset [ $size ; $stride ]); + }; + + // Shortcut for contiguous array of registers (stride =3D=3D size of e= lement). + ( + $name:ident @ $offset:literal [ $size:expr ] $(, $comment:literal)= ? { + $($fields:tt)* + } + ) =3D> { + register!($name @ $offset [ $size ; ::core::mem::size_of::() = ] $(, $comment)? { + $($fields)* + } ); + }; + + // Creates an alias of register `idx` of array of registers `alias` wi= th its own fields. + ($name:ident =3D> $alias:ident [ $idx:expr ] $(, $comment:literal)? { = $($fields:tt)* }) =3D> { + static_assert!($idx < $alias::SIZE); + register!(@core $name $(, $comment)? { $($fields)* } ); + register!(@io_fixed $name @ $alias::OFFSET + $idx * $alias::STRIDE= ); + }; + // All rules below are helpers. =20 // Defines the wrapper `$name` type, as well as its relevant implement= ations (`Debug`, @@ -490,4 +566,119 @@ pub(crate) fn alter( } } }; + + // Generates the IO accessors for an array of registers. + (@io_array $name:ident @ $offset:literal [ $size:expr ; $stride:expr ]= ) =3D> { + #[allow(dead_code)] + impl $name { + pub(crate) const OFFSET: usize =3D $offset; + pub(crate) const SIZE: usize =3D $size; + pub(crate) const STRIDE: usize =3D $stride; + + /// Read the array register at index `idx` from its address in= `io`. + #[inline(always)] + pub(crate) fn read( + io: &T, + idx: usize, + ) -> Self where + T: ::core::ops::Deref>, + { + build_assert!(idx < Self::SIZE); + + let offset =3D Self::OFFSET + (idx * Self::STRIDE); + let value =3D io.read32(offset); + + Self(value) + } + + /// Write the value contained in `self` to the array register = with index `idx` in `io`. + #[inline(always)] + pub(crate) fn write( + self, + io: &T, + idx: usize + ) where + T: ::core::ops::Deref>, + { + build_assert!(idx < Self::SIZE); + + let offset =3D Self::OFFSET + (idx * Self::STRIDE); + + io.write32(self.0, offset); + } + + /// Read the array register at index `idx` in `io` and run `f`= on its value to obtain a + /// new value to write back. + #[inline(always)] + pub(crate) fn alter( + io: &T, + idx: usize, + f: F, + ) where + T: ::core::ops::Deref>, + F: ::core::ops::FnOnce(Self) -> Self, + { + let reg =3D f(Self::read(io, idx)); + reg.write(io, idx); + } + + /// Read the array register at index `idx` from its address in= `io`. + /// + /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the + /// access was out-of-bounds. + #[inline(always)] + pub(crate) fn try_read( + io: &T, + idx: usize, + ) -> ::kernel::error::Result where + T: ::core::ops::Deref>, + { + if idx < Self::SIZE { + Ok(Self::read(io, idx)) + } else { + Err(EINVAL) + } + } + + /// Write the value contained in `self` to the array register = with index `idx` in `io`. + /// + /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the + /// access was out-of-bounds. + #[inline(always)] + pub(crate) fn try_write( + self, + io: &T, + idx: usize, + ) -> ::kernel::error::Result where + T: ::core::ops::Deref>, + { + if idx < Self::SIZE { + Ok(self.write(io, idx)) + } else { + Err(EINVAL) + } + } + + /// Read the array register at index `idx` in `io` and run `f`= on its value to obtain a + /// new value to write back. + /// + /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the + /// access was out-of-bounds. + #[inline(always)] + pub(crate) fn try_alter( + io: &T, + idx: usize, + f: F, + ) -> ::kernel::error::Result where + T: ::core::ops::Deref>, + F: ::core::ops::FnOnce(Self) -> Self, + { + if idx < Self::SIZE { + Ok(Self::alter(io, idx, f)) + } else { + Err(EINVAL) + } + } + } + }; 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Use the newly available register array feature to define them properly and improve the code using them. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon/hal/ga102.rs | 33 ++++++++++++++-------------= ---- drivers/gpu/nova-core/regs.rs | 8 +++++--- 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-c= ore/falcon/hal/ga102.rs index 3fdacd19322dd122eb00e245de4be8d1edd61a5f..13c945fd6d6b7b1acbb466678af= 0bf18da506265 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -42,35 +42,32 @@ fn signature_reg_fuse_version_ga102( engine_id_mask: u16, ucode_id: u8, ) -> Result { - // TODO[REGA]: The ucode fuse versions are contained in the - // FUSE_OPT_FPF__UCODE_VERSION registers, which are an arra= y. Our register - // definition macros do not allow us to manage them properly, so we ne= ed to hardcode their - // addresses for now. Clean this up once we support register arrays. + const NV_FUSE_OPT_FPF_SIZE: u8 =3D regs::NV_FUSE_OPT_FPF_SIZE as u8; =20 // Each engine has 16 ucode version registers numbered from 1 to 16. - if ucode_id =3D=3D 0 || ucode_id > 16 { - dev_err!(dev, "invalid ucode id {:#x}", ucode_id); - return Err(EINVAL); - } + let ucode_idx =3D match ucode_id { + 1..=3DNV_FUSE_OPT_FPF_SIZE =3D> (ucode_id - 1) as usize, + _ =3D> { + dev_err!(dev, "invalid ucode id {:#x}", ucode_id); + return Err(EINVAL); + } + }; =20 - // Base address of the FUSE registers array corresponding to the engin= e. - let reg_fuse_base =3D if engine_id_mask & 0x0001 !=3D 0 { - regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::OFFSET + // `ucode_idx` is guaranteed to be in the range [0..15], making the `r= ead` calls provable valid + // at build-time. + let reg_fuse_version =3D if engine_id_mask & 0x0001 !=3D 0 { + regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::read(bar, ucode_idx).da= ta() } else if engine_id_mask & 0x0004 !=3D 0 { - regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::OFFSET + regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::read(bar, ucode_idx).d= ata() } else if engine_id_mask & 0x0400 !=3D 0 { - regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::OFFSET + regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::read(bar, ucode_idx).dat= a() } else { dev_err!(dev, "unexpected engine_id_mask {:#x}", engine_id_mask); return Err(EINVAL); }; =20 - // Read `reg_fuse_base[ucode_id - 1]`. - let reg_fuse_version =3D - bar.read32(reg_fuse_base + ((ucode_id - 1) as usize * core::mem::s= ize_of::())); - // TODO[NUMM]: replace with `last_set_bit` once it lands. - Ok(u32::BITS - reg_fuse_version.leading_zeros()) + Ok(u16::BITS - reg_fuse_version.leading_zeros()) } =20 fn program_brom_ga102(bar: &Bar0, params: &FalconBromPara= ms) -> Result { diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 95b2c0d6b88f3b04af96f07c055c539870649937..5156ab1910501e86b4391a34549= 817d2e7818e07 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -168,15 +168,17 @@ pub(crate) fn vga_workspace_addr(self) -> Option= { =20 /* FUSE */ =20 -register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100 { +pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize =3D 16; + +register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100[NV_FUSE_OPT_FP= F_SIZE] { 15:0 data as u16; }); =20 -register!(NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION @ 0x00824140 { +register!(NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION @ 0x00824140[NV_FUSE_OPT_FPF= _SIZE] { 15:0 data as u16; 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This is effectively a combination of the relative and array registers features. nova-core does not make much use of this yet, but it will become helpful to have for GSP boot. Signed-off-by: Alexandre Courbot --- Documentation/gpu/nova/core/todo.rst | 1 - drivers/gpu/nova-core/falcon.rs | 2 +- drivers/gpu/nova-core/falcon/hal/ga102.rs | 2 +- drivers/gpu/nova-core/regs.rs | 8 +- drivers/gpu/nova-core/regs/macros.rs | 241 ++++++++++++++++++++++++++= ++++ 5 files changed, 247 insertions(+), 7 deletions(-) diff --git a/Documentation/gpu/nova/core/todo.rst b/Documentation/gpu/nova/= core/todo.rst index a1d12c1b289d89251d914fc271b7243ced11d487..48b20656dcb16056db7784fa186= f161126aae9aa 100644 --- a/Documentation/gpu/nova/core/todo.rst +++ b/Documentation/gpu/nova/core/todo.rst @@ -131,7 +131,6 @@ crate so it can be used by other components as well. =20 Features desired before this happens: =20 -* Arrays of registers with build-time index validation, * Make I/O optional I/O (for field values that are not registers), * Support other sizes than `u32`, * Allow visibility control for registers and individual fields, diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 23a4ff591c8db8d4600ec43dfaa42233cbf65c0e..2929032a97a6ccecb2d090b82af= 966991b53797b 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -501,7 +501,7 @@ fn dma_wr>( pub(crate) fn dma_load>(&self, bar: &B= ar0, fw: &F) -> Result { regs::NV_PFALCON_FBIF_CTL::alter(bar, &E::ID, |v| v.set_allow_phys= _no_ctx(true)); regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, &E::ID); - regs::NV_PFALCON_FBIF_TRANSCFG::alter(bar, &E::ID, |v| { + regs::NV_PFALCON_FBIF_TRANSCFG::alter(bar, &E::ID, 0, |v| { v.set_target(FalconFbifTarget::CoherentSysmem) .set_mem_type(FalconFbifMemType::Physical) }); diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-c= ore/falcon/hal/ga102.rs index 13c945fd6d6b7b1acbb466678af0bf18da506265..0b1cbe7853b3e85cb9c03f8e398= 7ec50a30253fb 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -73,7 +73,7 @@ fn signature_reg_fuse_version_ga102( fn program_brom_ga102(bar: &Bar0, params: &FalconBromPara= ms) -> Result { regs::NV_PFALCON2_FALCON_BROM_PARAADDR::default() .set_value(params.pkc_data_offset) - .write(bar, &E::ID); + .write(bar, &E::ID, 0); regs::NV_PFALCON2_FALCON_BROM_ENGIDMASK::default() .set_value(u32::from(params.engine_id_mask)) .write(bar, &E::ID); diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 5156ab1910501e86b4391a34549817d2e7818e07..0a5ccd845eae755c3dbfe25971b= 6d0cdf4189f8e 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -275,8 +275,7 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 0:0 reset as bool; }); =20 -// TODO[REGA]: this is an array of registers. -register!(NV_PFALCON_FBIF_TRANSCFG @ PFalconBase[0x00000600] { +register!(NV_PFALCON_FBIF_TRANSCFG @ PFalconBase[0x00000600[8]] { 1:0 target as u8 ?=3D> FalconFbifTarget; 2:2 mem_type as bool =3D> FalconFbifMemType; }); @@ -299,8 +298,9 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 31:0 value as u32; }); =20 -// TODO[REGA]: this is an array of registers. -register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ PFalcon2Base[0x00000210] { +// OpenRM defines this as a register array, but doesn't specify its size a= nd only uses its first +// element. Be conservative until we know the actual size or need to use m= ore registers. +register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ PFalcon2Base[0x00000210[1]] { 31:0 value as u32; }); =20 diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index af432f0535d2944fa4609f4a44c98a0b1394a2c0..0a342f1ac665fc99eecb08e6188= 9427543f63bc8 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -179,6 +179,73 @@ pub(crate) trait RegisterBase { /// # Ok(()) /// # } /// ``` +/// +/// ## Relative arrays of registers +/// +/// Combining the two features described in the sections above, arrays of = registers accessible from +/// a base can also be defined: +/// +/// ```no_run +/// # fn no_run() -> Result<(), Error> { +/// # fn get_scratch_idx() -> usize { +/// # 0x15 +/// # } +/// // Type used as parameter of `RegisterBase` to specify the base. +/// pub(crate) struct CpuCtlBase; +/// +/// // ZST describing `CPU0`. +/// struct Cpu0; +/// impl RegisterBase for Cpu0 { +/// const BASE: usize =3D 0xf00; +/// } +/// // Singleton of `CPU0` used to identify it. +/// const CPU0: Cpu0 =3D Cpu0; +/// +/// // ZST describing `CPU1`. +/// struct Cpu1; +/// impl RegisterBase for Cpu1 { +/// const BASE: usize =3D 0x1f00; +/// } +/// // Singleton of `CPU1` used to identify it. +/// const CPU1: Cpu1 =3D Cpu1; +/// +/// // 64 per-cpu scratch registers, arranged as an contiguous array. +/// register!(CPU_SCRATCH @ CpuCtlBase[0x1000[64]], "Per-CPU scratch regis= ters" { +/// 31:0 value as u32; +/// }); +/// +/// let cpu0_scratch_0 =3D CPU_SCRATCH::read(bar, &Cpu0, 0).value(); +/// let cpu1_scratch_15 =3D CPU_SCRATCH::read(bar, &Cpu1, 15).value(); +/// // This won't build. +/// // let cpu0_scratch_128 =3D CPU_SCRATCH::read(bar, &Cpu0, 128).value(); +/// +/// // Runtime-obtained array index. +/// let scratch_idx =3D get_scratch_idx(); +/// // Access on a runtime value returns an error if it is out-of-bounds. +/// let cpu0_some_scratch =3D CPU_SCRATCH::try_read(bar, &Cpu0, scratch_id= x)?.value(); +/// +/// // `SCRATCH[8]` is used to convey the firmware exit code. +/// register!(CPU_FIRMWARE_STATUS =3D> CpuCtlBase[CPU_SCRATCH[8]], +/// "Per-CPU firmware exit status code" { +/// 7:0 status as u8; +/// }); +/// +/// let cpu0_status =3D CPU_FIRMWARE_STATUS::read(bar, &Cpu0).status(); +/// +/// // Non-contiguous register arrays can be defined by adding a stride pa= rameter. +/// // Here, each of the 16 registers of the array are separated by 8 byte= s, meaning that the +/// // registers of the two declarations below are interleaved. +/// register!(CPU_SCRATCH_INTERLEAVED_0 @ CpuCtlBase[0x00000d00[16 ; 8]], +/// "Scratch registers bank 0" { +/// 31:0 value as u32; +/// }); +/// register!(CPU_SCRATCH_INTERLEAVED_1 @ CpuCtlBase[0x00000d04[16 ; 8]], +/// "Scratch registers bank 1" { +/// 31:0 value as u32; +/// }); +/// # Ok(()) +/// # } +/// ``` macro_rules! register { // Creates a register at a fixed offset of the MMIO space. ($name:ident @ $offset:literal $(, $comment:literal)? { $($fields:tt)*= } ) =3D> { @@ -226,7 +293,41 @@ macro_rules! register { } ); }; =20 + // Creates an array of registers at a relative offset from a base addr= ess provider. + ( + $name:ident @ $base:ty [ $offset:literal [ $size:expr ; $stride:ex= pr ] ] + $(, $comment:literal)? { $($fields:tt)* } + ) =3D> { + static_assert!(::core::mem::size_of::() <=3D $stride); + register!(@core $name $(, $comment)? { $($fields)* } ); + register!(@io_relative_array $name @ $base [ $offset [ $size ; $st= ride ] ]); + }; + + // Shortcut for contiguous array of relative registers (stride =3D=3D = size of element). + ( + $name:ident @ $base:ty [ $offset:literal [ $size:expr ] ] $(, $com= ment:literal)? { + $($fields:tt)* + } + ) =3D> { + register!($name @ $base [ $offset [ $size ; ::core::mem::size_of::= () ] ] + $(, $comment)? { $($fields)* } ); + }; + + // Creates an alias of register `idx` of relative array of registers `= alias` with its own + // fields. + ( + $name:ident =3D> $base:ty [ $alias:ident [ $idx:expr ] ] $(, $comm= ent:literal)? { + $($fields:tt)* + } + ) =3D> { + static_assert!($idx < $alias::SIZE); + register!(@core $name $(, $comment)? { $($fields)* } ); + register!(@io_relative $name @ $base [ $alias::OFFSET + $idx * $al= ias::STRIDE ] ); + }; + // Creates an alias of register `idx` of array of registers `alias` wi= th its own fields. + // This rule belongs to the (non-relative) register arrays set, but ne= eds to be put last + // to avoid it being interpreted in place of the relative register arr= ay alias rule. ($name:ident =3D> $alias:ident [ $idx:expr ] $(, $comment:literal)? { = $($fields:tt)* }) =3D> { static_assert!($idx < $alias::SIZE); register!(@core $name $(, $comment)? { $($fields)* } ); @@ -681,4 +782,144 @@ pub(crate) fn try_alter( } } }; + + // Generates the IO accessors for an array of relative registers. + ( + @io_relative_array $name:ident @ $base:ty + [ $offset:literal [ $size:expr ; $stride:expr ] ] + ) =3D> { + #[allow(dead_code)] + impl $name { + pub(crate) const OFFSET: usize =3D $offset; + pub(crate) const SIZE: usize =3D $size; + pub(crate) const STRIDE: usize =3D $stride; + + /// Read the array register at index `idx` from `io`, using th= e base address provided + /// by `base` and adding the register's offset to it. + #[inline(always)] + pub(crate) fn read( + io: &T, + #[allow(unused_variables)] + base: &B, + idx: usize, + ) -> Self where + T: ::core::ops::Deref>, + B: crate::regs::macros::RegisterBase<$base>, + { + build_assert!(idx < Self::SIZE); + + let offset =3D >::BASE + + Self::OFFSET + (idx * Self::STRIDE); + let value =3D io.read32(offset); + + Self(value) + } + + /// Write the value contained in `self` to `io`, using the bas= e address provided by + /// `base` and adding the offset of array register `idx` to it. + #[inline(always)] + pub(crate) fn write( + self, + io: &T, + #[allow(unused_variables)] + base: &B, + idx: usize + ) where + T: ::core::ops::Deref>, + B: crate::regs::macros::RegisterBase<$base>, + { + build_assert!(idx < Self::SIZE); + + let offset =3D >::BASE + + Self::OFFSET + (idx * Self::STRIDE); + + io.write32(self.0, offset); + } + + /// Read the array register at index `idx` from `io`, using th= e base address provided + /// by `base` and adding the register's offset to it, then run= `f` on its value to + /// obtain a new value to write back. + #[inline(always)] + pub(crate) fn alter( + io: &T, + base: &B, + idx: usize, + f: F, + ) where + T: ::core::ops::Deref>, + B: crate::regs::macros::RegisterBase<$base>, + F: ::core::ops::FnOnce(Self) -> Self, + { + let reg =3D f(Self::read(io, base, idx)); + reg.write(io, base, idx); + } + + /// Read the array register at index `idx` from `io`, using th= e base address provided + /// by `base` and adding the register's offset to it. + /// + /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the + /// access was out-of-bounds. + #[inline(always)] + pub(crate) fn try_read( + io: &T, + base: &B, + idx: usize, + ) -> ::kernel::error::Result where + T: ::core::ops::Deref>, + B: crate::regs::macros::RegisterBase<$base>, + { + if idx < Self::SIZE { + Ok(Self::read(io, base, idx)) + } else { + Err(EINVAL) + } + } + + /// Write the value contained in `self` to `io`, using the bas= e address provided by + /// `base` and adding the offset of array register `idx` to it. + /// + /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the + /// access was out-of-bounds. + #[inline(always)] + pub(crate) fn try_write( + self, + io: &T, + base: &B, + idx: usize, + ) -> ::kernel::error::Result where + T: ::core::ops::Deref>, + B: crate::regs::macros::RegisterBase<$base>, + { + if idx < Self::SIZE { + Ok(self.write(io, base, idx)) + } else { + Err(EINVAL) + } + } + + /// Read the array register at index `idx` from `io`, using th= e base address provided + /// by `base` and adding the register's offset to it, then run= `f` on its value to + /// obtain a new value to write back. + /// + /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the + /// access was out-of-bounds. + #[inline(always)] + pub(crate) fn try_alter( + io: &T, + base: &B, + idx: usize, + f: F, + ) -> ::kernel::error::Result where + T: ::core::ops::Deref>, + B: crate::regs::macros::RegisterBase<$base>, + F: ::core::ops::FnOnce(Self) -> Self, + { + if idx < Self::SIZE { + Ok(Self::alter(io, base, idx, f)) + } else { + Err(EINVAL) + } + } + } + }; } --=20 2.50.0