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Thu, 03 Jul 2025 14:53:29 -0700 (PDT) Received: from stband-bld-1.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c8459b3a0sm4249645ad.219.2025.07.03.14.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jul 2025 14:53:28 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/3] PCI: brcmstb: Add 74110a0 SoC configuration details Date: Thu, 3 Jul 2025 17:53:13 -0400 Message-Id: <20250703215314.3971473-4-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250703215314.3971473-1-james.quinlan@broadcom.com> References: <20250703215314.3971473-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable PCIe for 74110a0 SoC. This chip uses a simple mechanism to map inbound memory regions. Both the "ranges" and "dma-ranges" are identity-mapped to PCIe space. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 362ac083e112..bfedab15a162 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -276,6 +276,7 @@ enum pcie_soc_base { BCM7435, BCM7712, BCM33940, + BCM74110, }; =20 /* @@ -291,7 +292,7 @@ enum pcie_soc_base { * power of two. Such systems may or may not have an IOMMU between the RC * and memory. */ -#define IS_NG_PCI_SOC(t) (0) +#define IS_NG_PCI_SOC(t) ((t) =3D=3D BCM74110) =20 struct inbound_win { u64 size; @@ -2046,6 +2047,14 @@ static const int pcie_offsets_bcm7712[] =3D { [PCIE_INTR2_CPU_BASE] =3D 0x4400, }; =20 +static const int pcie_offset_bcm74110[] =3D { + [RGR1_SW_INIT_1] =3D 0xc010, + [EXT_CFG_INDEX] =3D 0x9000, + [EXT_CFG_DATA] =3D 0x8000, + [PCIE_HARD_DEBUG] =3D 0x4204, + [PCIE_INTR2_CPU_BASE] =3D 0x4300, +}; + static const int pcie_offset_bcm33940[] =3D { [RGR1_SW_INIT_1] =3D 0x9210, [EXT_CFG_INDEX] =3D 0x9000, @@ -2162,6 +2171,15 @@ static const struct pcie_cfg_data bcm33940_cfg =3D { .num_inbound_wins =3D 10, }; =20 +static const struct pcie_cfg_data bcm74110_cfg =3D { + .offsets =3D pcie_offset_bcm74110, + .soc_base =3D BCM74110, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .has_phy =3D true, + .has_err_report =3D true, +}; + static const struct of_device_id brcm_pcie_match[] =3D { { .compatible =3D "brcm,bcm2711-pcie", .data =3D &bcm2711_cfg }, { .compatible =3D "brcm,bcm2712-pcie", .data =3D &bcm2712_cfg }, @@ -2177,6 +2195,7 @@ static const struct of_device_id brcm_pcie_match[] = =3D { { .compatible =3D "brcm,bcm7445-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7712-pcie", .data =3D &bcm7712_cfg }, { .compatible =3D "brcm,bcm33940-pcie", .data =3D &bcm33940_cfg }, + { .compatible =3D "brcm,bcm74110-pcie", .data =3D &bcm74110_cfg }, {}, }; =20 --=20 2.34.1