From nobody Wed Oct 8 02:01:44 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 502AE2F2C7D for ; Thu, 3 Jul 2025 19:26:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751570815; cv=none; b=XwiUX/ZBfPF3/Vs67dgePnHeFCHmor89mbhIJVOXyMVpP3Y2bvMko3tVJmLPNgAxjxRF5JdnG0XtEVDHwFanEx2UZ4Ewmdmja6cK1bVZaNfxVBf3K4Z8J5sQ1E9yxPTQZTN8gHX7qwGUvqCfSbd/smH4AWDr40OkXg5Pmfju4JY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751570815; c=relaxed/simple; bh=SsTnvwJ+cEVA7NM8KwrGIh0nmDOkD5TYSCwiYE+RYKE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=J9Zl6/4Bg3ZJCP+3fe0phjwjZBi1bQhy+AzfBhpLyTzmTB84HBEDlSbWgJxLenkjPW87mmehVoZxeUoK8iajxpfWVg5JAXzQsFeu7lUUsko2ujtadKP3UNHzqGBh27nucGOZ0jREZvxlUJgzaUTIO1iNqdsByVeejbRnRyEM6EQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GcpTQA2b; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GcpTQA2b" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751570813; x=1783106813; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SsTnvwJ+cEVA7NM8KwrGIh0nmDOkD5TYSCwiYE+RYKE=; b=GcpTQA2bsMtVWbkEG4qLtRo454NpKwYielP9JCjiZR4QFqE8+eoGM3O3 vMWQgofX/E7doqfY5yfShTKtembpAMj/i1uNUI4u8J/YzqP9LDsAhY1Ga qWjvVSZt6PSq2EtToOUb3o0waDqbUln+hRHcyXjns3mkQt4hHJunWJwkE QIGScK6S4qOh0PYu6rPDsCM17x9MZ5qX4uDTtXPgYhHb/y93KNUIYvpwF +bIL42bHxojrUBqld99ryuaZxEIEFtcs28bRgL9Z3j11KVmPskYjaSlF6 BVmG8IOQJe6AGcEWA0uiK/UgVmiWCAn3fTjgyl7jJA3W1gEZupyuZPNOR Q==; X-CSE-ConnectionGUID: 9sXPgAP4T+S1c5jY8CmHUw== X-CSE-MsgGUID: 9U+NhPabQ0aYnn7EJTGIIA== X-IronPort-AV: E=McAfee;i="6800,10657,11483"; a="65361997" X-IronPort-AV: E=Sophos;i="6.16,285,1744095600"; d="scan'208";a="65361997" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 12:26:53 -0700 X-CSE-ConnectionGUID: QoAjFWCXRFmYDCmq6unlIA== X-CSE-MsgGUID: Yf0UsJ/RTw6LQAEqB6YTCw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,285,1744095600"; d="scan'208";a="191624631" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 12:26:51 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v6 03/10] drm/xe/xe_late_bind_fw: Introducing xe_late_bind_fw Date: Fri, 4 Jul 2025 01:00:59 +0530 Message-Id: <20250703193106.954536-4-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250703193106.954536-1-badal.nilawar@intel.com> References: <20250703193106.954536-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Introducing xe_late_bind_fw to enable firmware loading for the devices, such as the fan controller, during the driver probe. Typically, firmware for such devices are part of IFWI flash image but can be replaced at probe after OEM tuning. This patch binds mei late binding component to enable firmware loading. v2: - Add devm_add_action_or_reset to remove the component (Daniele) - Add INTEL_MEI_GSC check in xe_late_bind_init() (Daniele) v3: - Fail driver probe if late bind initialization fails, add has_late_bind flag (Daniele) v4: - %S/I915_COMPONENT_LATE_BIND/INTEL_COMPONENT_LATE_BIND/ v6: - rebased Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 5 ++ drivers/gpu/drm/xe/xe_device_types.h | 6 ++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 83 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.h | 15 ++++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 35 +++++++++ drivers/gpu/drm/xe/xe_pci.c | 2 + drivers/gpu/drm/xe/xe_pci_types.h | 1 + 8 files changed, 148 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.c create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.h create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw_types.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 7c039caefd00..521547d78fd2 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -76,6 +76,7 @@ xe-y +=3D xe_bb.o \ xe_hw_fence.o \ xe_irq.o \ xe_lrc.o \ + xe_late_bind_fw.o \ xe_migrate.o \ xe_mmio.o \ xe_mocs.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 0b73cb72bad1..cb595bae5f55 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -44,6 +44,7 @@ #include "xe_hw_engine_group.h" #include "xe_hwmon.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_mmio.h" #include "xe_module.h" #include "xe_nvm.h" @@ -866,6 +867,10 @@ int xe_device_probe(struct xe_device *xe) if (err) return err; =20 + err =3D xe_late_bind_init(&xe->late_bind); + if (err && err !=3D -ENODEV) + return err; + err =3D xe_oa_init(xe); if (err) return err; diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index 78c4acafd268..a8891833f980 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -16,6 +16,7 @@ #include "xe_devcoredump_types.h" #include "xe_heci_gsc.h" #include "xe_lmtt_types.h" +#include "xe_late_bind_fw_types.h" #include "xe_memirq_types.h" #include "xe_oa_types.h" #include "xe_platform_types.h" @@ -325,6 +326,8 @@ struct xe_device { u8 has_heci_cscfi:1; /** @info.has_heci_gscfi: device has heci gscfi */ u8 has_heci_gscfi:1; + /** @info.has_late_bind: Device has firmware late binding support */ + u8 has_late_bind:1; /** @info.has_llc: Device has a shared CPU+GPU last level cache */ u8 has_llc:1; /** @info.has_mbx_power_limits: Device has support to manage power limit= s using @@ -557,6 +560,9 @@ struct xe_device { /** @nvm: discrete graphics non-volatile memory */ struct intel_dg_nvm_dev *nvm; =20 + /** @late_bind: xe mei late bind interface */ + struct xe_late_bind late_bind; + /** @oa: oa observation subsystem */ struct xe_oa oa; =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c new file mode 100644 index 000000000000..22e79f0dbbdf --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#include +#include + +#include +#include +#include +#include + +#include "xe_device.h" +#include "xe_late_bind_fw.h" + +static struct xe_device * +late_bind_to_xe(struct xe_late_bind *late_bind) +{ + return container_of(late_bind, struct xe_device, late_bind); +} + +static int xe_late_bind_component_bind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + late_bind->component.ops =3D data; + late_bind->component.mei_dev =3D mei_kdev; + + return 0; +} + +static void xe_late_bind_component_unbind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + late_bind->component.ops =3D NULL; +} + +static const struct component_ops xe_late_bind_component_ops =3D { + .bind =3D xe_late_bind_component_bind, + .unbind =3D xe_late_bind_component_unbind, +}; + +static void xe_late_bind_remove(void *arg) +{ + struct xe_late_bind *late_bind =3D arg; + struct xe_device *xe =3D late_bind_to_xe(late_bind); + + component_del(xe->drm.dev, &xe_late_bind_component_ops); +} + +/** + * xe_late_bind_init() - add xe mei late binding component + * + * Return: 0 if the initialization was successful, a negative errno otherw= ise. + */ +int xe_late_bind_init(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int err; + + if (!xe->info.has_late_bind) + return 0; + + if (!IS_ENABLED(CONFIG_INTEL_MEI_LATE_BIND) || !IS_ENABLED(CONFIG_INTEL_M= EI_GSC)) { + drm_info(&xe->drm, "Can't init xe mei late bind missing mei component\n"= ); + return -ENODEV; + } + + err =3D component_add_typed(xe->drm.dev, &xe_late_bind_component_ops, + INTEL_COMPONENT_LATE_BIND); + if (err < 0) { + drm_info(&xe->drm, "Failed to add mei late bind component (%pe)\n", ERR_= PTR(err)); + return err; + } + + return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); +} diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h new file mode 100644 index 000000000000..4c73571c3e62 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_FW_H_ +#define _XE_LATE_BIND_FW_H_ + +#include + +struct xe_late_bind; + +int xe_late_bind_init(struct xe_late_bind *late_bind); + +#endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h new file mode 100644 index 000000000000..9806d17291ad --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_TYPES_H_ +#define _XE_LATE_BIND_TYPES_H_ + +#include +#include +#include + +/** + * struct xe_late_bind_component - Late Binding services component + * @mei_dev: device that provide Late Binding service. + * @ops: Ops implemented by Late Binding driver, used by Xe driver. + * + * Communication between Xe and MEI drivers for Late Binding services + */ +struct xe_late_bind_component { + /** @late_bind_component.mei_dev: mei device */ + struct device *mei_dev; + /** @late_bind_component.ops: late binding ops */ + const struct late_bind_component_ops *ops; +}; + +/** + * struct xe_late_bind + */ +struct xe_late_bind { + /** @late_bind.component: struct for communication with mei component */ + struct xe_late_bind_component component; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 42aaef9fa2ea..b1fe5a323897 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -329,6 +329,7 @@ static const struct xe_device_desc bmg_desc =3D { .has_gsc_nvm =3D 1, .has_heci_cscfi =3D 1, .max_gt_per_tile =3D 2, + .has_late_bind =3D true, .needs_scratch =3D true, }; =20 @@ -575,6 +576,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.has_gsc_nvm =3D desc->has_gsc_nvm; xe->info.has_heci_gscfi =3D desc->has_heci_gscfi; xe->info.has_heci_cscfi =3D desc->has_heci_cscfi; + xe->info.has_late_bind =3D desc->has_late_bind; xe->info.has_llc =3D desc->has_llc; xe->info.has_pxp =3D desc->has_pxp; xe->info.has_sriov =3D desc->has_sriov; diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_= types.h index 4de6f69ed975..51a607d323fb 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -39,6 +39,7 @@ struct xe_device_desc { u8 has_gsc_nvm:1; u8 has_heci_gscfi:1; u8 has_heci_cscfi:1; + u8 has_late_bind:1; u8 has_llc:1; u8 has_mbx_power_limits:1; u8 has_pxp:1; --=20 2.34.1