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Thu, 3 Jul 2025 11:56:23 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , , , , Vlad Dogaru , "Yevgeny Kliteynik" , Mark Bloch Subject: [PATCH net-next v3 06/10] net/mlx5: HWS, Decouple matcher RX and TX sizes Date: Thu, 3 Jul 2025 21:54:27 +0300 Message-ID: <20250703185431.445571-7-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250703185431.445571-1-mbloch@nvidia.com> References: <20250703185431.445571-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|SJ0PR12MB6784:EE_ X-MS-Office365-Filtering-Correlation-Id: c426485a-ca37-493e-906d-08ddba635b5e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?puKb0QP4GIAahgftDiXppDwfn3AOPrInCuppHLMVPOMQjYA42B3qkHzUI0PJ?= =?us-ascii?Q?0438+5vOR+lOJaJ5g+1YnwdE7XWejmE3Dh43p2ZPNMY9t7V/WWqAKZskNhzk?= =?us-ascii?Q?RutvFXbGoIRWi2ZPLu16J1Qk8QdPybAD/ND+1lfBsQ9JiVzI6F4fndfs1hl2?= =?us-ascii?Q?aoWvNDCcKYmrvHlxkmjFT9vtluhPPEnNIOFb1G/OcHixC/frzosZ6xfvXDY8?= =?us-ascii?Q?KKSeJQT5CACPufc8b9kJxyvOgdJLraSaCGjFvGihF+g8S2juLnbcA+jj1eZL?= =?us-ascii?Q?T9G3GjoqsQP4oH6JAw+twyY6CFzD0h4JciRsa4+TiFHQYbppQdoIfnuYGWPe?= =?us-ascii?Q?r76/X98piA1iVdKY7qTmwlvCJzbqNy5YkRqrYn+Pyi+Z+tzpx0LXVkbk/e3T?= =?us-ascii?Q?WpEPJ4/Id5bQBx7s/fWbXJw1ete5Rj6CYLA8JZ19yYBhLASMH4OGh63wYjoD?= =?us-ascii?Q?m+RHHOqDe8FK849gEnorj3iVdWz5BcPjEWJm54qtwDl54amOF0ux1MwDurv3?= =?us-ascii?Q?ASyDt/bue9jZukZuy8734EsHUCBTucB7Y1QjJGQffXowAWK+UABpQF3opBW1?= =?us-ascii?Q?47NOTMAPWvmEaspCNnRQ5v70aR8Nl1EWycBRh9jtkHsc0VoLYc0AHqSfdwWk?= =?us-ascii?Q?2CEG38cxVOFI8WaQzEG6c55N1wmybq3Ni2+b0OnhBvE3jPDDSItvfOmigG+o?= =?us-ascii?Q?WQr6EQnKab/f+pgfsy7wNDGbzOcIpss7hQo/Wqi1qXqdUlFxJMvbxnGmtAZf?= =?us-ascii?Q?KA4vWfeZ12hqF5HJCvv1du+yPRRZa/aR3+UfGHitWVlTD0NoseEqw1lHVyEU?= =?us-ascii?Q?OJa2O1ogorG0wDIdeYYm57+P5AdWKc1VT8W5ibUs/fKI88v7269fS0InoaeX?= =?us-ascii?Q?wKIDEVPku05hJKtpFLxjXj1HgelMtpm8fh69inVDSw6WaNDgbbm3gj1vW22b?= =?us-ascii?Q?1fd7c4MH9WT6iQD1JvtiNO/vg6IZf4FkurJU5/NWafATBnzLMExRdD/8TcEC?= =?us-ascii?Q?6m2hGZJ1OsqzX1Yxx7CivBNLbiTwnMDxRzOJ0ccTbXDil35IIwpL89R1vLny?= =?us-ascii?Q?w/7Ndecnm/71nhk5uQbiiS0amsxnVO4WFNkmr+7cMPPJJ92Jh5E2yHcFBg8z?= =?us-ascii?Q?6H1mpXJGABbNi/8cQUnmqdcMJzQu2cDe+qeGd/2HvlEhN9cwvLaU4B2BHrb8?= =?us-ascii?Q?C4816kHdNs6Jdfg8aHUqZW1AcqxAFPcKSleHEid8H7Fx+M1Exm92pvQIt/Fd?= =?us-ascii?Q?NQ2oNORXGQfCipoi1zl7qMjd2fv2/P7lugp5oagmRWBhYd95u1FhxbvSWEUd?= =?us-ascii?Q?OEF7GKQa+8Hk/XN/W/Nw6Cpgp2eAuE0KdD/mAgZ3NHQqP69DlDPnG+9Geejh?= =?us-ascii?Q?7hn1fkE2hQ3RwaxqqdMMqdiW+VWHJJU8Tlt3DKlCKA3UXJUVjoBrcRLR2/50?= =?us-ascii?Q?yyOudIh+GQ1nYeh4f7OYYbfENfg+P8eYTYTm+T6prOFhbI6JmGGKqRojisgi?= =?us-ascii?Q?OLmtYrp22argSKjgTXliUCWPk3/+S45aGdFJ?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jul 2025 18:56:45.2106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c426485a-ca37-493e-906d-08ddba635b5e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6784 Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru Kernel HWS only uses FDB tables and, as such, creates two lower level containers (RTCs) for each matcher: one for RX and one for TX. Allow these RTCs to differ in size by converting the size part of the matcher attribute to a two element array. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Reviewed-by: Simon Horman Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/bwc.c | 7 +- .../mellanox/mlx5/core/steering/hws/debug.c | 10 +- .../mellanox/mlx5/core/steering/hws/matcher.c | 107 ++++++++++++------ .../mellanox/mlx5/core/steering/hws/mlx5hws.h | 28 +++-- 4 files changed, 104 insertions(+), 48 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index 665e6e285db5..009641e6c874 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -48,7 +48,7 @@ static void hws_bwc_unlock_all_queues(struct mlx5hws_cont= ext *ctx) =20 static void hws_bwc_matcher_init_attr(struct mlx5hws_bwc_matcher *bwc_matc= her, u32 priority, - u8 size_log, + u8 size_log_rx, u8 size_log_tx, struct mlx5hws_matcher_attr *attr) { struct mlx5hws_bwc_matcher *first_matcher =3D @@ -62,7 +62,8 @@ static void hws_bwc_matcher_init_attr(struct mlx5hws_bwc_= matcher *bwc_matcher, attr->optimize_flow_src =3D MLX5HWS_MATCHER_FLOW_SRC_ANY; attr->insert_mode =3D MLX5HWS_MATCHER_INSERT_BY_HASH; attr->distribute_mode =3D MLX5HWS_MATCHER_DISTRIBUTE_BY_HASH; - attr->rule.num_log =3D size_log; + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX].rule.num_log =3D size_log_rx; + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX].rule.num_log =3D size_log_tx; attr->resizable =3D true; attr->max_num_of_at_attach =3D MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM; =20 @@ -93,6 +94,7 @@ int mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bwc_= matcher *bwc_matcher, hws_bwc_matcher_init_attr(bwc_matcher, priority, MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG, + MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG, &attr); =20 bwc_matcher->priority =3D priority; @@ -696,6 +698,7 @@ static int hws_bwc_matcher_move(struct mlx5hws_bwc_matc= her *bwc_matcher) hws_bwc_matcher_init_attr(bwc_matcher, bwc_matcher->priority, bwc_matcher->size_log, + bwc_matcher->size_log, &matcher_attr); =20 old_matcher =3D bwc_matcher->matcher; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c b= /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c index f9b75aefcaa7..2ec8cb10139a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c @@ -99,17 +99,19 @@ hws_debug_dump_matcher_attr(struct seq_file *f, struct = mlx5hws_matcher *matcher) { struct mlx5hws_matcher_attr *attr =3D &matcher->attr; =20 - seq_printf(f, "%d,0x%llx,%d,%d,%d,%d,%d,%d,%d,%d\n", + seq_printf(f, "%d,0x%llx,%d,%d,%d,%d,%d,%d,%d,%d,-1,-1,%d,%d\n", MLX5HWS_DEBUG_RES_TYPE_MATCHER_ATTR, HWS_PTR_TO_ID(matcher), attr->priority, attr->mode, - attr->table.sz_row_log, - attr->table.sz_col_log, + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX].table.sz_row_log, + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX].table.sz_col_log, attr->optimize_using_rule_idx, attr->optimize_flow_src, attr->insert_mode, - attr->distribute_mode); + attr->distribute_mode, + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX].table.sz_row_log, + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX].table.sz_col_log); =20 return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index b0fcaf508e06..f3ea09caba2b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -468,12 +468,16 @@ static int hws_matcher_create_rtc(struct mlx5hws_matc= her *matcher) struct mlx5hws_cmd_rtc_create_attr rtc_attr =3D {0}; struct mlx5hws_match_template *mt =3D matcher->mt; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size_rx, *size_tx; struct mlx5hws_table *tbl =3D matcher->tbl; u32 obj_id; int ret; =20 - rtc_attr.log_size =3D attr->table.sz_row_log; - rtc_attr.log_depth =3D attr->table.sz_col_log; + size_rx =3D &attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; + size_tx =3D &attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; + + rtc_attr.log_size =3D size_rx->table.sz_row_log; + rtc_attr.log_depth =3D size_rx->table.sz_col_log; rtc_attr.is_frst_jumbo =3D mlx5hws_matcher_mt_is_jumbo(mt); rtc_attr.is_scnd_range =3D 0; rtc_attr.miss_ft_id =3D matcher->end_ft_id; @@ -525,6 +529,8 @@ static int hws_matcher_create_rtc(struct mlx5hws_matche= r *matcher) } =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) { + rtc_attr.log_size =3D size_tx->table.sz_row_log; + rtc_attr.log_depth =3D size_tx->table.sz_col_log; rtc_attr.ste_base =3D matcher->match_ste.ste_1_base; rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, true= ); =20 @@ -562,23 +568,33 @@ hws_matcher_check_attr_sz(struct mlx5hws_cmd_query_ca= ps *caps, struct mlx5hws_matcher *matcher) { struct mlx5hws_matcher_attr *attr =3D &matcher->attr; + struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size; + int i; =20 - if (attr->table.sz_col_log > caps->rtc_log_depth_max) { - mlx5hws_err(matcher->tbl->ctx, "Matcher depth exceeds limit %d\n", - caps->rtc_log_depth_max); - return -EOPNOTSUPP; - } + for (i =3D 0; i < 2; i++) { + size =3D &attr->size[i]; =20 - if (attr->table.sz_col_log + attr->table.sz_row_log > caps->ste_alloc_log= _max) { - mlx5hws_err(matcher->tbl->ctx, "Total matcher size exceeds limit %d\n", - caps->ste_alloc_log_max); - return -EOPNOTSUPP; - } + if (size->table.sz_col_log > caps->rtc_log_depth_max) { + mlx5hws_err(ctx, "Matcher depth exceeds limit %d\n", + caps->rtc_log_depth_max); + return -EOPNOTSUPP; + } =20 - if (attr->table.sz_col_log + attr->table.sz_row_log < caps->ste_alloc_log= _gran) { - mlx5hws_err(matcher->tbl->ctx, "Total matcher size below limit %d\n", - caps->ste_alloc_log_gran); - return -EOPNOTSUPP; + if (size->table.sz_col_log + size->table.sz_row_log > + caps->ste_alloc_log_max) { + mlx5hws_err(ctx, + "Total matcher size exceeds limit %d\n", + caps->ste_alloc_log_max); + return -EOPNOTSUPP; + } + + if (size->table.sz_col_log + size->table.sz_row_log < + caps->ste_alloc_log_gran) { + mlx5hws_err(ctx, "Total matcher size below limit %d\n", + caps->ste_alloc_log_gran); + return -EOPNOTSUPP; + } } =20 return 0; @@ -666,6 +682,7 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher *= matcher) { struct mlx5hws_cmd_ste_create_attr ste_attr =3D {}; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size; int ret; =20 /* Calculate match, range and hash definers */ @@ -682,11 +699,11 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher= *matcher) =20 /* Create an STE range each for RX and TX. */ ste_attr.table_type =3D FS_FT_FDB_RX; + size =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; ste_attr.log_obj_range =3D matcher->attr.optimize_flow_src =3D=3D - MLX5HWS_MATCHER_FLOW_SRC_VPORT ? - 0 : matcher->attr.table.sz_col_log + - matcher->attr.table.sz_row_log; + MLX5HWS_MATCHER_FLOW_SRC_VPORT ? + 0 : size->table.sz_col_log + size->table.sz_row_log; =20 ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, &matcher->match_ste.ste_0_base); @@ -696,11 +713,11 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher= *matcher) } =20 ste_attr.table_type =3D FS_FT_FDB_TX; + size =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; ste_attr.log_obj_range =3D matcher->attr.optimize_flow_src =3D=3D - MLX5HWS_MATCHER_FLOW_SRC_WIRE ? - 0 : matcher->attr.table.sz_col_log + - matcher->attr.table.sz_row_log; + MLX5HWS_MATCHER_FLOW_SRC_WIRE ? + 0 : size->table.sz_col_log + size->table.sz_row_log; =20 ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, &matcher->match_ste.ste_1_base); @@ -735,6 +752,10 @@ hws_matcher_validate_insert_mode(struct mlx5hws_cmd_qu= ery_caps *caps, { struct mlx5hws_matcher_attr *attr =3D &matcher->attr; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size_rx, *size_tx; + + size_rx =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; + size_tx =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; =20 switch (attr->insert_mode) { case MLX5HWS_MATCHER_INSERT_BY_HASH: @@ -745,7 +766,7 @@ hws_matcher_validate_insert_mode(struct mlx5hws_cmd_que= ry_caps *caps, break; =20 case MLX5HWS_MATCHER_INSERT_BY_INDEX: - if (attr->table.sz_col_log) { + if (size_rx->table.sz_col_log || size_tx->table.sz_col_log) { mlx5hws_err(ctx, "Matcher with INSERT_BY_INDEX supports only Nx1 table = size\n"); return -EOPNOTSUPP; } @@ -765,7 +786,10 @@ hws_matcher_validate_insert_mode(struct mlx5hws_cmd_qu= ery_caps *caps, return -EOPNOTSUPP; } =20 - if (attr->table.sz_row_log > MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX) { + if (size_rx->table.sz_row_log > + MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX || + size_tx->table.sz_row_log > + MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX) { mlx5hws_err(ctx, "Matcher with linear distribute: rows exceed limit %d= ", MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX); return -EOPNOTSUPP; @@ -789,6 +813,10 @@ hws_matcher_process_attr(struct mlx5hws_cmd_query_caps= *caps, struct mlx5hws_matcher *matcher) { struct mlx5hws_matcher_attr *attr =3D &matcher->attr; + union mlx5hws_matcher_size *size_rx, *size_tx; + + size_rx =3D &attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; + size_tx =3D &attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; =20 if (hws_matcher_validate_insert_mode(caps, matcher)) return -EOPNOTSUPP; @@ -800,8 +828,12 @@ hws_matcher_process_attr(struct mlx5hws_cmd_query_caps= *caps, =20 /* Convert number of rules to the required depth */ if (attr->mode =3D=3D MLX5HWS_MATCHER_RESOURCE_MODE_RULE && - attr->insert_mode =3D=3D MLX5HWS_MATCHER_INSERT_BY_HASH) - attr->table.sz_col_log =3D hws_matcher_rules_to_tbl_depth(attr->rule.num= _log); + attr->insert_mode =3D=3D MLX5HWS_MATCHER_INSERT_BY_HASH) { + size_rx->table.sz_col_log =3D + hws_matcher_rules_to_tbl_depth(size_rx->rule.num_log); + size_tx->table.sz_col_log =3D + hws_matcher_rules_to_tbl_depth(size_tx->rule.num_log); + } =20 matcher->flags |=3D attr->resizable ? MLX5HWS_MATCHER_FLAGS_RESIZABLE : 0; matcher->flags |=3D attr->isolated_matcher_end_ft_id ? @@ -862,14 +894,19 @@ static int hws_matcher_create_col_matcher(struct mlx5hws_matcher *matcher) { struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size_rx, *size_tx; struct mlx5hws_matcher *col_matcher; - int ret; + int i, ret; + + size_rx =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; + size_tx =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; =20 if (matcher->attr.mode !=3D MLX5HWS_MATCHER_RESOURCE_MODE_RULE || matcher->attr.insert_mode =3D=3D MLX5HWS_MATCHER_INSERT_BY_INDEX) return 0; =20 - if (!hws_matcher_requires_col_tbl(matcher->attr.rule.num_log)) + if (!hws_matcher_requires_col_tbl(size_rx->rule.num_log) && + !hws_matcher_requires_col_tbl(size_tx->rule.num_log)) return 0; =20 col_matcher =3D kzalloc(sizeof(*matcher), GFP_KERNEL); @@ -886,10 +923,16 @@ hws_matcher_create_col_matcher(struct mlx5hws_matcher= *matcher) col_matcher->flags |=3D MLX5HWS_MATCHER_FLAGS_COLLISION; col_matcher->attr.mode =3D MLX5HWS_MATCHER_RESOURCE_MODE_HTABLE; col_matcher->attr.optimize_flow_src =3D matcher->attr.optimize_flow_src; - col_matcher->attr.table.sz_row_log =3D matcher->attr.rule.num_log; - col_matcher->attr.table.sz_col_log =3D MLX5HWS_MATCHER_ASSURED_COL_TBL_DE= PTH; - if (col_matcher->attr.table.sz_row_log > MLX5HWS_MATCHER_ASSURED_ROW_RATI= O) - col_matcher->attr.table.sz_row_log -=3D MLX5HWS_MATCHER_ASSURED_ROW_RATI= O; + for (i =3D 0; i < 2; i++) { + union mlx5hws_matcher_size *dst =3D &col_matcher->attr.size[i]; + union mlx5hws_matcher_size *src =3D &matcher->attr.size[i]; + + dst->table.sz_row_log =3D src->rule.num_log; + dst->table.sz_col_log =3D MLX5HWS_MATCHER_ASSURED_COL_TBL_DEPTH; + if (dst->table.sz_row_log > MLX5HWS_MATCHER_ASSURED_ROW_RATIO) + dst->table.sz_row_log -=3D + MLX5HWS_MATCHER_ASSURED_ROW_RATIO; + } =20 col_matcher->attr.max_num_of_at_attach =3D matcher->attr.max_num_of_at_at= tach; col_matcher->attr.isolated_matcher_end_ft_id =3D diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h index a1295a311b70..59c14745ed0c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h @@ -93,6 +93,23 @@ enum mlx5hws_matcher_distribute_mode { MLX5HWS_MATCHER_DISTRIBUTE_BY_LINEAR =3D 0x1, }; =20 +enum mlx5hws_matcher_size_type { + MLX5HWS_MATCHER_SIZE_TYPE_RX, + MLX5HWS_MATCHER_SIZE_TYPE_TX, + MLX5HWS_MATCHER_SIZE_TYPE_MAX, +}; + +union mlx5hws_matcher_size { + struct { + u8 sz_row_log; + u8 sz_col_log; + } table; + + struct { + u8 num_log; + } rule; +}; + struct mlx5hws_matcher_attr { /* Processing priority inside table */ u32 priority; @@ -107,16 +124,7 @@ struct mlx5hws_matcher_attr { enum mlx5hws_matcher_distribute_mode distribute_mode; /* Define whether the created matcher supports resizing into a bigger mat= cher */ bool resizable; - union { - struct { - u8 sz_row_log; - u8 sz_col_log; - } table; - - struct { - u8 num_log; - } rule; - }; + union mlx5hws_matcher_size size[MLX5HWS_MATCHER_SIZE_TYPE_MAX]; /* Optional AT attach configuration - Max number of additional AT */ u8 max_num_of_at_attach; /* Optional end FT (miss FT ID) for match RTC (for isolated matcher) */ --=20 2.34.1