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Thu, 3 Jul 2025 11:56:19 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , , , , Vlad Dogaru , "Yevgeny Kliteynik" , Mark Bloch Subject: [PATCH net-next v3 05/10] net/mlx5: HWS, Create STEs directly from matcher Date: Thu, 3 Jul 2025 21:54:26 +0300 Message-ID: <20250703185431.445571-6-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250703185431.445571-1-mbloch@nvidia.com> References: <20250703185431.445571-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DE:EE_|DS7PR12MB5888:EE_ X-MS-Office365-Filtering-Correlation-Id: f4e2cd04-c187-4816-0e50-08ddba635922 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Iof/FWmo9F4nKXfFunkLDQSZIcmO+84RLCK/ts7tyMCciMmvA0VkdH+6iT96?= =?us-ascii?Q?wt8oDsdIxRkfJMmh53pFf2Vbx+X7M4O/oACWY400T3OoC7cFVvu/78wlrA0a?= =?us-ascii?Q?mErdp/8Jrkt2ZveGArYpYNTXzaYjJnrUBiwhdWu7VULBh1+39c9p4JpH9REN?= =?us-ascii?Q?hHN49Lr7tRRTj7cOubBPqjZDqUgaAFQ2+Dz/d812aKKcA5yyYV8P56Fios5E?= =?us-ascii?Q?aVkOxzccAvwn7fatWk2PbM1OlV67e270ogDeGZDibZhpHORBtXehi9Dmrv5p?= =?us-ascii?Q?7osaeMlvHYP8js5ouu2NSroracSwrXV1NLzwPLumSkizbToGjXXkbfh3inio?= =?us-ascii?Q?JtM0Ij8usgw+SwUu02qQIH1l11mnSGeLW0NLHdvoKoyZPH6rqIdgHIFYgvoE?= =?us-ascii?Q?7I9LgKrgkajQmQNxA3M3hOK5tYpSrL0oNi6QSO1VScOTlaxAUL1GDlYEirwX?= =?us-ascii?Q?xu0z5VYNzoaAnUkFw9vbKB6G/3AfnIIJuTYqLnYjycif2073VnffDjARsPy5?= =?us-ascii?Q?5ugzIWYR4IRVa/HjGgwmgHxtDtq86whG/tRThveYa96+7SMlq0Kms9+NhoHU?= =?us-ascii?Q?OmuRpn0BC4+8/uGEGTNV3WnUTBWXK1zL/jganCygcSck7TziaKK45Db/kP9K?= =?us-ascii?Q?hkEqJY+X+R1ZQu6TfMFq1YX/v/QGGg8ysUitJUXvjqcsXx1flGpMz0Sxu6ll?= =?us-ascii?Q?UERw346ASG5RymU1677tNZVUNOYK0IQP8fH1kB+qYjjRLOnmFXrYm7hYkApT?= =?us-ascii?Q?9T8ZZnMwM5Sz+xhdbc9tSk2G/2I218SkZ2iy4wQ1WXt3qciRVdiX+mpfr4DG?= =?us-ascii?Q?lJn4XbcLtRo736OZzL9NgVTlMYgg4KXdk1sq2PNF62jCHQh2/TThhKIpXk0k?= =?us-ascii?Q?bRJHZSvstqQH+Vucbwvpszzi52CIzhRAj4G38tHFa0fgk8mRNI26feWkbSep?= =?us-ascii?Q?51G7g/pv7xb95g9/0MoRADAw8dxV6Ypr9UK6odRhiimk/Fm42N2ufhseMLOu?= =?us-ascii?Q?DJb7ZOnhanOYmb9NPCE6gEmF95SVxnThHb8XTEN2v7NQw4I5vxw6gAQfcGmx?= =?us-ascii?Q?yWTtELF4nDjJJn9LZ8Bt5sypB3yWdaobwUFpnCpCTct3F/kP6Xf1ZztA44i3?= =?us-ascii?Q?pkcv+fLbo/vEo/1ReghiQf3gYlTzI/7C63Uva5o5iMuP+FtdGXhwZ5BqWsBy?= =?us-ascii?Q?MwRzEt5cRN3wFkPztPDYKZEeCDplsT7afbM9Xx7Gcn1l1PXMCh+D8XIPf4px?= =?us-ascii?Q?N1a5ih6iaXnG2fTCIY1/elnSIkLJq9wgBEPq/M77h20VwpjXOTaK4/XfF01l?= =?us-ascii?Q?WW311U76NzcHv90M4iGFl6iBDrrVaV6DoBqpcLB4Qv93K1RIK4UAKyddLXzP?= =?us-ascii?Q?9JnsBQOdGp2e5I3BkB655kxiUDAj44g9T9cskvGPn9aVT+4j+gkrbJyUnPDn?= =?us-ascii?Q?+h7BGgHHnTg4PVDrlWfY+FuFahwZc7bfWtwPJ9rqPYoZnN0qNgPaChgplk/3?= =?us-ascii?Q?GAAxZEQpj8alrogQTs7da2uILJy67F1x/9tb?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jul 2025 18:56:41.4942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4e2cd04-c187-4816-0e50-08ddba635922 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5888 Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru Matchers were using the pool abstraction solely as a convenience to allocate two STE ranges. The pool's core functionality, that of allocating individual items from the range, was unused. Matchers rely either on the hardware to hash rules into a table, or on a user-provided index. Remove the STE pool from the matcher and allocate the STE ranges manually instead. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Reviewed-by: Simon Horman Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/debug.c | 10 +-- .../mellanox/mlx5/core/steering/hws/matcher.c | 71 ++++++++++--------- .../mellanox/mlx5/core/steering/hws/matcher.h | 3 +- 3 files changed, 41 insertions(+), 43 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c b= /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c index 91568d6c1dac..f9b75aefcaa7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c @@ -118,7 +118,6 @@ static int hws_debug_dump_matcher(struct seq_file *f, s= truct mlx5hws_matcher *ma { enum mlx5hws_table_type tbl_type =3D matcher->tbl->type; struct mlx5hws_cmd_ft_query_attr ft_attr =3D {0}; - struct mlx5hws_pool *ste_pool; u64 icm_addr_0 =3D 0; u64 icm_addr_1 =3D 0; u32 ste_0_id =3D -1; @@ -133,12 +132,9 @@ static int hws_debug_dump_matcher(struct seq_file *f, = struct mlx5hws_matcher *ma matcher->end_ft_id, matcher->col_matcher ? HWS_PTR_TO_ID(matcher->col_matcher) : 0); =20 - ste_pool =3D matcher->match_ste.pool; - if (ste_pool) { - ste_0_id =3D mlx5hws_pool_get_base_id(ste_pool); - if (tbl_type =3D=3D MLX5HWS_TABLE_TYPE_FDB) - ste_1_id =3D mlx5hws_pool_get_base_mirror_id(ste_pool); - } + ste_0_id =3D matcher->match_ste.ste_0_base; + if (tbl_type =3D=3D MLX5HWS_TABLE_TYPE_FDB) + ste_1_id =3D matcher->match_ste.ste_1_base; =20 seq_printf(f, ",%d,%d,%d,%d", matcher->match_ste.rtc_0_id, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index ce28ee1c0e41..b0fcaf508e06 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -507,10 +507,8 @@ static int hws_matcher_create_rtc(struct mlx5hws_match= er *matcher) } } =20 - obj_id =3D mlx5hws_pool_get_base_id(matcher->match_ste.pool); - rtc_attr.pd =3D ctx->pd_num; - rtc_attr.ste_base =3D obj_id; + rtc_attr.ste_base =3D matcher->match_ste.ste_0_base; rtc_attr.reparse_mode =3D mlx5hws_context_get_reparse_mode(ctx); rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, false= ); hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, false); @@ -527,9 +525,7 @@ static int hws_matcher_create_rtc(struct mlx5hws_matche= r *matcher) } =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) { - obj_id =3D mlx5hws_pool_get_base_mirror_id( - matcher->match_ste.pool); - rtc_attr.ste_base =3D obj_id; + rtc_attr.ste_base =3D matcher->match_ste.ste_1_base; rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, true= ); =20 obj_id =3D mlx5hws_pool_get_base_mirror_id(ctx->stc_pool); @@ -588,21 +584,6 @@ hws_matcher_check_attr_sz(struct mlx5hws_cmd_query_cap= s *caps, return 0; } =20 -static void hws_matcher_set_pool_attr(struct mlx5hws_pool_attr *attr, - struct mlx5hws_matcher *matcher) -{ - switch (matcher->attr.optimize_flow_src) { - case MLX5HWS_MATCHER_FLOW_SRC_VPORT: - attr->opt_type =3D MLX5HWS_POOL_OPTIMIZE_ORIG; - break; - case MLX5HWS_MATCHER_FLOW_SRC_WIRE: - attr->opt_type =3D MLX5HWS_POOL_OPTIMIZE_MIRROR; - break; - default: - break; - } -} - static int hws_matcher_check_and_process_at(struct mlx5hws_matcher *matche= r, struct mlx5hws_action_template *at) { @@ -683,8 +664,8 @@ static void hws_matcher_set_ip_version_match(struct mlx= 5hws_matcher *matcher) =20 static int hws_matcher_bind_mt(struct mlx5hws_matcher *matcher) { + struct mlx5hws_cmd_ste_create_attr ste_attr =3D {}; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; - struct mlx5hws_pool_attr pool_attr =3D {0}; int ret; =20 /* Calculate match, range and hash definers */ @@ -699,22 +680,39 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher= *matcher) =20 hws_matcher_set_ip_version_match(matcher); =20 - /* Create an STE pool per matcher*/ - pool_attr.table_type =3D matcher->tbl->type; - pool_attr.pool_type =3D MLX5HWS_POOL_TYPE_STE; - pool_attr.alloc_log_sz =3D matcher->attr.table.sz_col_log + - matcher->attr.table.sz_row_log; - hws_matcher_set_pool_attr(&pool_attr, matcher); - - matcher->match_ste.pool =3D mlx5hws_pool_create(ctx, &pool_attr); - if (!matcher->match_ste.pool) { - mlx5hws_err(ctx, "Failed to allocate matcher STE pool\n"); - ret =3D -EOPNOTSUPP; + /* Create an STE range each for RX and TX. */ + ste_attr.table_type =3D FS_FT_FDB_RX; + ste_attr.log_obj_range =3D + matcher->attr.optimize_flow_src =3D=3D + MLX5HWS_MATCHER_FLOW_SRC_VPORT ? + 0 : matcher->attr.table.sz_col_log + + matcher->attr.table.sz_row_log; + + ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, + &matcher->match_ste.ste_0_base); + if (ret) { + mlx5hws_err(ctx, "Failed to allocate RX STE range (%d)\n", ret); goto uninit_match_definer; } =20 + ste_attr.table_type =3D FS_FT_FDB_TX; + ste_attr.log_obj_range =3D + matcher->attr.optimize_flow_src =3D=3D + MLX5HWS_MATCHER_FLOW_SRC_WIRE ? + 0 : matcher->attr.table.sz_col_log + + matcher->attr.table.sz_row_log; + + ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, + &matcher->match_ste.ste_1_base); + if (ret) { + mlx5hws_err(ctx, "Failed to allocate TX STE range (%d)\n", ret); + goto destroy_rx_ste_range; + } + return 0; =20 +destroy_rx_ste_range: + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_0_base); uninit_match_definer: if (!(matcher->flags & MLX5HWS_MATCHER_FLAGS_COLLISION)) mlx5hws_definer_mt_uninit(ctx, matcher->mt); @@ -723,9 +721,12 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher = *matcher) =20 static void hws_matcher_unbind_mt(struct mlx5hws_matcher *matcher) { - mlx5hws_pool_destroy(matcher->match_ste.pool); + struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_1_base); + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_0_base); if (!(matcher->flags & MLX5HWS_MATCHER_FLAGS_COLLISION)) - mlx5hws_definer_mt_uninit(matcher->tbl->ctx, matcher->mt); + mlx5hws_definer_mt_uninit(ctx, matcher->mt); } =20 static int diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h index 32e83cddcd60..ae20bcebfdde 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h @@ -48,7 +48,8 @@ struct mlx5hws_match_template { struct mlx5hws_matcher_match_ste { u32 rtc_0_id; u32 rtc_1_id; - struct mlx5hws_pool *pool; + u32 ste_0_base; + u32 ste_1_base; }; =20 enum { --=20 2.34.1