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charset="utf-8" The CSID in sa8775p is version 690, This csid is different from csid 780 w.r.t few bit-fields. Co-developed-by: Suresh Vankadara Signed-off-by: Suresh Vankadara Signed-off-by: Vikram Sharma --- .../platform/qcom/camss/camss-csid-gen3.c | 31 +++- drivers/media/platform/qcom/camss/camss.c | 151 ++++++++++++++++++ 2 files changed, 175 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 0941152ec301..f62084fb8287 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -47,8 +47,12 @@ #define CSID_CSI2_RX_IRQ_CLEAR 0xA4 #define CSID_CSI2_RX_IRQ_SET 0xA8 =20 +#define IS_CSID_690(csid) (csid->camss->res->version =3D=3D\ + CAMSS_8775P ? true : false) #define CSID_BUF_DONE_IRQ_STATUS 0x8C -#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 14) +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ?\ + 1 : (IS_CSID_690(csid) ?\ + 13 : 14)) #define CSID_BUF_DONE_IRQ_MASK 0x90 #define CSID_BUF_DONE_IRQ_CLEAR 0x94 #define CSID_BUF_DONE_IRQ_SET 0x98 @@ -61,6 +65,7 @@ =20 #define CSID_CSI2_RX_CFG0 0x200 #define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_VC_MODE 3 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 =20 @@ -68,7 +73,9 @@ #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) #define CSI2_RX_CFG1_VC_MODE BIT(2) =20 -#define CSID_RDI_CFG0(rdi) (0x500 + 0x100 * (rdi)) +#define CSID_RDI_CFG0(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ + (0x300 + 0x100 * (rdi)) :\ + (0x500 + 0x100 * (rdi))) #define RDI_CFG0_TIMESTAMP_EN BIT(6) #define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) #define RDI_CFG0_DECODE_FORMAT 12 @@ -77,10 +84,14 @@ #define RDI_CFG0_DT_ID 27 #define RDI_CFG0_EN BIT(31) =20 -#define CSID_RDI_CTRL(rdi) (0x504 + 0x100 * (rdi)) +#define CSID_RDI_CTRL(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ + (0x304 + 0x100 * (rdi)) :\ + (0x504 + 0x100 * (rdi))) #define RDI_CTRL_START_CMD BIT(0) =20 -#define CSID_RDI_CFG1(rdi) (0x510 + 0x100 * (rdi)) +#define CSID_RDI_CFG1(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ + (0x310 + 0x100 * (rdi)) :\ + (0x510 + 0x100 * (rdi))) #define RDI_CFG1_DROP_H_EN BIT(5) #define RDI_CFG1_DROP_V_EN BIT(6) #define RDI_CFG1_CROP_H_EN BIT(7) @@ -88,9 +99,12 @@ #define RDI_CFG1_PIX_STORE BIT(10) #define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) =20 -#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (0x548 + 0x100 * (rdi)) -#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (0x54C + 0x100 * (rdi)) - +#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (csid_is_lite(csid) && IS_CSID= _690(csid) ?\ + (0x348 + 0x100 * (rdi)) :\ + (0x548 + 0x100 * (rdi))) +#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_= 690(csid) ?\ + (0x34C + 0x100 * (rdi)) :\ + (0x54C + 0x100 * (rdi))) #define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 =20 static void __csid_configure_rx(struct csid_device *csid, @@ -102,6 +116,9 @@ static void __csid_configure_rx(struct csid_device *csi= d, val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0= _PHY_NUM_SEL; =20 + if (IS_CSID_690(csid) && (vc > 3)) + val |=3D 1 << CSI2_RX_CFG0_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index ebc3b296bb50..b2398196b9ff 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2269,6 +2269,10 @@ static const struct camss_subdev_resources csiphy_re= s_8550[] =3D { } }; =20 +static const struct resources_wrapper csid_wrapper_res_sa8775p =3D { + .reg =3D "csid_wrapper", +}; + static const struct resources_wrapper csid_wrapper_res_sm8550 =3D { .reg =3D "csid_wrapper", }; @@ -2558,6 +2562,153 @@ static const struct camss_subdev_resources csiphy_r= es_8775p[] =3D { }, }; =20 +static const struct camss_subdev_resources csid_res_8775p[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + + .clock =3D { "csid", "csiphy_rx"}, + .clock_rate =3D { + { 400000000, 400000000}, + { 400000000, 400000000} + }, + + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .is_lite =3D false, + .hw_ops =3D &csid_ops_gen3, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators =3D {}, + + .clock =3D { "csid", "csiphy_rx"}, + .clock_rate =3D { + { 400000000, 400000000}, + { 400000000, 400000000} + }, + + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .is_lite =3D false, + .hw_ops =3D &csid_ops_gen3, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + + /* CSID2 (lite) */ + { + .regulators =3D {}, + + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 400000000, 400000000, 0}, + { 0, 0, 400000000, 480000000, 0} + }, + + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_gen3, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID3 (lite) */ + { + .regulators =3D {}, + + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 400000000, 400000000, 0}, + { 0, 0, 400000000, 480000000, 0} + }, + + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_gen3, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID4 (lite) */ + { + .regulators =3D {}, + + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 400000000, 400000000, 0}, + { 0, 0, 400000000, 480000000, 0} + }, + + .reg =3D { "csid_lite2" }, + .interrupt =3D { "csid_lite2" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_gen3, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID5 (lite) */ + { + .regulators =3D {}, + + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 400000000, 400000000, 0}, + { 0, 0, 400000000, 480000000, 0} + }, + + .reg =3D { "csid_lite3" }, + .interrupt =3D { "csid_lite3" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_gen3, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID6 (lite) */ + { + .regulators =3D {}, + + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 400000000, 400000000, 0}, + { 0, 0, 400000000, 480000000, 0} + }, + + .reg =3D { "csid_lite4" }, + .interrupt =3D { "csid_lite4" }, + .csid =3D { + .is_lite =3D true, + .hw_ops =3D &csid_ops_gen3, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .formats =3D &csid_formats_gen2 + } + }, +}; + static const struct resources_icc icc_res_sa8775p[] =3D { { .name =3D "ahb", --=20 2.25.1