From nobody Wed Oct 8 00:37:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F1BE15C0; Thu, 3 Jul 2025 15:37:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751557057; cv=none; b=GitUZk0Zl1aSfW6T1TlZpH+PzGG9hMopBPDxX/CXuvbx9hc93CNyCl6gRSiPazqV4YaPPUzkbmJLlkdo/RC+h91DOq9/lOEWiGvWK1g//RM6I76LJLKw6sWHk1ADKj/ovCTH0SXakqdGNX1MVk6JV7uqF/OWlFEqRrfWUD7LBwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751557057; c=relaxed/simple; bh=2ZYiW9QKD/NNQXX4mTs5dc+Ov1mBPfARjMAo7zKsIJc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BvVrGHcCJKAoMNLhNHW83QRIvDyQEt2ruUBO+Mz51k24ThO1LDE16pFCiole7ANmKro7O4+tYtV34zI82caHKNqThyvZMDxkNF9jp2vQMmf2eTBAbmqWdIaTeGSaFoF1Asm7I4Ge5GY/DAI9qLkNLmw6OovXsStEEQu/O/DtpUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YiouNkfX; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YiouNkfX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751557057; x=1783093057; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2ZYiW9QKD/NNQXX4mTs5dc+Ov1mBPfARjMAo7zKsIJc=; b=YiouNkfX6neK5AOxjGt4v0UVuG6ngpGfEhmOMSiN0DgcXcXfZqzrOYGa 6SFoACkLsJHi8J3BQdl+EMYNMh2a9UdVIlbT5sKXavrt2fC+3lvEuLoYQ Ei4atBksnajNVuS5WTM7cJoEXTStLNMfCEOv7APeVeLFdQBWXAQbTc51K bP5WMch8ig5Px15fEq3IS8e/hkNA2eHaKLWyrln3sMED3F+d95l16MYiF tyak5HCGyrTHZfZ4OuKlb7nZ1Z0kQHgg3LtnTA/yohyXIokjwTNVnGp7d oHO+4HrBMiEuwOrgls5Gx7bRRG/uyq8ZkQYf+VgPm1tEVb9VEVabMnwOB g==; X-CSE-ConnectionGUID: BCPN44LNSRGwf4BZeRI8kQ== X-CSE-MsgGUID: RLo4haxEQGydO6p6XhTDsw== X-IronPort-AV: E=McAfee;i="6800,10657,11483"; a="76436672" X-IronPort-AV: E=Sophos;i="6.16,284,1744095600"; d="scan'208";a="76436672" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 08:37:36 -0700 X-CSE-ConnectionGUID: JehsTHjLSkm0b3aoPdXJPQ== X-CSE-MsgGUID: J8mRqbpURguS7di2CeBU3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,284,1744095600"; d="scan'208";a="178065105" Received: from johunt-mobl9.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.244.86]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 08:37:30 -0700 From: Adrian Hunter To: Dave Hansen , pbonzini@redhat.com, seanjc@google.com, vannapurve@google.com Cc: Tony Luck , Borislav Petkov , Thomas Gleixner , Ingo Molnar , x86@kernel.org, H Peter Anvin , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rick.p.edgecombe@intel.com, kirill.shutemov@linux.intel.com, kai.huang@intel.com, reinette.chatre@intel.com, xiaoyao.li@intel.com, tony.lindgren@linux.intel.com, binbin.wu@linux.intel.com, isaku.yamahata@intel.com, yan.y.zhao@intel.com, chao.gao@intel.com Subject: [PATCH V2 1/2] x86/tdx: Eliminate duplicate code in tdx_clear_page() Date: Thu, 3 Jul 2025 18:37:11 +0300 Message-ID: <20250703153712.155600-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250703153712.155600-1-adrian.hunter@intel.com> References: <20250703153712.155600-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" tdx_clear_page() and reset_tdx_pages() duplicate the TDX page clearing logic. Rename reset_tdx_pages() to tdx_quirk_reset_paddr() and use it in place of tdx_clear_page(). Signed-off-by: Adrian Hunter Acked-by: Kai Huang Reviewed-by: Binbin Wu Reviewed-by: Kirill A. Shutemov Reviewed-by: Xiaoyao Li --- Changes in V2: Rename reset_tdx_pages() to tdx_quirk_reset_paddr() Call tdx_quirk_reset_paddr() directly arch/x86/include/asm/tdx.h | 2 ++ arch/x86/kvm/vmx/tdx.c | 25 +++---------------------- arch/x86/virt/vmx/tdx/tdx.c | 5 +++-- 3 files changed, 8 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 7ddef3a69866..f66328404724 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -131,6 +131,8 @@ int tdx_guest_keyid_alloc(void); u32 tdx_get_nr_guest_keyids(void); void tdx_guest_keyid_free(unsigned int keyid); =20 +void tdx_quirk_reset_paddr(unsigned long base, unsigned long size); + struct tdx_td { /* TD root structure: */ struct page *tdr_page; diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index a08e7055d1db..031e36665757 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -276,25 +276,6 @@ static inline void tdx_disassociate_vp(struct kvm_vcpu= *vcpu) vcpu->cpu =3D -1; } =20 -static void tdx_clear_page(struct page *page) -{ - const void *zero_page =3D (const void *) page_to_virt(ZERO_PAGE(0)); - void *dest =3D page_to_virt(page); - unsigned long i; - - /* - * The page could have been poisoned. MOVDIR64B also clears - * the poison bit so the kernel can safely use the page again. - */ - for (i =3D 0; i < PAGE_SIZE; i +=3D 64) - movdir64b(dest + i, zero_page); - /* - * MOVDIR64B store uses WC buffer. Prevent following memory reads - * from seeing potentially poisoned cache. - */ - __mb(); -} - static void tdx_no_vcpus_enter_start(struct kvm *kvm) { struct kvm_tdx *kvm_tdx =3D to_kvm_tdx(kvm); @@ -340,7 +321,7 @@ static int tdx_reclaim_page(struct page *page) =20 r =3D __tdx_reclaim_page(page); if (!r) - tdx_clear_page(page); + tdx_quirk_reset_paddr(page_to_phys(page), PAGE_SIZE); return r; } =20 @@ -589,7 +570,7 @@ static void tdx_reclaim_td_control_pages(struct kvm *kv= m) pr_tdx_error(TDH_PHYMEM_PAGE_WBINVD, err); return; } - tdx_clear_page(kvm_tdx->td.tdr_page); + tdx_quirk_reset_paddr(page_to_phys(kvm_tdx->td.tdr_page), PAGE_SIZE); =20 __free_page(kvm_tdx->td.tdr_page); kvm_tdx->td.tdr_page =3D NULL; @@ -1689,7 +1670,7 @@ static int tdx_sept_drop_private_spte(struct kvm *kvm= , gfn_t gfn, pr_tdx_error(TDH_PHYMEM_PAGE_WBINVD, err); return -EIO; } - tdx_clear_page(page); + tdx_quirk_reset_paddr(page_to_phys(page), PAGE_SIZE); tdx_unpin(kvm, page); return 0; } diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index c7a9a087ccaf..14d93ed05bd2 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -637,7 +637,7 @@ static int tdmrs_set_up_pamt_all(struct tdmr_info_list = *tdmr_list, * clear these pages. Note this function doesn't flush cache of * these TDX private pages. The caller should make sure of that. */ -static void reset_tdx_pages(unsigned long base, unsigned long size) +void tdx_quirk_reset_paddr(unsigned long base, unsigned long size) { const void *zero_page =3D (const void *)page_address(ZERO_PAGE(0)); unsigned long phys, end; @@ -653,10 +653,11 @@ static void reset_tdx_pages(unsigned long base, unsig= ned long size) */ mb(); } +EXPORT_SYMBOL_GPL(tdx_quirk_reset_paddr); =20 static void tdmr_reset_pamt(struct tdmr_info *tdmr) { - tdmr_do_pamt_func(tdmr, reset_tdx_pages); + tdmr_do_pamt_func(tdmr, tdx_quirk_reset_paddr); } =20 static void tdmrs_reset_pamt_all(struct tdmr_info_list *tdmr_list) --=20 2.48.1 From nobody Wed Oct 8 00:37:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 581EA2E7620; Thu, 3 Jul 2025 15:37:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="76436688" X-IronPort-AV: E=Sophos;i="6.16,284,1744095600"; d="scan'208";a="76436688" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 08:37:41 -0700 X-CSE-ConnectionGUID: gJjfCQoiS1iD0sYiLVRShw== X-CSE-MsgGUID: UJtWWCbCRqaaihgUssbEhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,284,1744095600"; d="scan'208";a="178065127" Received: from johunt-mobl9.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.244.86]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 08:37:36 -0700 From: Adrian Hunter To: Dave Hansen , pbonzini@redhat.com, seanjc@google.com, vannapurve@google.com Cc: Tony Luck , Borislav Petkov , Thomas Gleixner , Ingo Molnar , x86@kernel.org, H Peter Anvin , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rick.p.edgecombe@intel.com, kirill.shutemov@linux.intel.com, kai.huang@intel.com, reinette.chatre@intel.com, xiaoyao.li@intel.com, tony.lindgren@linux.intel.com, binbin.wu@linux.intel.com, isaku.yamahata@intel.com, yan.y.zhao@intel.com, chao.gao@intel.com Subject: [PATCH V2 2/2] x86/tdx: Skip clearing reclaimed pages unless X86_BUG_TDX_PW_MCE is present Date: Thu, 3 Jul 2025 18:37:12 +0300 Message-ID: <20250703153712.155600-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250703153712.155600-1-adrian.hunter@intel.com> References: <20250703153712.155600-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Avoid clearing reclaimed TDX private pages unless the platform is affected by the X86_BUG_TDX_PW_MCE erratum. This significantly reduces VM shutdown time on unaffected systems. Background KVM currently clears reclaimed TDX private pages using MOVDIR64B, which: - Clears the TD Owner bit (which identifies TDX private memory) and integrity metadata without triggering integrity violations. - Clears poison from cache lines without consuming it, avoiding MCEs on access (refer TDX Module Base spec. 16.5. Handling Machine Check Events during Guest TD Operation). The TDX module also uses MOVDIR64B to initialize private pages before use. If cache flushing is needed, it sets TDX_FEATURES.CLFLUSH_BEFORE_ALLOC. However, KVM currently flushes unconditionally, refer commit 94c477a751c7b ("x86/virt/tdx: Add SEAMCALL wrappers to add TD private pages") In contrast, when private pages are reclaimed, the TDX Module handles flushing via the TDH.PHYMEM.CACHE.WB SEAMCALL. Problem Clearing all private pages during VM shutdown is costly. For guests with a large amount of memory it can take minutes. Solution TDX Module Base Architecture spec. documents that private pages reclaimed from a TD should be initialized using MOVDIR64B, in order to avoid integrity violation or TD bit mismatch detection when later being read using a shared HKID, refer April 2025 spec. "Page Initialization" in section "8.6.2. Platforms not Using ACT: Required Cache Flush and Initialization by the Host VMM" That is an overstatement and will be clarified in coming versions of the spec. In fact, as outlined in "Table 16.2: Non-ACT Platforms Checks on Memory" and "Table 16.3: Non-ACT Platforms Checks on Memory Reads in Li Mode" in the same spec, there is no issue accessing such reclaimed pages using a shared key that does not have integrity enabled. Linux always uses KeyID 0 which never has integrity enabled. KeyID 0 is also the TME KeyID which disallows integrity, refer "TME Policy/Encryption Algorithm" bit description in "Intel Architecture Memory Encryption Technologies" spec version 1.6 April 2025. So there is no need to clear pages to avoid integrity violations. There remains a risk of poison consumption. However, in the context of TDX, it is expected that there would be a machine check associated with the original poisoning. On some platforms that results in a panic. However platforms may support "SEAM_NR" Machine Check capability, in which case Linux machine check handler marks the page as poisoned, which prevents it from being allocated anymore, refer commit 7911f145de5fe ("x86/mce: Implement recovery for errors in TDX/SEAM non-root mode") Improvement By skipping the clearing step on unaffected platforms, shutdown time can improve by up to 40%. On platforms with the X86_BUG_TDX_PW_MCE erratum (SPR and EMR), continue clearing because these platforms may trigger poison on partial writes to previously-private pages, even with KeyID 0, refer commit 1e536e1068970 ("x86/cpu: Detect TDX partial write machine check erratum") Signed-off-by: Adrian Hunter Acked-by: Kai Huang Reviewed-by: Kirill A. Shutemov --- Changes in V2: Improve the comment arch/x86/virt/vmx/tdx/tdx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 14d93ed05bd2..4fa86188aa40 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -642,6 +642,14 @@ void tdx_quirk_reset_paddr(unsigned long base, unsigne= d long size) const void *zero_page =3D (const void *)page_address(ZERO_PAGE(0)); unsigned long phys, end; =20 + /* + * Typically, any write to the page will convert it from TDX + * private back to normal kernel memory. Systems with the + * erratum need to do the conversion explicitly. + */ + if (!boot_cpu_has_bug(X86_BUG_TDX_PW_MCE)) + return; + end =3D base + size; for (phys =3D base; phys < end; phys +=3D 64) movdir64b(__va(phys), zero_page); --=20 2.48.1