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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 8/8] arm64: dts: allwinner: A523: Add thermal sensors and zones Date: Thu, 3 Jul 2025 23:11:32 +0800 Message-ID: <20250703151132.2642378-9-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mikhail Kalashnikov The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM. THS1 does have 3 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu Add the thermal sensor configuration and the thermal zones. Trips temperature, polling-delay and sustainable-power parameters are deriv= ed from the manufacturer's BSP. Signed-off-by: Mikhail Kalashnikov --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 295292d67..a1304c55c 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&gic>; @@ -22,6 +23,7 @@ cpu0: cpu@0 { device_type =3D "cpu"; reg =3D <0x000>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu1: cpu@100 { @@ -29,6 +31,7 @@ cpu1: cpu@100 { device_type =3D "cpu"; reg =3D <0x100>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu2: cpu@200 { @@ -36,6 +39,7 @@ cpu2: cpu@200 { device_type =3D "cpu"; reg =3D <0x200>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu3: cpu@300 { @@ -43,6 +47,7 @@ cpu3: cpu@300 { device_type =3D "cpu"; reg =3D <0x300>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu4: cpu@400 { @@ -50,6 +55,7 @@ cpu4: cpu@400 { device_type =3D "cpu"; reg =3D <0x400>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu5: cpu@500 { @@ -57,6 +63,7 @@ cpu5: cpu@500 { device_type =3D "cpu"; reg =3D <0x500>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu6: cpu@600 { @@ -64,6 +71,7 @@ cpu6: cpu@600 { device_type =3D "cpu"; reg =3D <0x600>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; =20 cpu7: cpu@700 { @@ -71,6 +79,7 @@ cpu7: cpu@700 { device_type =3D "cpu"; reg =3D <0x700>; enable-method =3D "psci"; + #cooling-cells =3D <2>; }; }; =20 @@ -181,12 +190,46 @@ ccu: clock-controller@2001000 { #reset-cells =3D <1>; }; =20 + ths1: thermal-sensor@2009400 { + compatible =3D "allwinner,sun55i-a523-ths1"; + reg =3D <0x02009400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; + clock-names =3D "bus", "gpadc"; + resets =3D <&ccu RST_BUS_THS>; + nvmem-cells =3D <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names =3D "calibration", + "calibration-second-part"; + #thermal-sensor-cells =3D <1>; + }; + + ths0: thermal-sensor@200a000 { + compatible =3D "allwinner,sun55i-a523-ths0"; + reg =3D <0x0200a000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>; + clock-names =3D "bus", "gpadc"; + resets =3D <&ccu RST_BUS_THS>; + nvmem-cells =3D <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names =3D "calibration", + "calibration-second-part"; + #thermal-sensor-cells =3D <0>; + }; + sid: efuse@3006000 { compatible =3D "allwinner,sun55i-a523-sid", "allwinner,sun50i-a64-sid"; reg =3D <0x03006000 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + + ths_calibration0: ths-calibration0@38 { + reg =3D <0x38 0x8>; + }; + + ths_calibration1: ths-calibration1@44 { + reg =3D <0x44 0x8>; + }; }; =20 mmc0: mmc@4020000 { @@ -644,4 +687,115 @@ rtc: rtc@7090000 { #clock-cells =3D <1>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <1000>; + thermal-sensors =3D <&ths1 1>; + sustainable-power =3D <1200>; + + trips { + cpu0_threshold: cpu-trip-0 { + temperature =3D <70000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + cpu0_target: cpu-trip-1 { + temperature =3D <90000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + cpu0_critical: cpu-trip-2 { + temperature =3D <110000>; + type =3D "critical"; + hysteresis =3D <0>; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu0_target>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4_thermal: cpu4-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <1000>; + thermal-sensors =3D <&ths1 0>; + sustainable-power =3D <1600>; + + trips { + cpu4_threshold: cpu-trip-0 { + temperature =3D <70000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + cpu4_target: cpu-trip-1 { + temperature =3D <90000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + cpu4_critical: cpu-trip-2 { + temperature =3D <110000>; + type =3D "critical"; + hysteresis =3D <0>; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu4_target>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <1000>; + thermal-sensors =3D <&ths1 2>; + sustainable-power =3D <2400>; + + gpu-trips { + gpu_temp_threshold: gpu-trip-0 { + temperature =3D <60000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + gpu_temp_target: gpu-trip-1 { + temperature =3D <90000>; + type =3D "passive"; + hysteresis =3D <0>; + }; + gpu_temp_critical: gpu-trip-2 { + temperature =3D <110000>; + type =3D "critical"; + hysteresis =3D <0>; + }; + }; + }; + + ddr-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&ths0>; + + trips { + ddr_temp_critical: ddr-trip-0 { + temperature =3D <110000>; + type =3D "critical"; + hysteresis =3D <0>; + }; + }; + }; + }; }; --=20 2.49.0