From nobody Tue Feb 10 09:11:02 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3BCB2E7F21; Thu, 3 Jul 2025 14:11:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751551915; cv=none; b=uu6uRG4WqsthLfbDddWge06X0f33DwMCNg9CQTXrp555SJGtjwGeOJZwOV4SSjwITy8J6+KdqDfn9rpip0sHfcNFZdyxOTBjQTDHB2j73UupzJH9Jw2+w0/Oh9PeHiMmi5A173x5GlsP3Mk54NEnEQxrkY1+jVIiC+zIMnnFNEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751551915; c=relaxed/simple; bh=drUM3Xkn3wXyic08nt+xAscSRk+ZSNHceFGvcO5x5dw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JagT76AUVmAA66nNDD+EOi8c6UuBx5ert5+pMwmgDgjsxjHl/i/ZdeiJquKu1WJId4q7pXPUWSWPN3tRlfhMZPAjd10fy9YoiQt5cz9ygI3sISnLQqpaRXVISjQQEDvSDVq2ya6AShcsJodbhw5EVrpKUtbUwOLaYwT3ySZX9sE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=VSPyGbow; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="VSPyGbow" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1751551912; bh=drUM3Xkn3wXyic08nt+xAscSRk+ZSNHceFGvcO5x5dw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VSPyGbowCI4M7Kk2GY0AKDNrA2Y6U8c76ww13SoARjJJPk4ixyby/rl//Qt0KnwG5 2YOgx3RMIPazuPl15g6YnQCJ0wPt58bg7HpfyxlQ30NYW57E/n7ODc5TqPxLYKvIkT uxgavlocCRZ7d+BZ6FhU31w+JbWTiA7HkPgpR0Xc+25BaX+SkQlyroqZw4G/Wa+vIF FUdGSlv732YvkwzLPNEVMoRY5L8Ibj5E+zDrJQuTJxFZkw9Di36YwgM18qBxcmNRjh cs3JyTMM6j3J8obQKApqrh2wjqvarqI6MFp+Ozk9jD/swx4PY+y6wnxEmt+NNROrUf epV8YB0RPsfHw== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 488FE17E0EBD; Thu, 3 Jul 2025 16:11:51 +0200 (CEST) From: AngeloGioacchino Del Regno To: jic23@kernel.org Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v2 3/6] iio: adc: mt6359: Add ready register index and mask to channel data Date: Thu, 3 Jul 2025 16:11:43 +0200 Message-ID: <20250703141146.171431-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703141146.171431-1-angelogioacchino.delregno@collabora.com> References: <20250703141146.171431-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In preparation for adding support for the AUXADC block found in the MT6363 PMIC, add the ready register index and mask to the mtk_pmic_auxadc_chan structure, populate those in the channel description for all of the already supported SoCs and make use of them in the .read_imp() callbacks. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/iio/adc/mt6359-auxadc.c | 118 ++++++++++++++++++-------------- 1 file changed, 65 insertions(+), 53 deletions(-) diff --git a/drivers/iio/adc/mt6359-auxadc.c b/drivers/iio/adc/mt6359-auxad= c.c index eecf88b05c6f..2ccc64e6c126 100644 --- a/drivers/iio/adc/mt6359-auxadc.c +++ b/drivers/iio/adc/mt6359-auxadc.c @@ -101,12 +101,16 @@ struct mt6359_auxadc { * struct mtk_pmic_auxadc_chan - PMIC AUXADC channel data * @req_idx: Request register number * @req_mask: Bitmask to activate a channel + * @rdy_idx: Readiness register number + * @rdy_mask: Bitmask to determine channel readiness * @num_samples: Number of AUXADC samples for averaging * @r_ratio: Resistance ratio fractional */ struct mtk_pmic_auxadc_chan { u8 req_idx; u16 req_mask; + u8 rdy_idx; + u16 rdy_mask; u16 num_samples; struct u8_fract r_ratio; }; @@ -130,13 +134,17 @@ struct mtk_pmic_auxadc_info { const u16 *regs; u16 sec_unlock_key; u8 imp_adc_num; - int (*read_imp)(struct mt6359_auxadc *adc_dev, int *vbat, int *ibat); + int (*read_imp)(struct mt6359_auxadc *adc_dev, + const struct iio_chan_spec *chan, int *vbat, int *ibat); }; =20 -#define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _samples, _rnum, _r= div) \ +#define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit,= \ + _samples, _rnum, _rdiv) \ [PMIC_AUXADC_CHAN_##_ch_idx] =3D { \ .req_idx =3D _req_idx, \ .req_mask =3D BIT(_req_bit), \ + .rdy_idx =3D _rdy_idx, \ + .rdy_mask =3D BIT(_rdy_bit), \ .num_samples =3D _samples, \ .r_ratio =3D { _rnum, _rdiv } \ } @@ -177,21 +185,21 @@ static const struct iio_chan_spec mt6357_auxadc_chann= els[] =3D { }; =20 static const struct mtk_pmic_auxadc_chan mt6357_auxadc_ch_desc[] =3D { - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 3, 1), - MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, 128, 3, 1), - MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, 8, 1, 1), - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 1, 1), - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, 8, 1, 1), + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128,= 3, 1), + MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128,= 3, 1), + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, = 1), + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8,= 1, 1), + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8= , 1, 1), + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1= , 1), + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 12= 8, 1, 1), + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 2= 56, 1, 1), + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, = 16, 1, 1), + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 1,= 1), + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), =20 /* Battery impedance channels */ - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 3, 1), + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1), }; =20 static const u16 mt6357_auxadc_regs[] =3D { @@ -224,22 +232,22 @@ static const struct iio_chan_spec mt6358_auxadc_chann= els[] =3D { }; =20 static const struct mtk_pmic_auxadc_chan mt6358_auxadc_ch_desc[] =3D { - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 3, 1), - MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, 8, 1, 1), - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 2, 1), - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, 8, 3, 2), - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 2, 1), - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, 8, 1, 1), + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128,= 3, 1), + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, = 1), + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8,= 2, 1), + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8= , 1, 1), + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1= , 1), + MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP0, 8, 8, 3,= 2), + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 12= 8, 1, 1), + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 2= 56, 1, 1), + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, = 16, 1, 1), + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 2,= 1), + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), =20 /* Battery impedance channels */ - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 7, 2), + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 7, 2), }; =20 static const u16 mt6358_auxadc_regs[] =3D { @@ -272,22 +280,22 @@ static const struct iio_chan_spec mt6359_auxadc_chann= els[] =3D { }; =20 static const struct mtk_pmic_auxadc_chan mt6359_auxadc_ch_desc[] =3D { - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 7, 2), - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 5, 2), - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, 8, 3, 2), - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 5, 2), - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, 8, 1, 1), + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP1, 15, 128= , 7, 2), + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP1, 15, 8= , 5, 2), + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP1, 15, = 8, 1, 1), + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15 ,8, = 1, 1), + MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP1, 15, 8, 3= , 2), + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP1, 15, 1= 28, 1, 1), + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP1, 15, = 256, 1, 1), + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP1, 15,= 16, 1, 1), + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP1, 15, 8, 5= , 2), + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP1, 15,= 8, 1, 1), + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP1, 15,= 8, 1, 1), + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP1, 15,= 8, 1, 1), =20 /* Battery impedance channels */ - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 7, 2), - MTK_PMIC_ADC_CHAN(IBAT, 0, 0, 128, 7, 2), + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), + MTK_PMIC_ADC_CHAN(IBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2), }; =20 static const u16 mt6359_auxadc_regs[] =3D { @@ -313,9 +321,10 @@ static void mt6358_stop_imp_conv(struct mt6359_auxadc = *adc_dev) regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK= _SW_EN); } =20 -static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev) +static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev, const stru= ct iio_chan_spec *chan) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; + const struct mtk_pmic_auxadc_chan *desc =3D &cinfo->desc[chan->scan_index= ]; struct regmap *regmap =3D adc_dev->regmap; u32 val; int ret; @@ -323,8 +332,8 @@ static int mt6358_start_imp_conv(struct mt6359_auxadc *= adc_dev) regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_S= W_EN); regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTORE= PEAT_EN); =20 - ret =3D regmap_read_poll_timeout(adc_dev->regmap, cinfo->regs[PMIC_AUXADC= _IMP0], - val, val & MT6358_IMP0_IRQ_RDY, + ret =3D regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], + val, val & desc->rdy_mask, IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); if (ret) { mt6358_stop_imp_conv(adc_dev); @@ -334,7 +343,8 @@ static int mt6358_start_imp_conv(struct mt6359_auxadc *= adc_dev) return 0; } =20 -static int mt6358_read_imp(struct mt6359_auxadc *adc_dev, int *vbat, int *= ibat) +static int mt6358_read_imp(struct mt6359_auxadc *adc_dev, + const struct iio_chan_spec *chan, int *vbat, int *ibat) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; struct regmap *regmap =3D adc_dev->regmap; @@ -342,7 +352,7 @@ static int mt6358_read_imp(struct mt6359_auxadc *adc_de= v, int *vbat, int *ibat) u32 val_v; int ret; =20 - ret =3D mt6358_start_imp_conv(adc_dev); + ret =3D mt6358_start_imp_conv(adc_dev, chan); if (ret) return ret; =20 @@ -359,17 +369,19 @@ static int mt6358_read_imp(struct mt6359_auxadc *adc_= dev, int *vbat, int *ibat) return 0; } =20 -static int mt6359_read_imp(struct mt6359_auxadc *adc_dev, int *vbat, int *= ibat) +static int mt6359_read_imp(struct mt6359_auxadc *adc_dev, + const struct iio_chan_spec *chan, int *vbat, int *ibat) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; + const struct mtk_pmic_auxadc_chan *desc =3D &cinfo->desc[chan->scan_index= ]; struct regmap *regmap =3D adc_dev->regmap; u32 val, val_v, val_i; int ret; =20 /* Start conversion */ regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6359_IMP0_CONV_EN); - ret =3D regmap_read_poll_timeout(regmap, cinfo->regs[PMIC_AUXADC_IMP1], - val, val & MT6359_IMP1_IRQ_RDY, + ret =3D regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], + val, val & desc->rdy_mask, IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); =20 /* Stop conversion regardless of the result */ @@ -506,10 +518,10 @@ static int mt6359_auxadc_read_raw(struct iio_dev *ind= io_dev, scoped_guard(mutex, &adc_dev->lock) { switch (chan->scan_index) { case PMIC_AUXADC_CHAN_IBAT: - ret =3D adc_dev->chip_info->read_imp(adc_dev, NULL, val); + ret =3D adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val); break; case PMIC_AUXADC_CHAN_VBAT: - ret =3D adc_dev->chip_info->read_imp(adc_dev, val, NULL); + ret =3D adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL); break; default: ret =3D mt6359_auxadc_read_adc(adc_dev, chan, val); --=20 2.49.0