From nobody Wed Oct 8 04:09:24 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A5AC298CBC; Thu, 3 Jul 2025 11:58:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751543929; cv=none; b=I+m1qMQjZN1MqU5IJ489emO8Vm/OnO2hpg7hR3B6Disljpd1OIvPXSHwOlobQLsnehgCRxIJg0vtFCNdfJ8CZnenosCpCZVS+zTFheQEow6oyV0LD9ImM0o/1InETKqp0eq/V7i2iXVXHe4rNWxJEDywCTOiZQFiOp7khZzMgxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751543929; c=relaxed/simple; bh=gKPq2547ARTVgOSdR2UTZsF7CVdcjQ30QSsT719lHUk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NhiNIOrsqWt56Y4tuNUDMVNr6SD2Q5+pnlsiQlvUxBIt79Y5T0o3iliXrvDkKWZxbxu0XuaSsJdNuujPaVjRP8APvIIP8pbMhvnq3Qj7FQ+9jAs1bERCYkYT7lrwEyBTB+DMck7TI3hN8hVRxuIEvccnOnI+Z4vhalRukpO6Pjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=nzw09OFW; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="nzw09OFW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1751543925; bh=gKPq2547ARTVgOSdR2UTZsF7CVdcjQ30QSsT719lHUk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nzw09OFWTXu/3TuoMqpbM9TjCdQHrzjw7+G/kuFF/n5jl/Np78ENvmdofx7HO+wE7 3/jgnjUWLHJMn9thJoAl8mcvL4PbxrQ4Wc97R60ZbYVbpZgDLkXaC7Ehw4jzWyMoyv FfDjD5EmpdbxHY5Y92IgllU+GiBS8a9j3sDI1U40iGLxaaS77K2Tr7Mtxgw6vHyXcR 1AaqGCcU4a8dKFrQ6LMOTiPNWunkomQ+oFrbllBa4Smnfyyn6QyttIhTv8jlp4laZh a2m4G6N2HoVNz48i65aj+8q3KXTvXN1dQEL6rOWZtNrkU/HPSuOEwQAI5aHWObv/9G OCx9RiAEO/jpQ== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7DA7117E059B; Thu, 3 Jul 2025 13:58:44 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsin-hsiung.wang@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Subject: [PATCH v2 2/5] spmi: mtk-pmif: Add multi-bus support for SPMI 2.0 Date: Thu, 3 Jul 2025 13:58:25 +0200 Message-ID: <20250703115828.118425-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703115828.118425-1-angelogioacchino.delregno@collabora.com> References: <20250703115828.118425-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In preparation for adding support for MT8196/MT6991 SoCs having multiple SPMI busses, move the bus specific parameters into a new pmif_bus structure and keep the SoC-specific data in the already existing struct pmif, and add means to register multiple SPMI controllers. While this needs a different devicetree node structure, where each of the controllers are in subnodes of a main SPMI node, and where each has its own resources (iospaces and clocks), support for the legacy single-controller was retained and doesn't require any DT change in the currently supported SoCs. Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/spmi/spmi-mtk-pmif.c | 235 +++++++++++++++++++++++------------ 1 file changed, 157 insertions(+), 78 deletions(-) diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c index 160d36f7d238..68f458587c67 100644 --- a/drivers/spmi/spmi-mtk-pmif.c +++ b/drivers/spmi/spmi-mtk-pmif.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 // // Copyright (c) 2021 MediaTek Inc. +// Copyright (c) 2025 Collabora Ltd +// AngeloGioacchino Del Regno =20 #include #include @@ -25,6 +27,7 @@ =20 #define PMIF_CHAN_OFFSET 0x5 =20 +#define PMIF_MAX_BUSES 2 #define PMIF_MAX_CLKS 3 =20 #define SPMI_OP_ST_BUSY 1 @@ -41,16 +44,22 @@ struct pmif_data { const u32 *regs; const u32 *spmimst_regs; u32 soc_chan; + u32 num_spmi_buses; }; =20 -struct pmif { +struct pmif_bus { void __iomem *base; void __iomem *spmimst_base; - struct ch_reg chan; + struct spmi_controller *ctrl; struct clk_bulk_data clks[PMIF_MAX_CLKS]; size_t nclks; + raw_spinlock_t lock; +}; + +struct pmif { + struct pmif_bus bus[PMIF_MAX_BUSES]; + struct ch_reg chan; const struct pmif_data *data; - raw_spinlock_t lock; }; =20 static const char * const pmif_clock_names[] =3D { @@ -262,33 +271,41 @@ static const u32 mt8195_spmi_regs[] =3D { [SPMI_MST_DBG] =3D 0x00FC, }; =20 -static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg) +static inline struct pmif *to_mtk_pmif(struct spmi_controller *ctrl) +{ + return dev_get_drvdata(ctrl->dev.parent); +} + +static u32 pmif_readl(struct pmif *arb, struct pmif_bus *pbus, enum pmif_r= egs reg) { - return readl(arb->base + arb->data->regs[reg]); + return readl(pbus->base + arb->data->regs[reg]); } =20 -static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg) +static void pmif_writel(struct pmif *arb, struct pmif_bus *pbus, + u32 val, enum pmif_regs reg) { - writel(val, arb->base + arb->data->regs[reg]); + writel(val, pbus->base + arb->data->regs[reg]); } =20 -static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg) +static void mtk_spmi_writel(struct pmif *arb, struct pmif_bus *pbus, + u32 val, enum spmi_regs reg) { - writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]); + writel(val, pbus->spmimst_base + arb->data->spmimst_regs[reg]); } =20 -static bool pmif_is_fsm_vldclr(struct pmif *arb) +static bool pmif_is_fsm_vldclr(struct pmif *arb, struct pmif_bus *pbus) { u32 reg_rdata; =20 - reg_rdata =3D pmif_readl(arb, arb->chan.ch_sta); + reg_rdata =3D pmif_readl(arb, pbus, arb->chan.ch_sta); =20 return GET_SWINF(reg_rdata) =3D=3D SWINF_WFVLDCLR; } =20 static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) { - struct pmif *arb =3D spmi_controller_get_drvdata(ctrl); + struct pmif_bus *pbus =3D spmi_controller_get_drvdata(ctrl); + struct pmif *arb =3D to_mtk_pmif(ctrl); u32 rdata, cmd; int ret; =20 @@ -298,8 +315,8 @@ static int pmif_arb_cmd(struct spmi_controller *ctrl, u= 8 opc, u8 sid) =20 cmd =3D opc - SPMI_CMD_RESET; =20 - mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL); - ret =3D readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_= regs[SPMI_OP_ST_STA], + mtk_spmi_writel(arb, pbus, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL); + ret =3D readl_poll_timeout_atomic(pbus->spmimst_base + arb->data->spmimst= _regs[SPMI_OP_ST_STA], rdata, (rdata & SPMI_OP_ST_BUSY) =3D=3D SPMI_OP_ST_BUSY, PMIF_DELAY_US, PMIF_TIMEOUT_US); if (ret < 0) @@ -311,7 +328,8 @@ static int pmif_arb_cmd(struct spmi_controller *ctrl, u= 8 opc, u8 sid) static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, u16 addr, u8 *buf, size_t len) { - struct pmif *arb =3D spmi_controller_get_drvdata(ctrl); + struct pmif_bus *pbus =3D spmi_controller_get_drvdata(ctrl); + struct pmif *arb =3D to_mtk_pmif(ctrl); struct ch_reg *inf_reg; int ret; u32 data, cmd; @@ -336,31 +354,31 @@ static int pmif_spmi_read_cmd(struct spmi_controller = *ctrl, u8 opc, u8 sid, else return -EINVAL; =20 - raw_spin_lock_irqsave(&arb->lock, flags); + raw_spin_lock_irqsave(&pbus->lock, flags); /* Wait for Software Interface FSM state to be IDLE. */ inf_reg =3D &arb->chan; - ret =3D readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch= _sta], + ret =3D readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->c= h_sta], data, GET_SWINF(data) =3D=3D SWINF_IDLE, PMIF_DELAY_US, PMIF_TIMEOUT_US); if (ret < 0) { /* set channel ready if the data has transferred */ - if (pmif_is_fsm_vldclr(arb)) - pmif_writel(arb, 1, inf_reg->ch_rdy); - raw_spin_unlock_irqrestore(&arb->lock, flags); + if (pmif_is_fsm_vldclr(arb, pbus)) + pmif_writel(arb, pbus, 1, inf_reg->ch_rdy); + raw_spin_unlock_irqrestore(&pbus->lock, flags); dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); return ret; } =20 /* Send the command. */ cmd =3D (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr; - pmif_writel(arb, cmd, inf_reg->ch_send); - raw_spin_unlock_irqrestore(&arb->lock, flags); + pmif_writel(arb, pbus, cmd, inf_reg->ch_send); + raw_spin_unlock_irqrestore(&pbus->lock, flags); =20 /* * Wait for Software Interface FSM state to be WFVLDCLR, * read the data and clear the valid flag. */ - ret =3D readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch= _sta], + ret =3D readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->c= h_sta], data, GET_SWINF(data) =3D=3D SWINF_WFVLDCLR, PMIF_DELAY_US, PMIF_TIMEOUT_US); if (ret < 0) { @@ -368,9 +386,9 @@ static int pmif_spmi_read_cmd(struct spmi_controller *c= trl, u8 opc, u8 sid, return ret; } =20 - data =3D pmif_readl(arb, inf_reg->rdata); + data =3D pmif_readl(arb, pbus, inf_reg->rdata); memcpy(buf, &data, len); - pmif_writel(arb, 1, inf_reg->ch_rdy); + pmif_writel(arb, pbus, 1, inf_reg->ch_rdy); =20 return 0; } @@ -378,7 +396,8 @@ static int pmif_spmi_read_cmd(struct spmi_controller *c= trl, u8 opc, u8 sid, static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 si= d, u16 addr, const u8 *buf, size_t len) { - struct pmif *arb =3D spmi_controller_get_drvdata(ctrl); + struct pmif_bus *pbus =3D spmi_controller_get_drvdata(ctrl); + struct pmif *arb =3D to_mtk_pmif(ctrl); struct ch_reg *inf_reg; int ret; u32 data, wdata, cmd; @@ -409,27 +428,27 @@ static int pmif_spmi_write_cmd(struct spmi_controller= *ctrl, u8 opc, u8 sid, /* Set the write data. */ memcpy(&wdata, buf, len); =20 - raw_spin_lock_irqsave(&arb->lock, flags); + raw_spin_lock_irqsave(&pbus->lock, flags); /* Wait for Software Interface FSM state to be IDLE. */ inf_reg =3D &arb->chan; - ret =3D readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch= _sta], + ret =3D readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->c= h_sta], data, GET_SWINF(data) =3D=3D SWINF_IDLE, PMIF_DELAY_US, PMIF_TIMEOUT_US); if (ret < 0) { /* set channel ready if the data has transferred */ - if (pmif_is_fsm_vldclr(arb)) - pmif_writel(arb, 1, inf_reg->ch_rdy); - raw_spin_unlock_irqrestore(&arb->lock, flags); + if (pmif_is_fsm_vldclr(arb, pbus)) + pmif_writel(arb, pbus, 1, inf_reg->ch_rdy); + raw_spin_unlock_irqrestore(&pbus->lock, flags); dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); return ret; } =20 - pmif_writel(arb, wdata, inf_reg->wdata); + pmif_writel(arb, pbus, wdata, inf_reg->wdata); =20 /* Send the command. */ cmd =3D (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr; - pmif_writel(arb, cmd, inf_reg->ch_send); - raw_spin_unlock_irqrestore(&arb->lock, flags); + pmif_writel(arb, pbus, cmd, inf_reg->ch_send); + raw_spin_unlock_irqrestore(&pbus->lock, flags); =20 return 0; } @@ -446,84 +465,143 @@ static const struct pmif_data mt8195_pmif_arb =3D { .soc_chan =3D 2, }; =20 -static int mtk_spmi_probe(struct platform_device *pdev) +static int mtk_spmi_bus_probe(struct platform_device *pdev, + struct device_node *node, + const struct pmif_data *pdata, + struct pmif_bus *pbus) { - struct pmif *arb; struct spmi_controller *ctrl; - int err, i; - u32 chan_offset; + int err, idx, bus_id, i; + + if (pdata->num_spmi_buses > 1) + bus_id =3D of_alias_get_id(node, "spmi"); + else + bus_id =3D 0; + + if (bus_id < 0) + return dev_err_probe(&pdev->dev, bus_id, + "Cannot find SPMI Bus alias ID\n"); =20 - ctrl =3D devm_spmi_controller_alloc(&pdev->dev, sizeof(*arb)); + ctrl =3D devm_spmi_controller_alloc(&pdev->dev, sizeof(*pbus)); if (IS_ERR(ctrl)) return PTR_ERR(ctrl); =20 - arb =3D spmi_controller_get_drvdata(ctrl); - arb->data =3D device_get_match_data(&pdev->dev); - if (!arb->data) { - dev_err(&pdev->dev, "Cannot get drv_data\n"); + pbus =3D spmi_controller_get_drvdata(ctrl); + pbus->ctrl =3D ctrl; + + idx =3D of_property_match_string(node, "reg-names", "pmif"); + if (idx < 0) return -EINVAL; - } =20 - arb->base =3D devm_platform_ioremap_resource_byname(pdev, "pmif"); - if (IS_ERR(arb->base)) - return PTR_ERR(arb->base); + pbus->base =3D devm_of_iomap(&pdev->dev, node, idx, NULL); + if (IS_ERR(pbus->base)) + return PTR_ERR(pbus->base); =20 - arb->spmimst_base =3D devm_platform_ioremap_resource_byname(pdev, "spmims= t"); - if (IS_ERR(arb->spmimst_base)) - return PTR_ERR(arb->spmimst_base); + idx =3D of_property_match_string(node, "reg-names", "spmimst"); + if (idx < 0) + return -EINVAL; =20 - arb->nclks =3D ARRAY_SIZE(pmif_clock_names); - for (i =3D 0; i < arb->nclks; i++) - arb->clks[i].id =3D pmif_clock_names[i]; + pbus->spmimst_base =3D devm_of_iomap(&pdev->dev, node, idx, NULL); + if (IS_ERR(pbus->spmimst_base)) + return PTR_ERR(pbus->spmimst_base); =20 - err =3D clk_bulk_get(&pdev->dev, arb->nclks, arb->clks); - if (err) { - dev_err(&pdev->dev, "Failed to get clocks: %d\n", err); - return err; + pbus->nclks =3D ARRAY_SIZE(pmif_clock_names); + for (i =3D 0; i < pbus->nclks; i++) { + pbus->clks[i].id =3D pmif_clock_names[i]; + pbus->clks[i].clk =3D of_clk_get_by_name(node, pbus->clks[i].id); + if (IS_ERR(pbus->clks[i].clk)) + return PTR_ERR(pbus->clks[i].clk); } =20 - err =3D clk_bulk_prepare_enable(arb->nclks, arb->clks); - if (err) { - dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err); + err =3D clk_bulk_prepare_enable(pbus->nclks, pbus->clks); + if (err) goto err_put_clks; - } =20 ctrl->cmd =3D pmif_arb_cmd; ctrl->read_cmd =3D pmif_spmi_read_cmd; ctrl->write_cmd =3D pmif_spmi_write_cmd; + ctrl->dev.of_node =3D node; + dev_set_name(&ctrl->dev, "spmi-%d", bus_id); =20 - chan_offset =3D PMIF_CHAN_OFFSET * arb->data->soc_chan; - arb->chan.ch_sta =3D PMIF_SWINF_0_STA + chan_offset; - arb->chan.wdata =3D PMIF_SWINF_0_WDATA_31_0 + chan_offset; - arb->chan.rdata =3D PMIF_SWINF_0_RDATA_31_0 + chan_offset; - arb->chan.ch_send =3D PMIF_SWINF_0_ACC + chan_offset; - arb->chan.ch_rdy =3D PMIF_SWINF_0_VLD_CLR + chan_offset; - - raw_spin_lock_init(&arb->lock); - - platform_set_drvdata(pdev, ctrl); + raw_spin_lock_init(&pbus->lock); =20 err =3D spmi_controller_add(ctrl); if (err) goto err_domain_remove; =20 + pbus->ctrl =3D ctrl; + return 0; =20 err_domain_remove: - clk_bulk_disable_unprepare(arb->nclks, arb->clks); + clk_bulk_disable_unprepare(pbus->nclks, pbus->clks); err_put_clks: - clk_bulk_put(arb->nclks, arb->clks); + clk_bulk_put(pbus->nclks, pbus->clks); return err; } =20 +static int mtk_spmi_probe(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct pmif *arb; + u32 chan_offset; + u8 cur_bus =3D 0; + int ret; + + arb =3D devm_kzalloc(&pdev->dev, sizeof(*arb), GFP_KERNEL); + if (!arb) + return -ENOMEM; + + arb->data =3D device_get_match_data(&pdev->dev); + if (!arb->data) { + dev_err(&pdev->dev, "Cannot get drv_data\n"); + return -EINVAL; + } + + platform_set_drvdata(pdev, arb); + + if (!arb->data->num_spmi_buses) { + ret =3D mtk_spmi_bus_probe(pdev, node, arb->data, &arb->bus[cur_bus]); + if (ret) + return ret; + } else { + for_each_available_child_of_node_scoped(node, child) { + if (!of_node_name_eq(child, "spmi")) + continue; + + ret =3D mtk_spmi_bus_probe(pdev, child, arb->data, + &arb->bus[cur_bus]); + if (ret) + return ret; + cur_bus++; + } + } + + chan_offset =3D PMIF_CHAN_OFFSET * arb->data->soc_chan; + arb->chan.ch_sta =3D PMIF_SWINF_0_STA + chan_offset; + arb->chan.wdata =3D PMIF_SWINF_0_WDATA_31_0 + chan_offset; + arb->chan.rdata =3D PMIF_SWINF_0_RDATA_31_0 + chan_offset; + arb->chan.ch_send =3D PMIF_SWINF_0_ACC + chan_offset; + arb->chan.ch_rdy =3D PMIF_SWINF_0_VLD_CLR + chan_offset; + + return 0; +} + static void mtk_spmi_remove(struct platform_device *pdev) { - struct spmi_controller *ctrl =3D platform_get_drvdata(pdev); - struct pmif *arb =3D spmi_controller_get_drvdata(ctrl); + struct pmif *arb =3D platform_get_drvdata(pdev); + int i; =20 - spmi_controller_remove(ctrl); - clk_bulk_disable_unprepare(arb->nclks, arb->clks); - clk_bulk_put(arb->nclks, arb->clks); + for (i =3D 0; i < PMIF_MAX_BUSES; i++) { + struct pmif_bus *pbus =3D &arb->bus[i]; + + if (!pbus->ctrl) + continue; + + spmi_controller_remove(pbus->ctrl); + clk_bulk_disable_unprepare(pbus->nclks, pbus->clks); + clk_bulk_put(pbus->nclks, pbus->clks); + } } =20 static const struct of_device_id mtk_spmi_match_table[] =3D { @@ -549,6 +627,7 @@ static struct platform_driver mtk_spmi_driver =3D { }; module_platform_driver(mtk_spmi_driver); =20 +MODULE_AUTHOR("AngeloGioacchino Del Regno "); MODULE_AUTHOR("Hsin-Hsiung Wang "); MODULE_DESCRIPTION("MediaTek SPMI Driver"); MODULE_LICENSE("GPL"); --=20 2.49.0